Apparatus for converting scan data of a keyboard

Abstract

There is disclosed a circuit for converting scan data comprising a key matrix switch having multiple keys and multiple mode selecting switches for producing scan data when one of said keys is activated, a scan decoder for decoding said scan data to produce a mode selecting signal, first scan data, second scan data, and first and second clock signals respectively synchronized with said first and second scan data, first and second latch circuits for latching said first and second scan data according to said first and second clock signals, and a mode selecting adder for converting the first and second latched output data of said first and second latch circuits into the first and second converted scan data according to the mode selecting signal of said scan decoder, whereby scan data of a different modes may be produced according to the operation of said mode selecting switches.

Description

TECHNICAL BACKGROUND

The present invention generally relates to an apparatus for producing scan data by employing a scan key matrix, and more particularly to an apparatus for converting the scan data in which the apparatus provides a variety of operational modes by using an additional mode selecting switch.

Generally, electronic machines to control the various functions thereof have a scan key matrix which enables the machines to arrange the maximum number of keys in the minimum area. Such a scan key matrix circuit usually converts into a binary data of given bits the data selected by one of the multiple keys arranged in a switch block, that is finally activated. The conventional scan key matrix circuit can produce only the scan data of the operational mode depending on the number of the cross points where the rows cross the columns in the matrix, and therefore there is caused the drawback that the number of the keys constituting the scan key matrix limits the number of the output data.

Referring to FIG. 1, the conventional scan data conversion circuit includes a key matrix 12 for producing scan data SD, a scan decoder 14 for decoding the scan data SD, and the first and the second latches 16 and 18 for latching the scan data decoded by the scan decoder 14.

The scan data output from the conventional scan data conversion circuit is transmitted to a key data processing section (not shown) to control the workings and functions of the system. When applied to a scan data conversion system, the conventional scan data conversion circuit is disadvantageous in that an additional scan data conversion circuit must be provided to expand the operational modes of the key matrix switch.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a scan data conversion circuit having a mode selecting switch in addition to the key matrix so as to convert the format of the output scan data according to the switching state of the mode selecting switch.

According to one aspect of the present invention, a circuit for converting scan data includes: a key matrix switch having multiple keys and multiple mode selecting switches for producing the scan data when one of the keys is activated; a scan decoder for decoding the scan data to produce a mode selecting signal, a first scan data, a second scan data, and a first and a second clock signals respectively synchronized with the first and second scan data; first and second latch circuits for latching the first and second scan data according to the first and second clock signals; and a mode selecting adder for converting the first and second latched output data of the first and second latch circuits into a first and second converted scan data according to the mode selecting signal of the scan decoder, whereby scan data of different modes may be produced according to the operation of the mode selecting switches.

BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:

FIG. 1 is a schematic diagram for illustrating a conventional scan data conversion circuit;

FIG. 2 is a schematic diagram for illustrating a scan data conversion circuit according to the present invention;

FIG. 3 is a detailed diagram of the option adder key of FIG. 2; and

FIG. 4 is a schematic diagram of a switch arrangement for illustrating the operational modes of an up/down switch according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described more specifically with reference to the drawings attached only by way of example. Throughout the specification, the same symbols and the equivalent part are described in the same reference numerals.

Referring to FIG. 2 for illustrating a scan data conversion circuit according to the present invention, a key matrix 12 has one key at each of the cross points where the rows cross the columns, and a given number of option switches, so as to produce the scan data SD when one of the keys is activated.

A scan decoder 14 decodes the scan data to produce a mode selecting data DD, a first scan data Ma, a second scan data Mb, and first and second clock signals LCKa and LCKb which are respectively synchronized with the first and second scan data Ma and Mb.

First and second latch circuits 16 and 18 latch the first and second scan data Ma and Mb according to first and second clock signals LCKa and LCKb.

A mode selection adder (option adder) 20 converts the first and second latched output data Ma' and Mb' first and second latch circuits 16 and 18 into the first and second scan conversion data Na' and Nb' according to the mode selecting data DD scan decoder

The first and second data Ma and Mb are binary data of n bits, and the mode selecting data DD is the data to control the scan data conversion mode (hereinafter referred to as option data), having the bit states of OP.sub.1, OP.sub.2, OP.sub.3 and up/down (U/D.sub.A, U/D.sub.B).

Referring to FIG. 3, mode selection adder 20 includes an option state determining section including multiple inverters G.sub.1, G.sub.9, G.sub.10, AND gates G.sub.2, G.sub.3, G.sub.13 and OR gate G.sub.11, first data (Ma') conversion section including multiple AND gates G.sub.4, G.sub.6, G.sub.7, G.sub.8 and OR gate G.sub.5, and second data (Mb) conversion section including multiple AND gates G.sub.12, G.sub.14, G.sub.15 and OR gate G.sub.16.

Hereinafter the operation of the inventive structure will be described. The key matrix 12 is assumed to have 7.times.6 matrix structure and the key arrangement as shown in Table 1.

TABLE 1______________________________________A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6A.sub.7 A.sub.8 A.sub.9 A.sub.10 A.sub.11 A.sub.12 A.sub.13A.sub.14 A.sub.15 U/D.sub.A X OP.sub.1 OP.sub.2 OP.sub.3B.sub.0 B.sub.1 B.sub.2 B.sub.3 B.sub.4 B.sub.5 B.sub.6B.sub.7 B.sub.8 B.sub.9 B.sub.10 B.sub.11 B.sub.12 B.sub.13B.sub.14 B.sub.15 U/D.sub.B X X X X______________________________________

Namely, it is assumed that the key matrix 12 includes group A switches A.sub.0 -A.sub.15, group B switches B.sub.0 -B.sub.15, group A up/down switch U/D.sub.A, group B up/down switch U/D.sub.B, and option switches OP.sub.1, OP.sub.2, OP.sub.3, as shown in Table 1. In this case, the option data DD produced by the scan decoder 14 is 5-bit data including the data of U/D.sub.A, U/D.sub.B, OP.sub.1, OP.sub.2, OP.sub.3 that each have a given logic level of 1 or 0. The table 2 shown below represents the states of the mode that may be selected according to the state of the option data OP.sub.1, OP.sub.2, OP.sub.3.

TABLE 2______________________________________Na' Nb' OP.sub.1 OP.sub.2 OP.sub.3______________________________________16U/D 16U/D 0 X X16 16U/D 1 0 016 16 1 0 18U/D 16U/D 1 1 08U/D 8U/D 1 1 1______________________________________

The switching state of each switching group is represented by the first and second data Ma and Mb formed of 4-bit data, whose format is presented by the data of DA.sub.3, DA.sub.2, DA.sub.1, DA.sub.0 for the first data Ma and by DB.sub.3, DB.sub.2, DB.sub.1, DB.sub.0 for the second data Mb. Hence, if the group A and B switches are used for 16 switches without operation of the up/down key, the data format will be as shown in Table 3. If the up/down key is used for each of the 16 group data, the data format is as shown in Table 4. If the up/down key is used for each of the 8 group data, the data format is as shown in Table 5. In Tables 3-5, the input data Ma' and Mb' are supplied to mode selection adder 20, while the output data Na' and Nb' are produced by mode selection adder 20.

TABLE 3______________________________________S.W. Ma DA.sub.3 DA.sub.2 DA.sub.1 DA.sub.0 HEXASTATES Mb DB.sub.3 DB.sub.2 DB.sub.1 DB.sub.0 DECIMAL______________________________________A.sub.0 B.sub.0 0 0 0 0 0HA.sub.1 B.sub.1 0 0 0 1 1HA.sub.2 B.sub.2 0 0 1 0 2HA.sub.3 B.sub.3 0 0 1 1 3HA.sub.4 B.sub.4 0 1 0 0 4HA.sub.5 B.sub.5 0 1 0 1 5HA.sub.6 B.sub.6 0 1 1 0 6HA.sub.7 B.sub.7 0 1 1 1 7HA.sub.8 B.sub.8 1 0 0 0 8HA.sub.9 B.sub.9 1 0 0 1 9HA.sub.10 B.sub.10 1 0 1 0 AHA.sub.11 B.sub.11 1 0 1 1 BHA.sub.12 B.sub.12 1 1 0 0 CHA.sub.13 B.sub.13 1 1 0 1 DHA.sub.14 B.sub.14 1 1 1 0 EHA.sub.15 B.sub.15 1 1 1 1 FHB GROUP S.W.A GROUP S.W.______________________________________ TABLE 4______________________________________INPUT Ma U/D.sub.A DA.sub.3 DA.sub.2 DA.sub.1 DA.sub.0 Mb U/D.sub.B DB.sub.3 DB.sub.2 DB.sub.1 DB.sub.0______________________________________ 0 0 0 0 0 Down 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 Up 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1______________________________________OUTPUT Na' DA.sub.4 ' DA.sub.3 ' DA.sub.2 ' DA.sub.1 ' DA.sub.0 ' Nb' DB.sub.4 ' DB.sub.3 ' DB.sub.2 ' DB.sub.1 ' DB.sub.0 '______________________________________ TABLE 5______________________________________ U/D.sub.A DA.sub.2 DA.sub.1 DA.sub.0 Ma' INPUT U/D.sub.B DA.sub.2 DA.sub.1 DA.sub.0 Mb'______________________________________0 0 0 0 0 Down0 0 0 0 10 0 0 1 00 0 0 1 10 0 1 0 00 0 1 0 10 0 1 1 00 0 1 1 10 1 0 0 0 Up0 1 0 0 10 1 0 1 00 1 0 1 10 1 1 0 00 1 1 0 10 1 1 1 00 1 1 1 1______________________________________DA.sub.4 ' DA.sub.3 ' DA.sub.2 ' DA.sub.1 ' DA.sub.0 ' Na' OUTPUTDB.sub.4 ' DB.sub.3 ' DB.sub.4 ' DB.sub.4 ' DB.sub.0 ' Nb'______________________________________

In Table 2, there are shown the operational modes of the switch according to the states of the option data OP.sub.1, OP.sub.2, OP.sub.3 of the option switch. The functions of the up/down key are more easily understood with reference to FIG. 4. For example, if the second key from the left of the drawing is pushed with the up/down key turned-on, CH.sub.1 is selected, while CH.sub.32 is selected if the key rightmost on the drawing is pushed with the up/down key turned-off.

If the first data Ma is to be in the operational mode of 16U/D, 16, 8U/D the states of the option data OP.sub.1, OP.sub.2, OP.sub.3 must be as shown in Table 2. Namely, OP.sub.1, OP.sub.1 .multidot.OP.sub.2 and OP.sub.1 .multidot.OP.sub.2 should be logic "1" respectively for 16U/D, 16 and 8U/D modes. Of course, if the second data Mb is to be in the operational modes of 16U/D, 16, 8U/D modes, the states of the option data OP.sub.1, OP.sub.2, OP.sub.3 must be as shown in FIG. 2. Namely, OP.sub.1 +OP.sub.3, OP.sub.1 .multidot.OP.sub.2 .multidot.OP.sub.3 and OP.sub.1 .multidot.OP.sub.2 .multidot.OP.sub.3 should be logic "1" respectively for 16U/D, 16 and 8U/D modes.

The OP.sub.1, OP.sub.1 .multidot.OP.sub.2, OP.sub.1 .multidot.OP.sub.2, OP.sub.1 +OP.sub.3, OP.sub.1 .multidot.OP.sub.2 .multidot.OP.sub.3, and OP.sub.1 .multidot.OP.sub.2 .multidot.OP.sub.3 are obtained respectively by inverter G9, the combination of inverter G1 and AND gate G2, AND gate G3, the combination of inverters G9, G10 and G11, the combination of inverter G1 and AND gates G2, G15, and the combination of AND gates G3 and G13.

The option keys OP.sub.1, OP.sub.2, OP.sub.3 and the up/down key of particular group are activated after pushing a desired one of the group A keys A.sub.0 -A.sub.15 and the group B keys B.sub.0 -B.sub.15 on the key matrix 12, so as to produce a corresponding scan data SD, of which the process is the same as in the conventional matrix switch. The scan data SD is decoded by scan decoder 14 to produce the first and second data Ma and Mb simultaneously with first and second clock signals LCKa and LCKb and option data DD. The first and second data Ma and Mb produced by scan decoder 14 are latched by first and second latch circuits 16 and 18, supplied to mode selection adder 20 which is applied with the up/down data U/D.sub.A and U/D.sub.B of 5-bit option data produced by scan decoder 14 and the option data OP.sub.1, OP.sub.2 and OP.sub.3 as shown in Table 2.

When the first data Ma is in the 16U/D mode, the option data DD produced by scan decoder 14 has OP.sub.1 of logic "0" and OP.sub.2 and OP.sub.3 of logic "don't care", as shown in Table 2. Hence, the output of inverter G.sub.9 is logic "1", and the logic data combine OP.sub.1 .multidot.U/D.sub.A produced by AND gate G.sub.6 is DA.sub.4 '. Further, the output data of OR gate G.sub.5 is OP.sub.1 .multidot.OP.sub.2 .multidot.U/D.sub.A +OP.sub.1 .multidot.DA.sub.3 +OP.sub.1 .multidot.OP.sub.2 .multidot.OP.sub.3, which is 0+DA.sub.3 +0, i.e. DA.sub.3. Consequently, DA.sub.2 ',DA.sub.1 ' and DA.sub.0 ' come to have respectively DA.sub.2, DA.sub.1 and DA.sub.0. Here, the data format is as shown in Table 4. If the first data Ma is 16U/D, OP.sub.1, OP.sub.2 and OP.sub.3 are respectively logic "1", "0" and "don't care". Further, DA.sub.4 ' is U/D.sub.A .multidot.OP.sub.1 that is logic "0", and DA.sub.3 ' is OP.sub.1 .multidot.OP.sub.2 .multidot.U/D.sub.A +OP.sub.1 .multidot.DA.sub.3 +OP.sub.1 .multidot.OP.sub.2 .multidot.DA.sub.3 that is DA.sub.3. Finally, DA.sub.2 ', DA.sub.1 ' and DA.sub.0 ' come to have respectively DA.sub.2, DA.sub.1 and DA.sub.0. Here, the data format is as shown in Table 3.

If the first data Ma is 8U/D, OP.sub.1, OP.sub.2 and OP.sub.3 are respectively logic "1", "1" and "don't care". Further, DA.sub.4 ' is U/D.sub.A .multidot.OP.sub.1 that is logic "0", and DA.sub.3 ' is OP.sub.1 .multidot.OP.sub.2 .multidot.U/D.sub.A +OP.sub.1 .multidot.DA.sub.3 +OP.sub.1 .multidot.OP.sub.2 .multidot.DA.sub.3 that is DA.sub.3. Finally, DA.sub.2 ', DA.sub.1 ' and DA.sub.0 come to have respectively DA.sub.2, DA.sub.1 and DA.sub.0. Here, the data format is as shown in Table 3.

If the second data Mb is 16U/D, OP.sub.1 or OP.sub.3 is logic"0", and OP.sub.2 is "don't care". Hence, the output of AND gate G12 is DB.sub.4 ' that is U/D.sub.B .multidot.(OP.sub.1 +OP.sub.3), i.e. U/D.sub.B. Further, the output of OR gate G.sub.16 is DB.sub.3 ' that is equated as follows:

DB.sub.3 '=OP.sub.1 .multidot.OP.sub.2 .multidot.U/D.sub.B .multidot.OP.sub.3 +DB.sub.3 .multidot.(OP.sub.1 +OP.sub.3) +OP.sub.1 .multidot.OP.sub.2 .multidot.DB.sub.3 .multidot.OP.sub.3 =0+DB.sub.3 +0=DB.sub.3

Finally, DB.sub.2 ', DB.sub.1 ' and DB.sub.0 ' come to have respectively DB.sub.2, DB.sub.1 and DB.sub.0. Here, the data format is as shown in Table 4.

If the second data Mb is 16U/D, OP.sub.1, OP.sub.2 and OP.sub.3 are respectively logic "1", 0" and "1" Further, DB.sub.4 ' is U/D.sub.B .multidot.(OP.sub.1 +OP.sub.3) that is 0, and DB.sub.3 ' is OP.sub.1 .multidot.OP.sub.2 .multidot.U/D.sub.B .multidot.OP.sub.3 +DB.sub.3 .multidot.(OP.sub.1 +OP.sub.3)+OP.sub.1 .multidot.OP.sub.2 .multidot.DB.sub.3 .multidot.OP.sub.3 that is DB.sub.3. Finally, DB.sub.2 ', DB.sub.1 ' and DB.sub.0 ' come to have respectively DB.sub.2, DB.sub.1 and DB.sub.0. Here, the data format is as shown in Table 5. Thus, it will be noted that the first and second data Ma and Mb of a given bit produced by the scan decoder 14 are converted by the option data U/D.sub.A, U/D.sub.B, OP.sub.1, OP.sub.2, OP.sub.3.

In the present embodiment, five options are taken for two data inputs of 4 bits, but it is self-evident that additional options may be used for the increase of the number of the data bits and inputs.

As described above, the present invention provides a circuit for obtaining a variety of key data modes without expanding the key matrix switch, and the circuit converts the input data into another given data format by operation of the mode selecting switches.

Although specific constructions and procedures of the invention have been illustrated and described herein, it is not intended that the invention be limited to the elements and constructions disclosed. One skilled in the art will easily recognize that the particular elements or subconstructions may be used without departing from the scope and spirit of the invention.

Claims

1. A circuit for converting scan data, comprising:

a key matrix having a plurality of keys and a plurality of mode selecting switches for producing the scan data when one of the keys is activated, said plurality of keys being arranged in a matrix structure;

a scan decoder for decoding said scan data to produce a mode selecting signal, first scan data, second scan data, and first and second clock signals respectively synchronized with said first and second scan data;

first and second latch circuits for latching said first and second scan data according to said first and second clock signals; and

a mode selecting adder for converting first and second latched output data of said first and second latch circuits into first and second connected data according to the mode selecting signal of said scan decoder, whereby scan data of different modes may be produced according to the operation of said mode selecting switches.

2. A can data conversion circuit as claimed in claim 1, characterized by said key matrix having a plurality of crossing rows and columns and one key at each of the cross points where said multiple rows cross said multiple columns.

3. A scan data conversion circuit as claimed in claim 1, wherein said mode selecting adder comprises:

means for receiving said first and second latched output data of said first and second latch circuits;

means for receiving said mode selecting signal of said scan decoder to determine an operational mode;

means for converting said first and second latched output data into said first converted data according to said operational mode; and

means for converting said first and second latched output data into said second converted scan data according to said operational mode.

4. The scan data conversion circuit of claim 1, wherein said mode selecting adder comprises:

option data input lines for receiving said mode selecting signal;

first input data lines for receiving said first latched output data;

second input data lines for receiving said second latched output data;

first and second converted scan data output means;

first logical operation means for connecting said option data lines, said first input data lines and said first converted scan data output means;

second logical operation means for connecting said option data lines, said second input data lines and said second converted scan data output means.

5. The scan data conversion circuit of claim 4, said option data input lines including:

first and second key state input lines;

said first key state input line connected to said first logical operation means; and

said second key state input line connected to said second logical operation means.

6. The scan data conversion circuit of claim 4, said first and second logical operation means comprises:

logic means for combining said first and second latched data with said mode selecting signal to produce said first and second converted data.