Claims
- 1. A system for economically operating a microprocessor for performing at least one task of a first class requiring a minimum decoding time and a plurality of tasks of a second class permitting a decoding time substantially greater than said minimum decoding time, comprising:
- electrical power supply means (10, 11) for supplying power to said microprocessor (12);
- electrically controllable switch means (13) having a path controlled thereby which is interposed between said power supply means (10, 11) and said microprocessor (12);
- an OR circuit (18) having its output connected for controlling said switch means (13) to connect said power supply means (10, 11) to said microprocessor (12) during the presence of a signal at any one of several inputs of said OR circuit (18), said inputs including a first input (15) for receiving signals designating requests for performance of a task of said first class, a plurality of second inputs (19, 20) for receiving signals designating requests for performance of a task of said second class, said second inputs but not said first input being connected to an input port of said microprocessor (12) for task designation decoding and monitoring by said microprocessor, and a plurality of third inputs connected respectively to a plurality of first task performance controlling outputs (21, 22) of said microprocessor, which are related to the performance of ongoing tasks of said microprocessor respectively requested through signals at said input port thereof, said microprocessor also having a plurality of second task performance controlling outputs not connected to said OR circuit, and
- a plural-state circuit (14) settable by control inputs thereof for indicating which of a plurality of tasks of said first class is being initiated when an input appears at said first input (15) of said OR circuit,
- whereby said tasks of said first class are performable only when said tasks of said second class are not being performed and are then performable quickly with the shortest possible duration of on-time of said switch means (13).
- 2. A system according to claim 1 in which said connection of said third inputs of said OR circuit to said microprocessor outputs provides a signal through the output of said OR circuit for maintaining the connection of said power supply means to said microprocessor through said switch means throughout the execution of a program of said microprocessor.
- 3. A system according to claim 1 in which said plural-state circuit (14) is connected to said power supply means for preservation of a state of said plural-state circuit while said microprocessor is disconnected from said power supply means by said switch means.
- 4. A system according to claim 3 in which said control inputs of said plural-state circuit (14) are connected to outputs of said microprocessor.
Priority Claims (1)
Number |
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2911998 |
Mar 1979 |
DEX |
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Parent Case Info
This is a continuation of application Ser. No. 124,476 filed Feb. 25, 1980 now abandoned.
US Referenced Citations (6)
Continuations (1)
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Number |
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124476 |
Feb 1980 |
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