APPARATUS FOR DETECTING SYNCHRONIZATION

Abstract

A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become readily apparent to those of ordinary skill in the art when descriptions of exemplary embodiments thereof are read with reference to the accompanying drawings.

FIG. 1 is a timing diagram of an input video signal supplied to a conventional video signal processor.

FIG. 2 is a timing diagram of a horizontal synchronization extraction signal HSP and a horizontal synchronization flag signal HSFLAG that are generated from an input video signal, such as the input video signal of FIG. 1.

FIG. 3 is a block diagram of a line-locked, phase-locked loop (PLL) used for synchronization detection according to an exemplary embodiment of the present invention.

FIG. 4 is a block diagram of a synchronization detecting apparatus according to an exemplary embodiment of the present invention.

FIG. 5 is a block diagram of a counter of FIG. 4 according to an exemplary embodiment of the present invention.

FIG. 6 is a block diagram of an error detector of FIG. 4, according to an exemplary embodiment of the present invention.

FIG. 7 is a block diagram of a line length generator of FIG. 4, according to an exemplary embodiment of the present invention.

Claims

1. A synchronization detecting apparatus comprising: a counter counting to a pre-determined counter value in response to a clock signal;an error detector generating an error, which is a difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal; anda line length generator generating a current line length based on a compensated error and the pre-determined counter value,wherein the synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.

2. The synchronization detecting apparatus of claim 1, wherein the error detector outputs an error obtained by taking a difference between the pre-determined counter value and a corrected line length that is a sum of the previous line length and a predetermined offset, and outputs an integral part and a decimal part of the corrected line length as a next synchronization start signal and offset, respectively.

3. The synchronization detecting apparatus of claim 2, wherein the error detector comprises: an offset adder combining the offset and the previous line length to generate the corrected line length;an error detection storage unit updating and storing the current counter value and the corrected line length in response to the synchronization flag signal; anda comparator comparing the current counter value stored in the error detection storage unit with the corrected line length and outputting a difference between the current counter value and the corrected line length as the error.

4. The synchronization detecting apparatus of claim 3, wherein the error detection storage unit is a flip flop.

5. The synchronization detecting apparatus of claim 1, wherein the line length generator comprises: an error compensation unit generating the compensated error based on the error and a previously compensated error; anda line length output unit outputting a difference between the counting result and the compensated error as the current line length.

6. The synchronization detecting apparatus of claim 5, wherein the error compensation unit generates the compensated error using auto regression.

7. The synchronization detecting apparatus of claim 6, wherein the compensated error=(first weight×previously compensated error+error)/second weight.

8. The synchronization detecting apparatus of claim 1 wherein the counter is reset to a difference between the pre-determined counter value and the next synchronization start signal, in response to a counter reset signal.

9. The synchronization detecting apparatus of claim 8, wherein the counter reset signal is generated when the current counter value is equal to the predetermined counter value.

10. The synchronization detecting apparatus of claim 1, further comprising a synchronization signal generator generating a synchronization signal from current counter values and line lengths which are consecutively generated in response to the synchronization flag signal.

11. The synchronization detecting apparatus of claim 1, wherein the counting result is 858 when a national television system committee method is used.

12. The synchronization detecting apparatus of claim 1, wherein the counting result is 864 when a phase alternating line method is used.

13. The synchronization detecting apparatus of claim 1 wherein the compensated error is obtained by automatic compensation of the error and the current counter value.

14. The synchronization detecting apparatus of claim 1, wherein the line length generator comprises a line-locked phase-locked loop (PLL).

15. A synchronization detecting apparatus comprising: a counter counting a scan line length between occurrences of synchronization signals of an input signal;an error detector detecting an offset between a current scan line length and a previous scan line length; anda line length generator generating a current line length based on a compensated error and a preset count value,wherein the error detector is triggered by a synchronization flag signal having an active triggering level at a transitioning edge of the synchronization signals.