1. Field of the Invention
The present invention relates to an apparatus for digital video format down-conversion with arbitrary conversion ration, and to a method therefor. The invention is applicable to the implementation of a digital video format down-conversion for use in digital video decoder. Typical applications of this invention include HDTV decoding, DVD decoder, video conferencing and picture-in-picture systems.
2. Description of the Related Art
Low-resolution digital video decoders have received considerably attention lately in academia and industry. In a digital video decoding system, the format down-conversion can be achieved by decimating the decoded full-resolution video sequences. Reconstructed video with good quality can be obtained by using this method. However, the decimation of decoded video sequences adds complexity to the full-resolution video decoding. In order to reduce the amount of computation, the memory size and other constrains such as memory bandwidth and clock rates incurred by this approach, image decimation has to be realized in the earlier stage of the decoder, for example, inside the decoding loop.
In European patent application EP0707426, a digital video decoder that provides format down-conversion with motion-compensation is disclosed. Motion compensation is achieved by first interpolating, then performing full-resolution motion compensation, and finally, decimation of the compensated output.
European patent application EP0786902A discusses a technique for changing image resolution using a direct discrete cosine transformation (DCT) mapping, whereby DCT coefficient values of an original resolution are mapped to converted coefficient values of a new resolution, without having to convert the original DCT coefficient values into pixels first.
An effective method for the digital video format down-conversion has been invented and filed in Japan on Jun. 8, 1999, entitled “A generalized orthogonal transform method for low-resolution video decoding” with application No. H11-160876, published as JP 2000-350207 and assigned to Matsushita Electric Industrial Co. Ltd.
The digital video format down-conversion method using orthogonal transform described in the prior art generates high quality down-converted video. The conversion ratio is however fixed in the methods described in the prior art. Due to the expansion and diversity of multimedia applications and present communication devices, especially the mobile terminals equipped with various resolution screens, there has been growing need for variable resolution digital video format down-conversion. The in-loop variable size video format down-decoding algorithms are required to efficiently decode high resolution encoded bitstreams and display the decoded down-sized pictures on various communication terminals with different resolutions. The problem to be solved by the current invention is to derive a set of interpolation and decimation filters using orthogonal transform with different transform sizes and establish efficient computation architectures for the interpolation and decimation filtering processes to achieve effective motion compensation for the digital video format down-conversion system with variable conversion ratio.
U.S. Pat. No. 4,768,159 discloses an efficient computation method for discrete Fourier transform. In order to solve the above-described problem, efficient computation architecture for implementing interpolation and decimation filters used by the digital video format down-conversion system is invented.
The original resolutions for encoded videos may differ from target resolution of video displayer with various ratios. Orthogonal kernels used for all the possible integer resolution ratios are invented. The orthogonal transform kernels are defined in the invention, and the selection of proper kernels for a particular resolution change is defined also. The computation architecture comprises three apparatus, namely frequency component computing means, coefficient weighting means and pixel reconstruction means. Less computational operations are required compared to the direct implementation of the orthogonal transform kernels described in the prior art.
The frequency component computing means is used to transform the input into frequency domain to generate the transform coefficients The coefficient weighting means is used for receiving transform coefficients and generating weighted transform coefficients. The weighted transform coefficients are finally transformed into spatial domain to generate the filtered pixels having different resolution from the original pixels. Said decimation/interpolation parameter generator is used to determine the integer resolution conversion ratio, 8:r, select the appropriate orthogonal kernels and generate and provide decimation/interpolation parameters to said frequency component computing means, coefficient weighting means and pixel reconstruction means.
These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings throughout which like parts are designates by like reference numerals, and in which:
The present invention is an apparatus for performing efficient motion compensation for digital video format down-conversion for motion compensation in digital video format down-conversion, which comprises:
a frequency component computing means having an input terminal for receiving a block of original pixels, transforming said original pixels into frequency domain and providing transform coefficients;
a coefficient weighting means for receiving said transform coefficient, multiplying each said transform coefficient by one of the pre-determined constant values to generate weighted transform coefficients;
a pixel reconstruction means having an input terminal for receiving said weighted transform coefficients and having an output terminal, for generating filtered pixels which have different resolution from said original pixels,
a decimation/interpolation parameter generator having a first input terminal for receiving original resolution (Ro), having a second input terminal for receiving target resolution (Rt) and having two output terminals, said decimation/interpolation parameter generator for deriving a transform kernel indicator (an integer value r), by identifying the integer value r from integer set {2, 3, 4, 5, 6, 7} such that the ratio 8:r is the most close to the resolution ratio Ro:Rt, and providing said transform kernel indicator (said integer value r) and decimation/interpolation parameters through its two output terminals;
transform kernels K1 and K2 generator having an input terminal for receiving said transform kernel indicator (said integer value r) and having two output terminals, said transform kernels K1 and K2 generator for generating orthogonal transform kernels K1[r], K2[r] from pre-determined transform kernels K1 and K2. by extracting the first r rows from K1 and first r columns from K2, respectively, characterized in that the transform kernels K1 and K2 are provided in accordance with a generalized orthogonal transformation having kernels defined as follows:
transform kernels K3 and K4 generator having an input terminal for receiving said transform kernel indicator (said integer value r) and having two output terminals, said transform kernels K3 and K4 generator for selecting orthogonal transform kernels K3[r] and K4[r] from a pool of pre-determined transform kernels K3 and K4 candidates, by choosing the transform kernels defined for resolution ratio 8:r from the pre-determined candidate kernels, characterized in that the transform kernels K3[r] and K4[r] candidates are provided in accordance with a generalized orthogonal transformation having kernels defined as follows:
The operation of the apparatus of the invention is explained.
First the operation of the computation architecture for the interpolation and decimation filtering processes is explained. The decimation/interpolation parameter generator receives the original resolution of decoded video, Ro, and target resolution of video displayer, Rt. The integer resolution conversion ratio r (8:r) is derived by identifying the integer value r from integer set {2, 3, 4, 5, 6, 7} such that the ratio 8:r is the most close to the resolution ratio Ro:Rt. The orthogonal transform kernels (K1[r], K2[r], K3[r] and K4[r]) are retrieved from a pool of pre-determined orthogonal transform kernels. The decimation/interpolation parameters are then generated and provided to the frequency component computing means, the coefficient weighting means and pixel reconstruction means. The original pixels are transformed into frequency domain by said frequency component computing means to generate the transform coefficients. Said transform coefficients are multiplied by a set of pre-determined constants by said coefficient weighting means to generate the weighted transform coefficients. The weighted transform coefficients are transformed from frequency domain into spatial domain by said pixel reconstruction means to provide filtered pixels which have different resolution from said original pixels.
Next, the operations of the frequency component computing means are explained. A reversed sequence of a block of the original pixels is generated in upper or lower address reversed order. A pair of selected pixel sequences is selected from said pixel sequence, the reversed sequence, the transform coefficients and the bit-shifted coefficient sequence by a pixel selecting means. An operation indication sequence is generated by the pixel selecting means to indicate the adding or subtracting operation. The sum or difference of said pair of selected pixel sequences is computed based on said operation indication sequence to generate said transform coefficients. Each transform coefficient is shifted by one or more bits to generate said bit-shifted coefficient sequence.
The frequency component computing means can also be operated using another method described here. The data address reversing means provides a reversed data set of a block of said original pixels in upper or lower address reversed order. A data selecting means receives said original pixels and said reversed data set to provide an operation indication set and two selected data sets. The calculator computes sum or difference of each pair of said selected data to generate processed data. One or more cascaded arithmetic units receives said processed data, manipulates them algebraically to provide said transform coefficients.
The operations of the coefficient weighting means are explained. Each transform coefficient is multiplied by one of said pre-determined constant values stored in said coefficient memory. The output of said multiplying means or said transform coefficients are switched based on a coefficient bypass control signal to provide said weighted transform coefficients. Said coefficient bypass control signal is determined based on the transform kernels used for the format down-conversion system of digital video.
The operations of said pixel reconstruction means are explained. The weighted transform coefficients are shifted by one or more bits to generate said bit-shifted vector. A pair of selected coefficient vectors is selected from said coefficient vectors said bit-shifted vector, filtered pixels and reversed pixel vector by a coefficient selecting means. An operation indication vector is generated by said coefficient selecting means to indicate the adding or subtracting operation. The sum or difference of said pair of coefficient samples is computed based on said operation indication vector to generate said filtered pixels. The reversed pixel vector of a block of filtered coefficients is generated by an address reversing means in upper or lower address reversed order.
The pixel reconstruction means can also be realized using one or More cascaded arithmetic units. The operations of the arithmetic units used for said frequency component computation means and pixel reconstruction means are now explained. The shifter shifts the input data by one or more bits to generate bit-shifted data set. The data selector receives said input data and said bit-shifted data set to provide an operation indication set and two selected data sets. A calculator adds or subtracts two selected data sets based on said operation indication.
The input terminal of the frequency component computing means can be coupled to the output terminal of the frame buffer, and the output terminal of the pixel reconstruction means can provide the interpolated pixels to the motion compensation means.
The input terminal of the frequency component computing means can be coupled to the output terminal of the motion compensation means, and the output terminal of the pixel reconstruction means can provide the decimated pixels to the adding means.
An embodiment shown in
The video bitstream 201 is first decoded by the syntax parser and variable-length decoding means 210 to obtain the decoded motion parameters 211. The frame buffer 250 stores low-resolution video pictures. The low-resolution reference pixels 251 are retrieved from the frame buffer 250 by the interpolation means 220 and interpolated to generate the interpolated pixels 221 for inverse motion compensation means 230. The inverse motion compensation means 230 performs motion compensation based on the interpolated pixels 221 and the decoded motion parameters 211 to obtain the motion-compensated pixels 231. The motion-compensated pixels 231 are then decimated by the decimation means 240 to generate decimated pixels 241.
The effect of this embodiment is that the accuracy of inverse motion compensation for down-converted video can be improved by introducing the interpolation and decimation means. Since the format down-conversion processing of each video frame introduces error, it is extremely important to control the propagation of decoding errors. The properly designed interpolation and decimation means are efficient error control engines for minimizing the error of each decoded frame.
Another embodiment shown in
The operation of this embodiment is now explained. The operation of said computation architecture for the interpolation and decimation filtering processes is now explained. The decimation/interpolation parameter generator 330 receives the original resolution of decoded video 333, Ro, and target resolution of video displayer 334, Rt. The integer resolution conversion ratio 332 r (8:r) is derived by identifying the integer value r 332 from integer set {2, 3, 4, 5, 6, 7} such that the ratio 8:r is the most close to the resolution ratio Ro:Rt. The orthogonal transform kernels (K1[r], K2[r], K3[r] and K4[r]) are retrieved from pre-determined transform kernels K1 and K2340 and a pool of pre-determined transform kernels K3 and K4 candidates 350. K1[r] and K2[r] are derived from transform kernels K1 and K2, defined in
Another embodiment shown in
and
respectively. If rdiffcurr is smaller than rdiffpast, rpast and rcuur will be assigned to rpast=rcuur and rcuur=rcuur−1, Otherwise, rcurr will be outputted as the transform kernel indicator. After assignment of rpast=rcuur and rcuur=rcuur−1 are completed, the value of rcuur is examined. If rcuur is 2, the rcurr will be outputted as the transform kernel indicator, otherwise, the rdiffcurr and rdiffpast will be re-calculated by using updated rcuur and rpast. The above process will be repeated until the transform kernel indicator (an integer value r) is obtained and outputted.
Another embodiment shown in
The operation of this embodiment is now explained. The reversed sequence 402 of a block of the original pixels 401 is generated in upper/lower address reversed order by the address reversing means 400. A pair of selected pixel sequences 412, 413 is selected from the original pixels 401, reversed sequence 402, transform coefficients 421 and bit-shifted coefficient sequence 431 by a pixel selecting means 410. An operation indication sequence 411 is also generated by the pixel selecting means 410 to indicate the adding or subtracting operation. The sum or difference of the pair of selected pixel sequences 412. 413 is computed based on the operation indication sequence 411 to generate the transform coefficients 421. Each transform coefficient 421 is shifted by one or more bits by the bit shifting means 430 to generate the bit-shifted coefficient sequence 431.
Another embodiment shown in
The operation of this embodiment is now explained. Each transform coefficient 511 is multiplied by one of the pre-determined constant values stored in the coefficient memory 500. The output of multiplying means 510 and the transform coefficients 511 are multiplexed based on a coefficient bypass control signal 522 to provide the weighted transform coefficients 521. The coefficient bypass control signal is determined based on the transform kernels used for the format down-conversion system of digital video.
Another embodiment shown in
The operation of this embodiment is now explained. The weighted transform coefficients 601 are shifted by one or more bits, by the bit shifting means 600 to generate the bit-shifted vector 602. A pair of selected coefficient vectors 612, 613 is selected from the weighted transform coefficients 601, bit-slifted vector 602 and filtered pixels 621 by the signal selecting means 610. An operation indication vector 611 is also generated by the coefficient selecting means 610 to indicate the adding or subtracting operation. The sum or difference of the selected coefficient vectors 612, 613 is computed based on the operation indication vector 611 to generate the filtered pixels 621
The immediate effect of the embodiments shown in
The embodiment shown in
The operation of this embodiment is now explained. The original pixels 701 are processed by the pre-processing means 710 to generate processed data 711. The processed data 711 is further processed by one set of cascaded arithmetic units 720 to generate the transform coefficients 721 which is the same as the transform coefficients 302 shown in
The embodiment shown in
The operation of this embodiment is now explained. The reversed data set 821 of a block of original pixels 801 is generated in upper/lower address reversed order by the data address reversing means 820. The data selector 810 chooses a pair of data 812, 813, from the original pixels 801 and the reversed data set 821, and generates an operation indicator 811. The operation indicator 811 is a binary data with one value indicating adding operation and another value indicating subtracting operation. The adder/subtracter 830 computes the sum/difference of the selected pair of data 812, 813 based on the operation indicator 811 to generate the processed data 831.
Another embodiment shown in
The operation of the nth (n≧1) arithmetic unit 910 is now explained. The input rn−1, which is the output of the (n−1)th arithmetic unit (or the output of the pre-processing means 710 if n=1), is shifted by one or more bits by a shifter 920 to generate the bit-shifted data Sn. The data selector 930 chooses a pair of data (d1n and d2n), from rn−1 and sn, and an operation indicator (opn) The operation indicator (opn) is a binary data with one value indicating adding operation and another indicating subtracting operation. The adder/subtracter 940 computes the sum/difference of d1n and d2n based on the value of opn to generate the output rn of the nth arithmetic unit 910.
The effect of the embodiments shown in
This invention produces high-quality video format down-conversion solution. The computational requirement of the invention is much less intensive than that required for the conventional low-resolution video decoding methods or the direct implementation of the digital video format down-conversion method mentioned in the prior art. The apparatus designed for interpolation filter and decimation filter are of the same architecture. The number of shifting and adding operations required by the interpolation and decimation can be reduced by 46% and 21%, respectively, for the video format down-conversion at the down-conversion ratio of 8:3.
Number | Date | Country | Kind |
---|---|---|---|
2005/279652 | Sep 2005 | JP | national |