Apparatus for driving a display panel

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an apparatus for driving a display panel such as AC driving type plasma display panel or electroluminescence display panel.

2. Description of Related Art

Recently, display apparatuses using a display panel have been put into practical use as a wall-mounted TV. Examples of such display panels are a plasma display panel, and an electroluminescence display panel, or the like in which capacitive light emitting devices are arranged in the form of a matrix.

There, however, is a problem that when pixel data pulses are applied to column electrodes of a display panel such as plasma display panel or electroluminescence display panel having the capacitive light emitting devices, a charge or a discharge is created, due to a parasitic capacitance existing between the column electrodes, by a potential difference occurring between the column electrodes, so that a reactive power is consumed.

When the number of column electrodes is increased to display a high quality television image, the number of pixel data pulses to be applied to the column electrodes also increases in accordance with the increased number of columns. When this occurs, electric power consumption also increases. A driving apparatus, therefore, which can apply the pixel data pulses to the display panel while suppressing the electric power consumption is demanded at present.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide a driving apparatus of a display panel, in which electric power consumption at the time a pixel data pulse is generated can be reduced.

According to the invention, there is provided a driving apparatus for a display panel having a plurality of row electrodes and a plurality of column electrodes arranged so as to cross the row electrodes, in which a pixel data pulse corresponding to a video signal is applied to each of the column electrodes of the display panel, comprising: a power supply circuit which comprises a capacitor, a first switching current path for selectively discharging charges stored in the capacitor and supplying them to a power line, a second switching current path for selectively applying a power potential to the power line, a third switching current path for selectively charging the charges stored on the column electrodes into the capacitor via the power line, and a fourth switching current path for selectively connecting the power line to the ground only for a short predetermined period of time; and a pixel data pulse generating circuit for generating the pixel data pulses onto the column electrodes by connecting the power line with the column electrodes only for a predetermined period of time in response to the video signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a diagram showing a schematic construction of a plasma display apparatus using a plasma display panel as a flat display panel;

FIG. 2

is a diagram showing application timings of various drive pulses to be applied to a PDP

10

in one subfield;

FIG. 3

is a diagram showing a construction of a display apparatus in which a driving apparatus according to the invention has been installed;

FIG. 4

is a diagram showing an internal construction of a column electrode driving circuit

20

;

FIG. 5

is a diagram for explaining the internal operation of the column electrode driving circuit

20

.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Prior to describing an embodiment in detail, a construction and a driving method of a conventional plasma display panel will be described in detail with reference to the drawings.

FIG. 1

is a diagram showing a schematic construction of a display apparatus using a plasma display panel.

In

FIG. 1

, a PDP

10

as a plasma display panel has row electrodes Y

1

to Y

n

and X

1

to X

n

in which a row electrode pair corresponding to each row (the first to the nth rows) of one screen is formed by a pair of X and Y. Further, column electrodes Z

1

to Z

m

corresponding to respective columns (the first to the mth columns) of one screen are formed on the PDP

10

so as to cross the row electrode pairs perpendicularly and sandwich a dielectric material layer and a discharge space (not shown). A discharge cell serving as one pixel is formed in a crossing portion of one row electrode pair (X, Y) and one column electrode Z.

Each discharge cell has only two states. A first state of “light emission” and a second state of “non-light emission” depending on whether a discharge has occurred in the discharge cell or not. That is, only the luminances of two gradations of the lowest luminance (non-light emitting state) and the highest luminance (light emitting state) can be expressed.

For the PDP

10

having the light emitting devices, a driving apparatus

100

executes a gradation driving using a subfield method in order to obtain the luminance of the halftone corresponding to a supplied video signal.

According to the subfield method, the supplied video signal is converted into corresponding pixel data of N bits every pixel and a display period of one field is divided into N subfields in correspondence to each bit digit of those N bits. The number of times of discharge execution corresponding to a weight of the subfield is allocated to each subfield. The discharge is selectively caused or initiated only in the subfield according to the video signal. In this instance, the halftone luminance corresponding to the video signal is obtained by the total (in one field display period) number of times of discharge caused in each subfield.

A selective erasure address method is known as a method of actual gradation-driving the PDP by using the subfield method.

FIG. 2

is a diagram showing application timings of various drive pulses to be applied by the driving apparatus

100

to the column electrodes and row electrodes of the PDP

10

in one subfield when the gradation driving based on the selective erasure address method is executed.

First, the driving apparatus

100

simultaneously applies a reset pulse RP

X

of a negative polarity to the row electrodes X

1

to X

n

and, further, a reset pulse RP

Y

of a positive polarity to the row electrodes Y

1

to Y

n

(all-resetting step Rc).

All discharge cells in the PDP

10

are reset-discharged in response to the applying of the reset pulses RPX and RPY and wall charges of a predetermined amount are uniformly formed in each discharge cell. All of the discharge cells are, thus, temporarily initially set to the “light emitting cells”.

The driving apparatus

100

subsequently converts the supplied video signal into pixel data of, for example,

8

bits of each pixel. The driving apparatus

100

obtains pixel data bits by dividing the pixel data every digit bit and generates a pixel data pulse having a pulse voltage according to a logic level of the pixel data bit. Pixel data pulse groups DP

1

to DP

n

corresponding to the first to nth rows are formed by grouping the pixel data pulses every row (m pulses). The driving apparatus

100

sequentially applies the pixel data pulse groups DP

1

to DP

n

to the column electrodes Z

1−m

as shown in FIG.

2

. The driving apparatus

100

generates a pixel data pulse which is at a high voltage when the pixel data bit is set to, for example, logic level “1” and at a low voltage (0 volt) when the pixel data bit is set to logic level “0”. The driving apparatus

100

further generates scan pulses SP as shown in

FIG. 2

at the applying timing of each of the pixel data pulse groups DP and sequentially applies the pixel data pulse groups to the row electrodes Y

1

to Y

n

(pixel data writing step Wc).

In this instance, a discharge (selective erasure discharge) occurs only in the discharge cells in crossing portions of the “rows” to which the scan pulse SP has been applied and the “columns” to which the high voltage pixel data pulse has been applied and the wall charges remaining in those discharge cells are selectively erased. The discharge cells initialized to the status of the “light emitting cell” in the all-resetting step Rc are, consequently, shifted to the “non-light emitting cells”. The selective erasure discharge as mentioned above is not caused in the discharge cells formed so as to cross the “rows” and “columns” to which the pixel data pulses of the low voltage have been applied, although the scan pulses SP have been applied to the discharge cells. The status initialized in the all-resetting step Rc, namely, the status of the “light emitting cells” is held.

The driving apparatus

100

subsequently repetitively applies a sustain pulse IP

X

of a positive polarity as shown in

FIG. 2

to the row electrodes X

1

to X

n

and, for a period of time during which the sustain pulse IP

X

is not applied to the row electrodes X

1

to X

n

, the driving apparatus repetitively applies a sustain pulse IP

Y

of a positive polarity as shown in

FIG. 2

to the row electrodes Y

1

to Y

n

(light emission sustaining step Ic).

In this process, only the discharge cells in which the wall charges remain, namely, only the “light emitting cells” discharge (sustain discharge) every time the sustain pulses IP

X

and IP

Y

are alternately applied. That is, only the discharge cells set to the “light emitting cells” in the pixel data writing step Wc repeat the light emission due to the sustain discharge only the number of times corresponding to the weight of this subfield and sustain the light emitting state. The number of times of applying the sustain pulses IPX and IP

Y

is the number of times which has previously been set in accordance with the weight of each subfield.

The driving apparatus

100

applies erasing pulses EP as shown in

FIG. 2

to the row electrodes Y

1

to Y

n

(erasing step E). All of the discharge cells are, consequently, allowed to erasure-discharge in a lump, thereby extinguishing the wall charges remaining in each discharge cell.

By executing the series of operations as mentioned above a plurality of times in one field, the halftone luminance corresponding to the video signal can be derived by the sense of sight.

However, there is a problem that when the pixel data pulse is applied to the column electrodes of the display panel such as a plasma display panel, electroluminescence display panel, or the like having the capacitive light emitting devices as mentioned above, the charge or discharge is caused in the parasitic capacitance existing between the column electrodes due to the potential difference which occurs between the column electrodes, so that a reactive power is consumed.

If the number of column electrodes is increased to display a high quality television image, the number of pixel data pulses to be applied to the column electrodes is also increased in response to the increase in the number of column electrodes, so that an electric power consumption also increases.

FIG. 3

is a diagram showing the structure of a display apparatus including the driving apparatus according to the invention.

In

FIG. 3

, the PDP

10

as a plasma display panel has the row electrodes Y

1

to Y

n

and X

1

to X

n

serving as row electrode pairs in which a row electrode pair corresponding to each row (the first to the nth rows) of one screen is formed by a X and Y pair. Further, the column electrodes Z

1

to Z

m

corresponding to respective columns (the first to the mth columns) of one screen are formed on the PDP

10

so as to perpendicularly cross the row electrode pairs and sandwich a dielectric material layer and a discharge space (not shown). A discharge cell serving as one pixel is formed in a crossing portion of one row electrode pair (X, Y) and one column electrode Z.

A drive control circuit

50

generates various timing signals for allowing the reset pulses RP

X

and RP

Y

, scan pulses SP, and sustain pulses IP

X

and IP

Y

as shown in

FIG. 2

to be generated and supplies them to each of row electrode driving circuits

30

and

40

. The row electrode driving circuit

30

generates the reset pulse RP

X

and sustain pulse IP

X

in response to the timing signals and supplies them to the row electrodes X

1

to X

n

of the PDP

10

at the timings as shown in

FIG. 2

, respectively. The row electrode driving circuit

40

generates the reset pulse RP

Y

, scan pulse SP, sustain pulse IPY, and erasing pulse EP in response to the various timing signals supplied from the drive control circuit

50

and supplies them to the row electrodes Y

1

to Y

n

of the PDP

10

at the timings as shown in

FIG. 2

, respectively.

Further, the drive control circuit

50

converts the supplied video signal into pixel data of, for example,

8

bits every pixel, divides the pixel data every digit bit, extracts the data bits corresponding to each of the first to nth rows for every row (m bits), and supplies the extracted data bits as pixel data bits DB

1

to DB

m

to the column electrode driving circuit

20

. In this instance, the drive control circuit

50

generates switching signals SW

1

to SW

4

for generating the pixel data pulses according to the pixel data bits DB and supplies the pixel data pulses to a column electrode driving circuit

20

.

FIG. 4

is a diagram showing an internal structure of the column electrode driving circuit

20

.

As shown in

FIG. 4

, the column electrode driving circuit

20

includes a power supply circuit

21

and a pixel data pulse generating circuit

22

.

One end of a capacitor C

1

in the power supply circuit

21

is connected to a PDP grounding potential Vs as a grounding potential of the PDP

10

. A switching device S

1

is turned off when the switching signal SW

1

at the logic level “0” is supplied from the drive control circuit

50

. When the logic level of the switching signal SW

1

is set to “1”, the switching device S

1

is turned on, thereby allowing an electric potential developed at the other end of the capacitor C

1

to be applied onto a power line

2

via a coil L

1

and a diode D

1

. The capacitor C

1

, thus, starts to discharge and an electric potential developed by this discharge is applied to the power line

2

. A switching device S

2

is turned off when the switching signal SW

2

at the logic level “0” is supplied from the drive control circuit

50

. When the logic level of the switching signal SW

2

is set to “1”, the switching device S

2

is turned on, thereby allowing the electric potential on the power line

2

to be applied to the other end of the capacitor C

1

via a coil L

2

and a diode D

2

. In this instance, the capacitor C

1

is charged by the electric potential on the power line

2

. A switching device S

3

is turned off when the switching signal SW

3

at the logic level “0” is supplied from the drive control circuit

50

. When the logic level of the switching signal SW

3

is set to “1”, the switching device S

3

is turned on, thereby allowing a power potential Va derived from a DC power source B

1

to be applied onto the power line

2

. A negative terminal of the DC power source B

1

is connected to the PDP grounding potential Vs. A switching device S

4

is turned off when the switching signal SW

4

at the logic level “0” is supplied from the drive control circuit

50

. When the logic level of the switching signal SW

4

is set to “1”, the switching device S

4

is turned on, thereby connecting the power line

2

to the PDP grounding potential Vs.

Switching devices SWZ

1

to SWZ

m

and SWZ

10

to SWZ

m0

which are independently on/off controlled in accordance with the (m) pixel data bits DB

1

to DB

m

of one row supplied from the drive control circuit

50

are provided for the pixel data pulse generating circuit

22

, respectively. Each of the switching devices SWZ

1

to SWZ

m

is turned on only when each pixel data bit DB supplied thereto is set to logic level “1” and applies the electric potential developed on the power line

2

to each of the column electrodes Z

1

to Z

m

of the PDP

10

. Each of the switching devices SWZ

10

to SWZ

m0

is turned on only when each pixel data bit DB supplied thereto is set to logic level “0”, and connects the electric potential on the column electrodes to the PDP grounding potential Vs.

FIG. 5

is a diagram showing internal operation waveforms of the column electrode driving circuit

20

.

When a load in the PDP

10

is large, namely, when the pixel data pulses of high voltage are continuously applied to the column electrodes Z

i

(i=1 to m), as shown in the part B of

FIG. 5

, the switching devices SWZ

i

(i=1 to m) are turned on and the switching devices SWZ

i0

(i=1 to m) are turned off.

The drive control circuit

50

supplies the switching signals SW

2

to SW

4

of logic level “0” and the switching signal SW

1

of the logic level “1” to the power supply circuit

21

(driving step G

1

).

Only the switching device S

1

among the switching devices S

1

to S

4

is, thus, turned on and the charges stored in the capacitor C

1

are discharged. A current, therefore, flows to the column electrodes Z

i

via the coil L

1

, diode D

1

, switching device S

1

, and switching devices SWZ

i

and a load capacitor C

0

is charged. In this instance, an electric potential of the column electrode Z

i

gradually rises as shown in the part B of

FIG. 5

according to a time constant which is determined by the coil L

1

and load capacitor C

0

.

When the half period of a resonance period due to the coil L

1

and load capacitor has elapsed, the drive control circuit

50

switches only the switching signal SW

3

to logic level “1” (driving step G

2

). The switching device S

3

is, thus, turned on, the power potential Va by the DC power source B

1

is applied onto the power line

2

, and the potential of the column electrode Z

i

is fixed to the power potential Va.

The drive control circuit

50

subsequently switches the switching signal SW

1

to logic level “0” (driving step G

3

). The switching device S

1

is, thus, turned off, the resonance operation by the coil L

1

and load capacitor C

0

is stopped.

The drive control circuit

50

subsequently switches the switching signal SW

2

to logic level “1” and switches the switching signal SW

3

to logic level “0” (driving step G

4

). The charges stored in the load capacitor C

0

are thus discharged. A current, consequently, flows to the capacitor C

1

via the switching device SWZ

i

, coil L

2

, diode D

2

, and switching device S

2

and the capacitor C

1

is charged. In this instance, the potential of the column electrode Z

i

gradually decreases as shown in the part B of

FIG. 5

according to a time constant which is decided by the coil L

2

and load capacitor C

0

.

When the half period of the resonance period due to the coil Ll and load capacitor has elapsed, the drive control circuit

50

supplies the switching signal SW

4

of logic level “1” of a short pulse to the power supply circuit

21

in order to turn on the switching device

54

only for a short predetermined period (driving step G

5

).

The power line

2

is, thus, connected to the PDP grounding potential Vs only for the short period of time. In this instance, although the current is supplied from the PDP

10

to the switching device S

4

via the switching device SWZ

i

and power line

2

, the ON period of the switching device S

4

is set to be short so as to limit the current flowing into the switching device S

4

lest the potential on the power line

2

completely drops to 0 [V]. As shown in the part B of

FIG. 5

, an amplitude Vf of the potential waveform on the power line

2

is smaller than that in the case where the load is small, namely, the case where the pixel data pulses of the high voltage are discontinuously applied to the column electrode Z

i

.

By the series of operations comprising the driving steps G

1

to G

5

, the power supply circuit

21

generates a power potential having a potential fluctuation as shown in the part B of FIG.

5

and continuously applies it as a high voltage pixel data pulse to the column electrode Z

i

via the power line

2

and switching device SWZ

i

.

As mentioned above, when the load in the PDP

10

is large, the current flowing into the switching device S

4

is limited lest the potential on the power line

2

completely drops to 0 [V] and the amplitude of the potential change that is caused on the power line

2

is reduced, thereby enabling the electric power consumption to be reduced.

When the load in the PDP

10

is small, namely, when the high voltage pixel data pulses are discontinuously applied to the column electrode Z

i

, the power potential having a potential fluctuation as shown in the part A of

FIG. 5

is generated.

When the pixel data bit DB is at logic level “1”, the switching device SWZ

i

of the pixel data pulse generating circuit

22

is turned on and the switching device SWZ

i0

is turned off. When the pixel data bit DB is at logic level “0”, the switching device SWZ

i

of the pixel data pulse generating circuit

22

is turned off and the switching device SWZ

i0

is turned on.

When the pixel data bit DB is switched from logic level “1” to logic level “0”, the switching device SWZ

i0

is turned on, the column electrode Z

i

is connected to the ground, and the potential of the column electrode Z

i

is fixed to 0 [V].

When the pixel data bit DB is switched from logic level “0” to logic level “1”, the switching device SWZ

i

is turned on and the switching device SWZ

i0

is turned off.

Simultaneously with the turn-on of the switching device SWZ

i

, only the switching device S

1

is turned on, and the charges stored in the capacitor C

1

are discharged. As a result, the current flows to the column electrode Z

i

via the coil L

1

, diode D

1

, switching device S

1

, and switching device SWZ

i

and the load capacitor C

0

is charged. In this process, the electric potential of the column electrode Z

i

gradually rises as shown in the part A of

FIG. 5

according to a time constant which is determined by the coil L

1

and load capacitor C

0

.

When the half period of the resonance period due to the coil L

1

and load capacitor has elapsed, the switching signal SW

3

is turned on, the power potential Va by the DC power source B

1

is applied to the power line

2

, and the potential of the column electrode Z

i

is fixed to the power potential Va.

Subsequently, the switching device S

1

is turned off and the resonance operation by the coil L

1

and load capacitor C

0

is stopped.

The drive control circuit

50

subsequently turns on the switching device S

2

and turns off the switching device S

3

. The charges stored in the load capacitor C

0

are discharged. The current, therefore, flows to the capacitor C

1

via the switching device SWZ

i

, coil L

2

, diode D

2

, and switching device S

2

and the capacitor C

1

is charged. In this instance, the electric potential of the column electrode Z

i

gradually decreases as shown in the part B of

FIG. 5

according to a time constant which is determined by the coil L

2

and load capacitor C

0

.

Subsequently, when the half period of the resonance period due to the coil L

1

and load capacitor has elapsed, the switching device S

4

is turned on only for a short predetermined period of time and the switching device SWZ

i0

is turned off.

The discontinuous pixel data pulses are applied to the column electrodes Z

i

by the above series of operations.

As mentioned above, when the current is large, the power supply circuit

21

first selectively discharges the charges stored in the capacitor C

1

by a first switching current path comprising the coil L

1

, diode D

1

, and switching device S

1

and supplies (driving step G

1

) them to the power line

2

, thereby forming a leading edge portion of the pixel data pulse. Subsequently, the power potential is applied (driving step G

3

) to the power line

2

by a second switching current path comprising the DC power source B

1

and switching device S

3

, thereby generating the pulse voltage (Va) of the pixel data pulse. Subsequently, the charges stored in the load capacitor C

0

existing in the column electrode are selectively charged into the capacitor C

1

via the power line

2

and collected (driving step G

4

) by a third switching current path comprising the coil L

2

, diode D

2

, and switching device S

2

, thereby forming a trailing edge portion of the pixel data pulse. Finally, the power line

2

is forcedly connected to the ground only for a short predetermined period (driving step G

5

) by the switching device S

4

as a fourth switching current path, thereby deciding the lowest potential as a pixel data pulse.

According to the invention as described in detail above, by collecting the charges stored in the display panel via the power line, the trailing edge portion of the pixel data pulse is formed and, further, by using the collected charges, the leading edge portion of the pixel data pulse is formed. In this instance, the lowest potential of the pixel data pulse is determined by forcedly connecting the power line to the ground only for a short period of time.

According to the apparatus for driving a display panel according to the invention, when the pixel data pulse is generated, the main charging/discharging operations between the parasitic capacitors existing in the column electrodes and the surplus current flowing from the display panel to the driving apparatus side are suppressed, so that the electric power consumption is reduced.

Number	Name	Date
5517207	Kawada et al.	May 1996
5739641	Nakamura	Apr 1998
5943030	Minamibayashi	Aug 1999
6072447	Noborio	Jun 2000
6215463	Matsumoto et al.	Apr 2001

Apparatus for driving a display panel

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (1)

US Referenced Citations (5)