Apparatus for driving light-emitting display

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to an apparatus for driving a light-emitting display constructed of light-emitting elements such as organic EL elements and light-emitting diodes.

[0003] 2. Description of the Related Art

[0004] Where an image is displayed on the light-emitting display, each light-emitting element must be illuminated with the luminance corresponding to the luminance value of each of pixels of an image signal.

[0005] The technique for illuminating each light-emitting element with the luminance corresponding to the luminance value of the pixel includes an analog method and a time-divisional method.

[0006] The analog method is to vary the driving current of illuminating the light-emitting element according to the luminance value. The time-divisional method is to turn on/off the driving current, which is maintained constant, according to the luminance value, thereby varying its “ON” time.

[0007] The analog method requires linearity at high accuracy in order to vary the driving current according to the luminance value. Therefore, the analog method has a disadvantage that a driving section is up-sized and the value of the driving current varies according to a temperature.

[0008] On the other hand, in the time-divisional method in which requires a constant current to be produced, the driving section is down-sized and has a good temperature characteristic.

[0009] Now referring to FIG. 8, an explanation will be given of a driving apparatus in a time-divisional system.

[0010] In FIG. 8, reference numeral 50 denotes a frame memory for storing an image signal (pixel data) corresponding to its one frame; 51 a pattern memory; 52 a read section; 53 a driving section for producing a constant driving current; and 54 a light-emitting display.

[0011] For simplicity of explanation, the explanation will be made for a single pixel.

[0012] The read section 51 reads the pixel data stored in the frame memory in a frame period.

[0013] The luminance value of the pixel data is represented by a binary number of k (2k). Specifically, where k=8, the luminance is represented by 256 levels.

[0014] The pattern memory 51 stores schedule data (pattern information) for turning on the driving section 53 for the pixel data read by the read section 50.

[0015]
FIG. 12 shows a concrete example of the contents of the pattern memory 51 where k=3.

[0016] The addresses of the pattern memory 51 are correlated with the pixel data read from the frame memory 50. The pattern information is recorded as the bit information of 2k−1.

[0017] Namely, where k=3, the address is represented by 3 bits and the pattern information is represented by 7 bits.

[0018] For example, as seen from FIG. 12, where the address is ‘000’, the pattern information is ‘0000000’, and where the address is ‘001’, the pattern information is ‘1000000’. Likewise, the pattern information will be previously stored as seen from FIG. 12.

[0019] Using the addresses of the pixel data read from the frame memory 50, the read section 52 reads the pattern information stored in the pattern memory 51 and sequentially sends it to the driving unit 53 in a period of 1/(2k−1) of the frame period.

[0020] Where the signal sent from the read section 52 is “1”, the driving section 53 supplies a constant current to the light-emitting display 54, whereas the signal sent from the read section 52 is “0”, the driving section 53 stops supply of the current.

[0021] Generally, the image data has the luminance values of 8 bits or larger, i.e. 2k−1=255 level or larger. In this case, the pattern memory requires 256 addresses and memory capacity of 255 bits.

[0022] In the conventional apparatus for driving a light-emitting display in a time-divisional manner, where the image signal is represented by a binary number of k, the driving section 53 is on/off controlled in a period of 1/(2k−1) of the frame period, thereby requiring a high speed operation.

SUMMARY OF THE INVENTION

[0023] An object of this invention is to provide an apparatus for driving a light-emitting display which drives a driving section at a driving rate lower than e.g. (2k−1)f and equivalently provides the number of levels corresponding to 2K in a frequency band lower than fF/2 which is a reproduction band of a moving image, i.e. Nyquist band.

[0024] In order to the above object, in accordance with an aspect of this invention, there is provided a driving apparatus for a light-emitting display which controls the light-emission of M number of light-emitting elements in such a manner that a driving current or driving voltage is turned on or off by an on/off signal supplied through a driving unit, comprising:

[0025] a pixel read section for reading the luminance values for the light-emitting elements in a frame period from an image signal; and

[0026] a ΔΣ modulator which operates in a sub-frame period which is 1/n of the frame period according to the luminance values read by the pixel read section,

[0027] wherein an output of “1” or “0” from ΔΣ modulator is supplied to the driving unit as the on/off signal.

[0028] In this configuration, the luminance value of the pixel is subjected to the ΔΣ modulation, and the driving current or the driving voltage is turned on/off using the output from the ΔΣ modulator. For this reason, even if the on/off frequency of the driving current or driving voltage is lowered, a necessary S/N ratio can be assured within a reproduction frequency band of an image.

[0029] In order to the above object, in accordance with another aspect of this invention, there is provided a driving apparatus for a light-emitting display which controls the light-emission of M number of light-emitting elements in such a manner that a driving current or driving voltage is turned on or off by an on/off signal supplied through a driving unit, comprising:

[0030] a pixel read section for reading the luminance values of the light-emitting elements in a frame period from an image signal;

[0031] a ΔΣ modulator which operates in a sub-frame period which is 1/n of the frame period according to the luminance values read by the pixel read section; and

[0032] a random data generator for generating random luminance values of individual pixels,

[0033] wherein in an image displaying operation, the output from the random data generator is directly supplied to the ΔΣ modulator in place of the output from the pixel read section, or otherwise added to the output from the pixel read section.

[0034] Where the random luminance values are supplied to the ΔΣ modulator when the driving apparatus is started, the blinking of the display can be prevented.

[0035] The above and other objects and features of this invention will be more apparent from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036]
FIG. 1 is a block diagram of a basis construction of this invention;

[0037]
FIG. 2 is a block diagram of another basic construction of this invention;

[0038]
FIG. 3 is a block diagram of a ΔΣ modulator according the first embodiment of this invention;

[0039]
FIGS. 4A and 4B are views each for explaining the period while a driving current is turned on/off;

[0040]
FIG. 5 is a view for explaining a sample-and-hold section according to the second embodiment of this invention;

[0041]
FIGS. 6A and 6B are block diagrams of ΔΣ modulators according to the third embodiment of this invention;

[0042]
FIG. 7 is a schematic diagram of a random value generator;

[0043]
FIG. 8 is a block diagram of a ΔΣ modulator according to the fourth embodiment of this invention;

[0044]
FIG. 9 is a block diagram of a ΔΣ modulator according to a modification of the fourth embodiment of this invention;

[0045]
FIG. 10 is a graph showing the noise component;

[0046]
FIG. 11 is a block diagram of a prior art driving apparatus for a light-emitting display; and

[0047]
FIG. 12 is a view of a concrete example of the contents of a pattern memory in the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] Referring to FIG. 1 showing a block diagram of a basic construction of the invention, an explanation will be given of various embodiments of this invention.

[0049] In FIG. 1, reference numeral 1 denotes a frame memory in which pixel data are stored in a frame period; 2 a pixel read section which reads pixel data (luminance value) from the frame memory; 3 a ΔΣ modulator; and 4 a driving section for supplying a constant driving current or voltage to light-emitting elements constituting pixels of a light-emitting display 5.

[0050]
FIG. 2 is a block diagram of another basic construction of this invention. As seen, a random memory 6 which stores random luminance values is added to the construction of FIG. 1. In FIG. 2, like reference numeral refers to like units in FIG. 1.

[0051] The pixel read section 2 reads the pixel data from the frame memory 1 in synchronism with the frame pulse fF repeated in a frame period. The read of the random luminance values stored in the random memory 6 will be explained later.

[0052] The driving section 4 on/off controls the driving current or voltage on the basis of a “1” or “0” signal which is produced from the ΔΣ modulator.

[0053]
FIG. 3 is a block diagram of the ΔΣ modulator according to the first embodiment of this invention.

[0054] In FIG. 3, reference numeral 31 denotes an addition unit; 32 and 34 denote a first and a second delay unit for delaying input pixel data by the time TD which is 1/n of the frame period (1/n·fF (fF is a frequency of the frame pulse) ; and 33 denotes a decision unit which produces a positive prescribed value if the output value from the addition unit 31 is a prescribed or larger value and produces a negative prescribed value if the output value is smaller than the prescribed value.

[0055] The first delay unit 32 delays the output from the addition unit 31. The addition unit 31 performs an addition of the delayed output and the input pixel data.

[0056] The output from the decision unit 33 is delayed by the second delay unit 34. The delayed output is subjected to subtraction by the addition unit 31.

[0057] The output to be supplied to the driving unit 4 produces a sign bit (if positive, “1”, and if negative, “0”) which represents the positive/negative of the signal produced from the decision unit 33.

[0058] An explanation will be given of the operation of the the ΔΣ modulator according to the first embodiment shown in FIG. 3.

[0059] For the period of a single frame, the pixel read section 2 supplies the pixel data to the addition unit 31. Subsequently, for the period of a next single frame, the pixel read section 2 supplies the pixel data (luminance value) at the same position in the next frame to the pixel read section 2.

[0060] The addition unit 31 adds the output value from the first delay unit 32 to the pixel data thus supplied. The addition unit 31 subtracts the output value from the second delay unit 34. The addition unit 31 sends the resultant output to the decision unit 33 which makes a decision of positive or negative.

[0061] The output from the addition unit 31 is delayed by TD (= 1/n·fF) and the delayed output is sent back to the addition unit 31. The prescribed value outputted from the decision unit 33 is delayed by a time TD, and the delayed output is sent back to the addition unit 31.

[0062] Therefore, the output from the addition unit 31 is changed for each of TD times. The changed addition result is decided by the decision unit 33. The sign bit which is the decision result is supplied to the driving unit 4 to turn on/off the driving current.

[0063] In this way, the control signal for on/off controlling the driving current for each of n-divided sub-frames is determined by the output value resulting from ΔΣ-modulation for each sub-frame of the luminance data for each frame of each pixel. For this reason, even when “n” is made smaller than 2k−1, a necessary S/N ratio is assured within a Nyquist band of fF/2. This prevents the quality of the reproduced image from being attenuated.

[0064] As regards the image signal of a single pixel, the Nyquist band defined by ½ of the frame frequency is DC˜fF/2. The fact that the signal component within this frequency band has levels of 2k means that the quantity of the noise component within the frequency band is not larger than 1/{square root}2·2k.

[0065] When it is intended that the level is equivalently represented for each of sub-frames time-divided from the one frame period, the number n of time division must be generally 2k−1 or larger. In this case, as shown by {circle over (1)} in FIG. 10, the noise component which is a difference between an original signal and a reproduced signal has an amplitude of 1/{square root}2·2k and its frequency band extends ranges from DC˜n·fF/2.

[0066] If the number n of the divided sub-frames is smaller than 2k−1, the noise level rises as shown by {circle over (2)} in FIG. 10 so that the necessary S/N ratio cannot be assured.

[0067] Now where the signal processing is carried out by the ΔΣ-modulator with n<2k−1, the spectrum of noise is shifted toward the higher frequency as shown by {circle over (3)} in FIG. 10. If attention is paid to only the frequency band of DC˜fF, the noise level can be reduced to not lower than 1/{square root}2·2k according to the value of n.

[0068] The function of {circle over (3)} in FIG. 10 can be acquired from the equation of z-transform (the delay circuit can be represented by multiplication of a coefficient of z−1). Specifically, assuming in FIG. 3 that the input is X, the output is Y and the noise component added by the addition unit is Q,

Y=
(X−z−1Y){1/(1−z−1)}+Q

[0069] Therefore,

Y=X+Q
(1−z−1)

[0070] Since the noise component Q is multiplied by (1−z−1) it is similar to differentiation. This result in a characteristic which rises toward the higher frequency band with no DC component.

[0071] The secondary order ΔΣ modulator provides

Y=X+Q
(1−z−1)

[0072] This exhibits the second-order differentiation characteristic, thereby providing a more abrupt shifting effect.

[0073] In the prior art, as shown in FIG. 4A, where the luminance value is composed of k bits, the driving current is on/off controlled for each of 2k−1 sub-frames divided from the frame period (1/fF). On the other hand, in the first embodiment, as seen from FIG. 4B, the driving current is on/off controlled for each of n sub-frames divided from the frame period.

[0074] Now referring to FIG. 5, an explanation will be given of the second embodiment of this invention.

[0075] In the first embodiment, the signal (pixel value) was delayed using the first delay unit 32 and the second delay unit 34, whereas in the second embodiment, these delay units is replaced by a sample-and-hold unit (S/H) 32′ (34′) as shown in FIG. 5.

[0076] The S/H unit 32′ holds and outputs an input value whenever a sampling pulse is received. Therefore, if the frequency of the sampling pulse is set at the frequency which is n-times of the frequency fF of the frame pulse, i.e. n·fF, the pixel data can be delayed like the first delay unit 32 and second delay unit 34.

[0077] Referring to FIGS. 5A and 5B, an explanation will be given of the third embodiment.

[0078] In the first embodiment, as shown in FIG. 3, the first-order ΔΣ modulator was used. In this embodiment, a second-order ΔΣ modulator as shown in FIG. 5A or a third-order ΔΣ modulator as shown in FIG. 5B is used.

[0079] As shown in FIG. 6A, the second-order ΔΣ modulator is constructed so that a second addition unit 41 and a third delay unit 42 are cascade-connected between the addition unit 31 and the decision unit 33 in the first-order ΔΣ modulator explained with reference to FIG. 1.

[0080] The second addition unit 41 makes the same operation as the addition unit 31. The delay time is set at the same time as that of the first delay unit 32 and the second delay unit 34.

[0081] As shown in FIG. 6B, the third-order ΔΣ modulator is constructed so that a third addition unit 43 and a fourth delay unit 44 are cascade-connected between the second addition unit 41 and the decision unit 33 in the second-order ΔΣ modulator.

[0082] By raising the order of the ΔΣ modulator, the distribution of the noise component can be shifted toward the high frequency region so that the S/N ratio in the low frequency region is increased and naturalness of the displayed image can be further improved.

[0083] Returning to FIG. 2, an explanation will be given of the read of random pixel data stored in the random memory 6 by the pixel read section 2.

[0084] In the driving apparatus for a light-emitting display explained with reference to FIGS. 1 to 6, when the power is turned on, the outputs from the addition unit 31, 41 or 43 in the ΔΣ modulator 3 are 0 for all the pixels.

[0085] Therefore, where the pixel data inputted when the power is turned on is an image with random luminance values, no problem occurs. On the other hand, where the major part within a screen is occupied by pixels with low and equal luminance values, the period of the ON signals produced from the ΔΣ modulator is long and the ON signals are in phase between the pixels with equal phases because the outputs from the addition unit 31, 41 or 43 while the power is on.

[0086] Where the respective pixels on the light-emitting display are driven by the ON signals with the long period and in phase, the display emits light as if it were blinking.

[0087] In order to avoid such phenomenon of blinking, when the driving apparatus is started, the pixel read section 2 reads the luminance values of the pixels stored in the random memory 6 and supplies them to the ΔΣ modulator 3.

[0088] The random memory 6 has a capacity capable of the storing the luminance values of all the pixels and provides the pixels with random luminance values previously.

[0089] Therefore, by reading the luminance values stored in the random memory 6 when the driving apparatus is started, the output values of the addition unit 31 or the addition units 41 and 43 are different between the adjacent pixels. As a result, the timings of producing the ON signals from the decision unit 33 of the ΔΣ modulator 3 are random so that the above phenomenon of blinking does not occur.

[0090] Incidentally, the pixels read section 2 may read the random luminance values generated from a random value generator in place of the random memory 6 storing the random values.

[0091]
FIG. 7 shows a concrete example of a random generator 7.

[0092] The random value generator 7 includes e.g. an R-stage shift register 7A and an exclusive OR (EX/OR) 7B.

[0093] The outputs at an intermediate and a final stage of the shift register 7A are supplied to the EX/OR 7B, and the output from the EX/OR 7B is supplied to the first stage of the shift register 7A.

[0094] When a shift pulse is supplied to the shift register 7A, the data of “1” or “0” is shifted according to the shift pulse. Thus, data in a random time series which are repeated at the period of (2R−1) bits are obtained from the output from the shift resister 7A.

[0095] Therefore, the read from the random memory 6 can be replaced by the read of the necessary bits of the random signal which is produced from the shift register 7A.

[0096] Referring to FIG. 8, an explanation will be given of the fourth embodiment of this invention.

[0097] In the first to third embodiments, the ΔΣ modulator was provided for each of the pixels. In this embodiment, a ΔΣ modulator is provided commonly for M pixels so that it performs a time-divisional operation.

[0098] In FIG. 8, reference numeral 11 denotes a M pixel read section which sequentially reads the luminance values of the M pixels in synchronism with the read pulse at a frequency of nM·fF and supplies them to the addition section 31.

[0099] Reference numerals 12 and 13 denote a first and a second read/write section which are provided with a memory 12a and a memory 13a which store M pieces of data corresponding to the M pixels, respectively.

[0100] Reference numeral 33 denotes a decision section whose output is connected to a separation section.

[0101] The first and the second read/write section 12 and 13 perform the read/write operation in synchronism with the read/write pulse at the frequency of nM·fF which is the same as the read pulse for the M pixel read section 11.

[0102] Specifically, the first and the second read/write section 12 and 13 read, from the memories 12a and 13a, the data corresponding to the pixels supplied to the addition section 31 from the M pixel read section 11 and supply them to the addition section 31. These data are added in the addition section 31.

[0103] In operation, in response to the read/write pulse, the first read/write section 12 writes the output value from the addition section 31 in the corresponding memory and also read the stored data corresponding to the pixels read by the M pixel read section 11 which are supplied to the addition section 31.

[0104] Like the first read/write section, the second read/write section 13 writes the output value from the decision section 33 and reads the stored-data corresponding to the subsequent pixels which are supplied to the addition section 31.

[0105] A separating section 14 connects the output from the decision section 33 to driving units 3.1-3.M corresponding to the pixels read by the M pixel read section 11, and on/off controls the driving current for the driving units 3.1-3.M.

[0106] In FIG. 8, although M pixels are commonly used in the first-order ΔΣ modulation, the higher-order modulation may be carried out.

[0107] Where the M pixels are caused to correspond to the M pixels constituting the row or column of the light-emitting display, the number of the ΔΣ modulators can be reduced, and the driving units can be operated at a relative low speed.

[0108]
FIG. 9 shows a modification of the fourth embodiment of this invention. This modification is different from the fourth embodiment in that a random memory 12b which will be described below is added.

[0109] As described above, in order to remove the blinking of the light-emitting display 5, when the driving apparatus is started, the pixel read section 2 read the random luminance values from the random memory 6 or the random value generator 7 shown in FIG. 7.

[0110] The random memory 12b which stores the random values performs an alternative method to this method. Namely, when the driving apparatus is started, the first read/write section 12b reads the random luminance values stored in the random memory and supplies them to the addition unit 31.

[0111] More specifically, the random values read from the M pixel read section 11 are not supplied to the addition unit 31, but the random values read from the random memory 12 by the first read/write section 12 are supplied to the addition unit 31.

[0112] Incidentally, the random memory 12b may be connected to the second read/write section 13. In this case also, likewise, the random values read therefrom can be supplied to the addition unit 31.

[0113] In this modification, the random value generator 7 explained with reference to FIG. 7 may be used instead of the random memory 12b. In this case also, the random values read from the random value generator 7 by the first read/write section 12 or the second read/write section 13 are supplied to the addition unit 31.

[0114] Effects of the Invention

[0115] As understood from the description hitherto made, in accordance with this invention, the luminance value of the pixel is subjected to the ΔΣ modulation, and the driving current or the driving voltage is turned on/off using the output from the ΔΣ modulator. For this reason, even if the on/off frequency of the driving current or driving voltage is lowered, a necessary S/N ratio can be assured within a reproduction frequency band of an image.

[0116] Where the random luminance values are supplied to the ΔΣ modulator when the driving apparatus is started, the blinking of the display can be prevented.

Claims

1. A driving apparatus for a light-emitting display which controls the light-emission of M number of light-emitting elements in such a manner that a driving current or driving voltage is turned on or off by an on/off signal supplied through a driving unit, comprising: a pixel read section for reading the luminance values for the light-emitting elements in a frame period from an image signal; and a ΔΣ modulator which operates in a sub-frame period which is 1/n of the frame period according to the luminance values read by the pixel read section, wherein an output of “1” or “0” from ΔΣ modulator is supplied to the driving unit as the on/off signal.
2. A driving apparatus for a light-emitting display according to claim 1, wherein the ΔΣ modulator is a K-order modulator.
3. A driving apparatus for a light-emitting display according to claim 1, wherein the ΔΣ modulator comprises: an adder; a first delay unit for delaying an output from the adder by the sub-frame period; a deciding unit for deciding whether or not the output from the adder is not smaller than a prescribed value so that if YES, a positive prescribed value is outputted and if NO, a negative prescribed value is outputted; a second delay unit for delaying the prescribed value outputted from the deciding unit by the sub-frame period; wherein the adder performs an addition of outputs from the pixel read section and from the first delaying unit, a subtraction of an output from the second delay unit to produce a positive or negative sign bit of the prescribed value from the deciding unit as an output from the ΔΣ modulator.
4. A driving apparatus for a light-emitting display according to claim 3, wherein the ΔΣ modulator is a K-order ΔΣ modulator comprising respective K-1 components of the adder and the first delay unit, which are connected in a cascade between the adder and the deciding unit.
5. A driving apparatus for a light-emitting display according to claim 3, wherein the first delay unit and the second delay unit are constructed by a sample-and-hold unit for sampling/holding an input value by a sampling pulse which is repeated in the sub-frame period.
6. A driving apparatus for a light-emitting display according to claim 1, wherein the ΔΣ modulator modulates, in a time divisional manner, the luminance values for the M number of light emitting elements.
7. A driving apparatus for a light-emitting display according to claim 1, wherein the M number of light emitting elements are arranged in a row or column.
8. A driving apparatus for a light-emitting display according to claim 6, wherein the ΔΣ modulator comprises: a read section for reading the M number of luminance values in a 1/nM frame period; an adder; a first read/write section provided with first M memories for reading recorded values from the first M memories in the 1/nM frame period, writing an output from the adder, and sequentially reading recorded values from the subsequent memory; a deciding section for deciding whether or not the output from the adder is not smaller than a prescribed value so that if YES, a positive prescribed value is outputted and if NO, a negative prescribed value is outputted; a second read/write section provided with second M memories for reading recorded values from the second M memories in the 1/nM frame period, writing an output from the adder, and sequentially reading recorded values from the subsequent memory, wherein the adder performs an addition of outputs from the read section and from the first read/write section, a subtraction of an output from the second read/write section to produce a positive or negative sign bit of the prescribed value from the deciding unit as an output from the ΔΣ modulator.
9. A driving apparatus for a light-emitting display according to claim 8, wherein the ΔΣ modulator is a K-order ≢Σ modulator comprising respective K-1 components of the adder and the first read/write sections, which are connected in a cascade between the adder and the deciding unit.
10. A driving apparatus for a light-emitting display which controls the light-emission of M number of light-emitting elements in such a manner that a driving current or driving voltage is turned on or off by an on/off signal supplied through a driving unit, comprising: a pixel read section for reading the luminance values of the light-emitting elements in a frame period from an image signal; a ΔΣ modulator which operates in a sub-frame period which is 1/n of the frame period according to the luminance values read by the pixel read section; and a random data generator for generating random luminance values of individual pixels, wherein in an image displaying operation, the output from the random data generator is directly supplied to the ΔΣ modulator in place of the output from the pixel read section, or otherwise added to the output from the pixel read section.
11. A driving apparatus for a light-emitting display according to claim 10, wherein the random data generator is constructed of pixel memories with random data for the pixels.
12. A driving apparatus for a light-emitting display which controls the light-emission of M number of light-emitting elements in such a manner that a driving current or driving voltage is turned on or off by an on/off signal supplied through a driving unit, comprising: a pixel read section for reading the luminance values of the light-emitting elements in a frame period from an image signal; a ΔΣ modulator which operates in a sub-frame period which is 1/n of the frame period according to the luminance values read by the pixel read section, the ΔΣ modulator having a delay unit for delaying the image signal by a period of the sub-frame; and a random data generator for generating random luminance values for individual pixels, wherein at the start of an image displaying operation, the output from the random data generator is directly supplied to the ΔΣ modulator in place of an output from the delay unit, or otherwise added to the output from the delay unit.
13. A driving apparatus for a light-emitting display according to claim 12, wherein an output from the random data generator is supplied to the delay unit as an initial value therefor.
14. A driving apparatus for a light-emitting display according to claim 12, wherein the random data generator is constructed of pixel memories with random data for the pixels.

Priority Claims (2)

Number	Date	Country	Kind
2000-18330	Jan 2000	JP
2000-18331	Jan 2000	JP

Apparatus for driving light-emitting display

Information

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Date Filed

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CPC

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Abstract

Description

Claims

Priority Claims (2)