The present invention relates to on-chip impedance matching circuits, and more particularly, to an apparatus for obtaining precision integrated resistors in CMOS processes.
Mainstream CMOS processes typically do not offer precision resistors, with variation often being twenty percent or more. Circuits needing resistors are generally designed to function with this variation at the expense of performance.
Alternatively, prior art circuits have provided off-chip impedance matching circuits comprising variable resistors or similar devices that can be calibrated to compensate for process/voltage/temperature variations to improve the precision of on-chip resistors.
Unfortunately, the off-chip impedance matching approach is expensive and imposes additional constraints on system architecture. Furthermore, some integrated circuits have hundreds of circuits that require impedance matching circuitry. In these integrated circuits, a separate impedance matching resistor must be coupled to an 1/0 pin connected to each of the circuits requiring impedance matching. Hundreds of impedance matching resistors must be coupled to such an integrated circuit to provide adequate impedance matching. Thus, prior art off-chip impedance matching circuits substantially increase the amount of board space required.
Accordingly, there is a need for a technique for implementing on-chip precision integrated resistors in CMOS processes that allow improved precision of the resistor values without the need for external impedance matching circuitry.
According to one aspect of the invention, there is provided an impedance matching apparatus for obtaining precision integrated resistors in integrated circuits. According to another aspect of the invention, there is provided an integrated circuit with on-chip precision resistors for use in impedance matching techniques for functional circuitry. The apparatus of the invention utilizes on- or off-chip precision voltage and precision current sources to adjust a variable resistor implemented on the integrated circuit, for example by selectively switching in parts of a resistor array, until the desired resistance value is obtained. The calibrated resistor is then available for use in functional circuitry requiring matched impedance throughout the chip.
Advantageously, no processing matching is needed for the variable resistor itself because the same resistance being calibrated will actually be used in the functional circuitry, thereby removing processing variation. Depending on how frequently the calibration routine is exercised, the resistance may or may not be at the same temperature during calibration as during normal operation. If it is at the same temperature during calibration, then the variation caused by temperature is also removed. Another advantage is a reduction in the number of off-chip resistors that are coupled to the integrated circuit.
A more complete appreciation of this invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
Turning now to the drawings,
The integrated circuit 10 comprises a variable resistor 20 whose resistance is controlled by a control signal 31 generated by control logic 30. The variable resistor 20 may be connected between a node 7 that is switchably connected to an output node 5 of a precision voltage source 4 and a node 13 that is switchably connected to a node 15 at an input of a current comparator 18. The precision voltage source 4 may generate a known precise voltage on the node 5.
A precision current source 17 may generate a known precise reference current on a node 16 at another input of the current comparator 18. The current comparator 18 may generate an output signal representing the relative difference between current present at each of its inputs. In a particular embodiment, the output of the current comparator is a binary output representing whether the current IVR across the variable resistor 20 is greater than or less than the reference current IREF generated by the current source 17. The output signal of the current comparator 18 may be output on a node 19.
The node 19 may be connected to an input of control logic 30. Control logic 30 may generate a control signal 31 used by the variable resistor 20 to adjust the resistance of the variable resistor 20.
Node 7 connected to one terminal of the variable resistor 20 is switchably connectable to the output node 5 of the precision voltage source 4 by way of a switch device 6. The state of the switch device 6 is controlled by a calibration enable signal CAL. When the calibration enable signal CAL is in an asserted state, the switch device 6 is closed, connecting node 5 to node 7. When the calibration enable signal CAL is in a deasserted state, the switch device 6 is open, isolating node 5 from node 7.
Node 13 connected to the other terminal of the variable resistor 20 is switchably connectable to an input of the current comparator 18 at node 15 by way of a switch device 14. The state of the switch device 14 is controlled by the calibration enable signal CAL. When the calibration enable signal CAL is in an asserted state, the switch device 14 is closed, connecting node 13 to node 15. When the calibration enable signal CAL is in a deasserted state, the switch device 14 is open, isolating node 13 from node 15.
Functional application circuit 2 may be switchably connectable to node 7, and hence one terminal of the variable resistor 20, by way of switch device 8. The position of the switch device 8 is controlled by an inverted version CAL′ of the calibration enable signal CAL. When the inverted calibration enable signal CAL′ is in an asserted state, the switch device 8 is closed, connecting node 9 to node 7. When the inverted calibration enable signal CAL′ is in a deasserted state, the switch device 8 is open, isolating node 9 from node 7.
Functional application circuit 2 may be switchably connectable to node 13, and hence to the other terminal of the variable resistor 20, by way of switch device 12. The position of the switch device 12 is controlled by an inverted version CAL′ of the calibration enable signal CAL. When the inverted calibration enable signal CAL′ is in an asserted state, the switch device 12 is closed, connecting node 11 to node 13. When the inverted calibration enable signal CAL′ is in a deasserted state, the switch device 12 is open, isolating node 11 from node 13.
In operation, the circuit may be placed in a calibration mode wherein the calibration signal CAL is asserted and the inverted calibration signal CAL′ is deasserted. When the inverted calibration signal CAL′ is deasserted, switches 8 and 12 open, thereby isolating nodes 9 and 11 of the functional circuitry 2 from the terminal nodes 7 and 13 of the variable resistor 20. Since the calibration signal CAL is asserted, switches 6 and 14 close, thereby connecting terminal node 7 to the output 5 of the precision voltage source 4 and terminal node 13 to node 15 at the input of current comparator 18.
In implementation, each of the switch devices 6, 8, 12 and 14 are matched to ensure that the switch devices 6 and 14 vary in the same way with respect to process, voltage, and temperature variations as the switch devices 8 and 12 connected to the functional circuit 2. This ensures that the resistance of the variable resistor 20 will not appear differently to the functional circuit 2 as it did to the calibration circuitry.
The above-identified switch configuration (i.e., switch devices 8 and 12 open and switch devices 6 and 14 closed) results in the precision voltage generated on the output node 5 of the precision voltage source 4 being connected to the terminal node 7 of the variable resistor 20. Since switch device 8 is open, all current flow must go through the variable resistor 20. Further, since switch device 12 is open, all current flow through variable resistor 20 goes through the input of the comparator 18. Simultaneously, the precision current source. 17 generates a known precise reference current IREF on node 16 at the other input of the comparator 18. The current comparator 18 generates one logic level (e.g., a logic high, or “1”) on node 19 if the reference current IREF is greater than the current flow IVR through variable resistor 20 and the other logic level (e.g., a logic low, or “0”) on node 19 if the reference current IREF is less than the current flow IVR through variable resistor 20.
The control logic 30 utilizes the signal on node 19 in determining how to adjust the variable resistor 20 during a calibration mode.
The choice in resistive step may be implemented according to one of many different step algorithms, for example according to a thermometer code, a binary-weighted code, a hybrid code, etc. A detailed description of each of these codes is described in detail in U.S. patent application Ser. No. 10/835,906 to Humphrey, filed on Apr. 30, 2004, and entitled “Hybrid Binary/Thermometer Code For Controlled-Voltage Integrated Circuit Output Drivers”, which is hereby incorporated by reference herein for all that it teaches. Other implementations may be used for selecting the resistance at each step.
As also shown, the switch devices 6, 8, 12 and 14 are each implemented with matching FET devices, preferably using transmission gates (or “T-gates”) 106, 108, 112, and 114, as shown.
The resistance network 120 includes a resistive leg 1230 that is connected between node 107 and node 113, and a plurality of impedance legs 1231, . . . , 1237 programmably electrically connectable in parallel between node 107 and node 113 by the control circuit 130. In the preferred embodiment, each of the FET devices 1210, . . . , 1217 is defined by a channel width that defines the admittance of that FET device. When activated (i.e., turned on to conduct current), each FET device provides an electrical connection between node 107 and a first terminal of its corresponding resistor 1220, . . . , 1227. The other terminal of the corresponding resistor 1220, . . . , 1227 is connected to node 113. Activation of a FET device thereby allows current flow between nodes 107 and 113 such that the respective corresponding resistor 1220, . . . , 1227 contributes to the combined parallel resistance of the impedance network. When more than one of the FET devices 1210, . . . , 1217 is turned on, the characteristic resistance of the enabled FETs combine in parallel to provide a lower combined resistance. In this way, the output resistance of the resistance network 120 may be varied.
In the embodiment shown, the impedance leg 1230 is always activated, allowing a signal to pass from node 107 to node 113 in order to prevent impedance jumps which can result in noise glitches on the input nodes 109 and 111 of the functional circuitry 102 that may occur momentarily as a result of the switching on or off of the impedance legs 1231, . . . , 1237.
The control circuit 130 generates a digital calibration word W1::7 to activate selected ones of the switchable resistance legs 1231, . . . , 1237 to precisely control the resistance of the variable resistor 120 in accordance with one of the methods described in FIGS. 2 or 3, or using other step decision functionality. Each respective bit in the calibration word W1::7corresponds to, and controls, a different one of the resistance legs 1231, . . . , 1237. In the preferred embodiment, each respective bit W1, through W7 of the calibration word W1::7 drives a different respective gate of a corresponding respective resistance legs 1211, . . . , 1217 implementing the respective corresponding resistance legs 1231, . . . , 1237.
In the illustrative embodiment, the admittances of resistance legs 1231, . . . , 1237 of the impedance network 120 may be weighted to implement the chosen code of the controller. For example, in a binary weighted code, each resistance leg in the resistance network has an admittance of 2(bit position)Y, where Y is a predefined minimum admittance appropriate to the design. In other words, if bit B0 of a binary-coded calibration word B0::n−1controls a FET with admittance Y, bit B1. of the calibration word B0::n−1 controls a FET with admittance 2*Y, bit B2 of the calibration word B0::n−1 controls a FET with admittance 4*Y, and so on. Thus, the impedance of each leg of the resistance network corresponds to the weighted position of the bit in the binary code that controls the leg.
In a thermometer code, the admittances of the resistance legs 1231, . . . , 1237 may be weighted equally. Other codes may require different weighting of the admittances of the resistance legs.
The above described impedance matching circuit allows increased calibration precision of integrated resistors in integrated circuits. The above design allows high-precision on the order of 1% or less tolerance in resistance values. Compared to 10 or even 20% tolerance in prior art integrated resistors, the invention adds a clear contribution to integrated circuit designs.
In any given integrated circuit, the determination of when to calibrate the resistor depends on the design. Calibration can be performed once at power-up, periodically after power-up, or upon demand via external programming.
Those skilled in the art will appreciate that other equivalent implementations are possible. For example, there are many different circuits that can be used as a current source and many different circuits that can be used as a voltage source. The variable resistor 20 may be implemented as a resistor array, a field effect transistor (FET) array, or any other variable resistance equivalent, and may be implemented as a series array, a parallel array, or combination.
The current and/or voltage source may alternatively be implemented using a precision capacitor circuit with a precision clock. Capacitors are relatively simple to implement and generate a precise voltage when the clock signal is accurate. Integrating the charge over time results in voltage. The circuit then breaks down into comparing two voltages.
As known by those skilled in the art, q=CV and I=Δq/T, where q is charge, C is capacitance, V is voltage, I is current, and T is time. In the circuit of
Although this preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It is also possible that other benefits or uses of the currently disclosed invention will become apparent over time.