This invention is generally directed to detection of noise in a paired line. More particularly the present invention relates to an apparatus and method of measuring noise in a paired telecommunications line. The present invention is particularly, though not exclusively, an apparatus and method for detecting and isolating noise-creating imbalances in a paired line of a telecommunications cable by means of a balanced circuit.
Paired lines are a conventional means of carrying telecommunications transmissions. A paired line is made up of two balanced conductors individually insulated and twisted together. Paired lines are typically bundled together in a cable termed a paired cable, which contains up to one hundred or more paired lines, wherein each paired lines is capable of independently carrying telecommunications signals. Paired lines are typically effective telecommunications carriers, however, it is not uncommon for noise to occur in paired lines which is extremely disruptive to the clarity of the transmitted signal.
Test instruments have been developed that contain circuitry suitable to detect and isolate noise-creating imbalances so that a technician can diagnose the source of the problem and eliminate it. This is commonly referred to as the stress test. U.S. Pat. No. 5,157,336 (“the '336 patent”) and U.S. Pat. No. 5,302,905 (“the '905 patent) disclose circuitry of a test instrument that satisfies this need and their content is incorporated herein by reference in their entirety.
A prior art circuit 10 for performing a stress test, such as that described in the '905 patent is shown in
As shown in
In order to ensure balance of the first and second pathways 12, 16, a technician must examine a number of capacitors that have been pre-sorted by the manufacturer to locate two capacitors having values within 0.5% of one another. After the capacitors have been installed, the capacitors are further matched to be within 0.05% of each other. These steps to match the capacitors are necessary to ensure that the circuit 10 will operate properly. Because capacitors are inherently difficult to manufacture in tight tolerances, the technician can not simply rely on the pre-sorted values provided by the manufacturer. Furthermore, because capacitor values drift with temperature and age, the value of the capacitor may vary from the value at the time of manufacture.
It is inefficient, costly, and unreliable to have a technician perform this vetting operation. Consequently, there is a need for circuitry that can perform the necessary functions of a stress test as described in the '336 and '905 patents in a more efficient, economical and reliable manner.
The present invention provides a circuit and method which overcomes the problems presented in the prior art and which provides additional advantages over the prior art, such advantages will become clear upon a reading of the attached specification in combination with a study of the drawings.
The present invention provides a circuit and a method of measuring noise in a paired line which does not require vetting of capacitors to ensure balance between a first balanced inlet pathway and a second balanced inlet pathway.
The organization and manner of the structure and operation of the invention, together with further objects and advantages thereof, may best be understood by reference to the following description, taken in connection with the accompanying drawings, wherein like reference numerals identify like elements in which:
While the invention may be susceptible to embodiment in different forms, there is shown in the drawings, and herein will be described in detail, a specific embodiment with the understanding that the present disclosure is to be considered an exemplification of the principles of the invention, and is not intended to limit the invention to that as illustrated and described herein.
Referring first to
A series resistance fault 48 is shown on second conductor 28 which creates an imbalance in paired line 30 between first and second conductor 26, 28. It is understood that fault 48 is illustrative of any number of sources of imbalance in paired line 30 to which the present invention is applicable, including shunt resistance faults, cross faults, shunt capacitance faults, unbalanced series inductance, and power influence.
The internal circuit of the device 110 is shown in
Referring now to
The circuit 140 includes a first contact 142, a second contact 144, and a third contact 146. The first contact 42 provides external connection to the first conductor 26 of the paired line 30 through contact 122 and lead 116, the second contact 144 provides external connection to the second conductor 28 of the paired lines 30 through contact 124 and lead 118, and the third contact 146 provides external connection to the earth ground 34 through contact 32 and lead 120.
As also shown in
The ground pathway 156 generally includes an oscillator 160, a dc power source 162 and an ac blocking capacitor 196. The ac blocking capacitor 196 prevents the ground pathway 156 from drawing ac power influence current to ground to undesirably seal fault 48. In addition, capacitor 196 minimizes low frequency ac power influence current and the de loop current drawn by the ground pathway 156. The oscillator 160 provides a low voltage alternating current source feeding into conductors 26, 28 across the first and second balanced outlet pathways 148, 150. Low voltage ac is defined herein as preferably being less than about 10 volts.
First balanced outlet pathway 148 extends from earth ground 158 to the first conductor 26 through the first contact 142. The first balanced outlet pathway 148 includes a first balanced capacitor 184 and a first balanced resistor 186. Capacitor 184 preferably has a value of 2.2 μF and resistor 186 preferably has a value of 1 KΩ. Second balanced outlet pathway 150 extends from earth ground 158 to second conductor 28 through the second contact 144. The second balanced outlet pathway includes a second balanced capacitor 188 and a second balanced resistor 190. Capacitors 184, 188 are matched within 0.5%. Capacitor 188 preferably has the same value as capacitor 184 and thus preferably has a value of 2.2 μF. Resistor 190 preferably has the same value as resistor 186 and thus preferably has a value of 1 KΩ.
The first high voltage bias pathway 172 extends from earth ground 158 to the first conductor 26 through the first contact 142. The first high voltage bias pathway includes a high value resistor 180 which preferably has a value of 100 KΩ. Second high voltage bias pathway 174 extends from earth ground 158 to the second conductor 28 through second contact 144. The second high voltage bias pathway includes a high value resistor 182 which preferably has the same value as resistor 180.
Terminating pathway 170 is provided between first contact 142 second contact 144. Terminating pathway 170 includes a dc isolating capacitor 176 in series with a line terminating resistor 178.
The first voltage inlet pathway 152 extends from contact 142 to a first input of a differential amplifier 168. The first voltage inlet pathway includes a capacitor 192. The second voltage inlet pathway 154 extends from contact 144 to a second input of the differential amplifier 168 and includes a capacitor 194. Capacitors 192, 194 are matched within 5%. The differential amplifier 168 of the present invention provides measuring means in electrical communication with the first and second voltage inlet pathways 152, 154.
The circuit 140 of the present invention operates in the following manner. In the same manner as the circuit 10 of
The AC signal is reflected back to the stress test circuit 140 through contacts 142, 144 while resistor 178 and capacitor 176 filter out unwanted noise. Then, the AC signal passes through isolation capacitors 192 and 194 to the differential amplifier 168. The differential amplifier 168 receives metallic voltage signals from voltage inlet pathways 152, 154 and measures the voltage difference. Any difference of the capacitance between the two conductors 26, 28, will cause amplitude and phase changes of the coupled tone which is measured by the differential amplifier 168. The device 110 provides similar stress test results when using standard testing protocols under similar circumstances as devices employing the circuit 10 shown in
Thus, circuit 140 performs a stress test similar to that performed by the circuit 10 of
A need still exists to protect the measurement circuitry 168 from high voltage DC current in the circuit 140. Consequently, new capacitors 192, 194 have been included with values of only 1 microfarad and lose tolerances to prevent DC current from reaching the measurement circuitry 168 of the test instrument 110. Only capacitors of low values and tolerances are required because the impedance of the measurement circuit is very high. Furthermore, the load and isolation tasks of the original capacitors 34, 38 of the circuit 10 shown in
Each balanced outlet pathway 148, 150 includes a capacitor 184, 188 in series with a resistor 186, 190. Although the capacitors 184, 188 are positioned proximate the earth ground 34 in the circuit 140, it is to be understood that the positions of the capacitors 184, 188 and the resistors 186, 190 could be swapped such that the resistors 186, 190 are positioned proximate the node 158. However, by providing the capacitors 184, 188 connected directly to earth ground 158 as shown in
As can be seen, this invention provides a more efficient way of performing the stress test because it does not require a technician to vet capacitors. In addition, because the need to vet capacitors is eliminated, the circuit 140 is less prone to human error and therefore is more reliable. Finally, the amount of time required to assemble the circuit is reduced which results in reduced labor cost, making this circuit 140 more economical than the previous stress test circuits.
While preferred embodiments of the present invention are shown and described, it is envisioned that those skilled in the art may devise various modifications of the present invention without departing from the spirit and scope of the appended claims.
This application claims the domestic benefit of U.S. Provisional Application Ser. No. 60/980,523, filed on Oct. 17, 2007, which disclosure is incorporated herein by reference in its entirety.
Number | Date | Country | |
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60980523 | Oct 2007 | US |