Claims
- 1. A data transfer system for controlling data transfer between a channel of a central processing unit and a storage device, said channel having a first transfer rate, and said storage device having a second transfer rate, said system comprising:
- a channel transfer circuit for controlling the data transfer between said channel and said channel transfer circuit at the first transfer rate;
- a device transfer circuit for controlling data transfer between said device and said device transfer circuit at the second transfer rate;
- a first path for synchronously transferring data between said channel transfer circuit and said device transfer circuit;
- an intermediate memory, connected through a second path to said channel transfer circuit, and said device transfer circuit for temporarily storing transfer data from said channel transfer circuit and asynchronously transferring the transfer data to said device transfer circuit, and for temporarily storing the transfer data from said device transfer circuit and asynchronously transferring the transfer data to said channel transfer circuit;
- said channel transfer circuit including
- a memory for storing data representing the first transfer rate and data representing the second transfer rate;
- comparing means, connected to said memory, for comparing the first transfer rate and the second transfer rate; and
- switching means, for selecting one of the first path or the second path based on a result of said comparing means.
- 2. A data transfer system as claimed in claim 1 wherein said comparing means compares data representing said first and second transfer rates from said memory in response to a transfer request from said central processing unit and said switching means selects the first path when said first transfer rate is equal to said second transfer rate, and said switching means selects the second path when said first transfer rate is different from said second transfer rate.
- 3. A data transfer system as claimed in claim 1 wherein said storage device comprises a group of disk drives, each disk drive having said second transfer rate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
3-041649 |
Mar 1991 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 08/138,892, filed on Oct. 19, 1993, now abandoned, which is a continuation of application Ser. No. 07/846,280, filed Mar. 4, 1992, now abandoned.
US Referenced Citations (17)
Foreign Referenced Citations (1)
Number |
Date |
Country |
5155810 |
Oct 1992 |
JPX |
Non-Patent Literature Citations (3)
Entry |
Balue et al., "Data-Transfer Speed Extracts Mileage from 5.2-Gbyte Tape", Electronic Design International, vol. 35, No. 25, 29 Oct. 1987, pp. 95-99. |
"Two-Way Data Flow Interface Circuit to Increase Computer Processing Throughput", IBM Technical Disclosure Bulletin, vol. 32, No. 5A, Oct. 1989, pp. 120-122. |
Beukema et al. "Transparent Mode in an I/O Controller", IBM Technical Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, pp. 5956-5959. |
Continuations (2)
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Number |
Date |
Country |
Parent |
138892 |
Oct 1993 |
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Parent |
846280 |
Mar 1992 |
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