Claims
- 1. An apparatus for selectively producing any one of a plurality of predetermined sound effects each specified by an associated digital command character, said apparatus comprising:
- variable clock means for generating a binary clock signal having a frequency specified by an associated digital command character, said clock means including an input terminal adapted to be coupled to a source of timing signals, an output terminal for manifesting said binary clock signal, a data input terminal adapted to be coupled to said associated digital command character, and means coupled to said input terminal, said output terminal and said data input terminal for transforming said timing signals to said binary clock signals; and
- sound generator means for generating sound effect signals corresponding to said associated digital command character, said sound generator means including an input terminal coupled to said output terminal of said variable clock means, an output terminal for manifesting the electrical analog signals corresponding to said desired sound effect, counter means coupled to said input terminal and said output terminal for generating a binary signal train in response to the receipt of said binary clock signal, said binary signal train having a frequency content specified by said digital command character, and means coupled to said counter means for converting said binary signal train to said electrical analog signals corresponding to said desired sound effect, said converting means including means for providing a predetermined amplitude attenuation characteristic corresponding to said desired sound effect specified by said digital command character.
- 2. The combination of claim 1 wherein said transforming means includes a divide-by-N counter, where N is an integer, and a digital character register having input means for receiving said digital command character and output means coupled to said divide-by-N counter for controlling the value of N.
- 3. The combination of claim 1 wherein said counter means includes a multi-stage polynomial counter and first gating means coupled between predetermined states of said polynomial counter for controlling said frequency content in accordance with said digital command character.
- 4. The combination of claim 3 wherein said first gating means includes a first plurality of individual gating circuits each having an input coupled to the output of a predetermined one of said polynomial counter stages, and wherein said means for providing a predetermined amplitude attenuation characteristic includes means for selectively summing the output signals from said plurality of individual gating circuits to vary the amplitude of each frequency component in accordance with said digital command character.
- 5. The combination of claim 4 wherein said converting means includes low pass filter means coupled to the output of said summing means.
- 6. The combination of claim 3 wherein said means for providing a predetermined amplitude attenuation characteristic includes second gating means comprising a second plurality of individual gating circuits each having an input coupled to the output of a predetermined one of said polynomial counter stages, resistive summing means including a plurality of resistive elements each having a first terminal coupled to the output of a different one of said second plurality of individual gating circuits and a second terminal coupled to said sound generator means output terminal, and a digital character register having input means for receiving said digital command character and output means coupled to said second gating means for controlling the state of each of said individual gates so that the binary signal from said predetermined one of said polynomial counter stages is selectively applied through said second plurality of individual gating circuits and said plurality of resistive elements to said sound generator means output terminal.
- 7. The combination of claim 6 wherein said resistive summing means comprises a plurality of integrated field effect transistors each having a gate element coupled to the output of a different one of said second plurality of individual gating circuits, and wherein each of said resistive elements comprises the drain region of a different one of said plurality of integrated field effect transistors, said drain regions having areas proportional to the desired resistive summing.
Parent Case Info
This is a continuation of application Ser. No. 758,713, filed Jan. 12, 1977 now abandoned.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
3587094 |
Scott |
Jun 1971 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
758713 |
Jan 1977 |
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