Claims
- 1. A redundant remultiplexer comprising:
(a) at least two media control modules, each having multiple ports capable of being configured to operate as inputs or outputs, and having:
i) at least one port capable of receiving an externally originating sequence of one or more packets, or transmitting externally a sequence of one or more packets, ii) a clock capable of generating a time value that can be used to determine a time at which each externally originating packet is received at the port, or an approximate time for transmitting externally each packet from the port, iii) at least one processor capable of processing each packet according to the respective time determined for the packet by the clock, to schedule selected ones of the packets for transmission, and iv) an interface for transmitting packets processed by the at least one processor to, or receiving packets to be processed by a processor from another device, and (b) at least one switch control module, each capable of communicating packets with the media control modules via the interfaces of the media control modules, and each capable of selecting, based on address information carried within each packet present at the switch control module, a specific media control module to receive each of the packets present at the switch control module, wherein one of the media control modules operates as a primary module in either, an input mode, for receiving an externally originating sequence of packets, or in an output mode, for outputting externally a sequence of packets, and wherein another one of the media control modules operates as a backup module for the primary module, wherein, if the primary module operates in an input mode, the at least one processor of the backup module performs the same processing of packets as the primary module but the interface of the backup module only transmits processed packets to each switch control module if the primary module fails, and wherein, if the primary module is operating in the output mode, the at least one processor of the backup module performs the same processing as the primary output module on the same sequence of packets received from the switch module, but the port of the backup module only externally outputs the signal if the primary module fails.
- 2. The remultiplexer of claim 1 wherein the interface of each said media control module is connected to a full-duplex Ethernet link, which incurs an unpredictable jitter delay for communicating each packet thereon.
- 3. The remultiplexer of claim 1 wherein each of said at least one switch control module is capable of transmitting each of one or more of the to-be-externally outputted packets to each of one or more of the media control modules with a multicast destination address of a specific multicast group to which the one or more media control modules subscribe, wherein if the primary module operates in the output mode, the backup module is capable of subscribing to the same multicast group as the primary module so that both the primary module and the backup module receive and process the multicast packets transmitted by the switch control module.
- 4. The remultiplexer of claim 1 wherein each of said at least one switch control module is capable of transmitting at least one IP packet to the primary module using a MAC address assigned to at least the primary module and wherein, the backup module is capable of receiving and processing an identical copy of the at least one of the IP packets transmitted to the primary module with the MAC address assigned to at least the primary output module.
- 5. The remultiplexer of claim 1 wherein the backup module and primary module are both capable of being assigned of the same common address, wherein each of the primary module and backup module is capable of receiving, for external output from its port within the sequence of packets, externally originating data, the externally originating data being received via a TCP connection with an external source, and wherein the backup module is capable of filtering out certain control packets received at its interface prior to processing by the IP protocol stack, if no failure of the primary module is detected.
- 6. The remultiplexer of claim 6 wherein the backup module filters out TCP packet destined for the common address.
- 7. The remultiplexer of claim 6 wherein the backup module filters out ARP request packets sourced from the common address or destined to said common address.
- 8. The remultiplexer of claim 1, wherein said remultiplexer is a primary switch module, the remultiplexer further comprising:
(c) a backup switch module capable of communicating the same packets as the primary switch module, with the media control modules via the interfaces of the media control modules, and capable of selecting, based on address information carried within each corresponding packet, a specific media control module to receive each of selected received packets, as the primary switch module, wherein the media control modules discard packets transmitted from the backup switch module unless the primary switch module is determined to have failed.
- 9. The remultiplexer of claim 1, wherein the interface of each media control module comprises:
(c) a media access control circuit, (d) physical layer circuitry having
i) a first input capable of receiving packets from the primary switch module, ii) a first output for outputting the packets destined to a device connected to the first input, iii) a second input capable of receiving packets from a backup switch module for the first switch module, and iv) a second output for outputting packet packets destined to a device connected to the second input, and (e) a switch circuit having
i) first and second selectable inputs connected to the first and second outputs of the physical layer circuitry, respectively, and ii) an output connected to the receive input of the media access control circuit, so that the media access control circuit is capable of selectively receiving the to-be-externally transmitted packets from only one of the primary switch module and backup switch module at one time, the switch selecting the packets received from the backup switch module only in response to detecting a failure of the primary switch module.
- 10. The redundant remultiplexer of claim 9 wherein each of the primary switch module and the backup switch module comprises:
(f) at least one external interface for receiving packets other than those provided by the media control modules, the external interface being capable of receiving one or more addressed packets,
i) each of the primary and backup switch modules being capable of receiving identical copies of the addressed packets and being capable of selecting, based on address information carried with the corresponding packet, the same specific media control module to receive each of selected ones of the addressed packets, ii) wherein the same IP address is assigned to the external interfaces of both of the primary switch module and the backup switch module and wherein the backup switch module is capable of disabling its external interface in the absence of a determination that the primary switch module has failed.
- 11. A switch control module, capable of communicating packets with media control modules via interfaces of the media control modules, and capable of selecting, based on address information carried within each packet present at the switch control module, a specific media control module to receive each of the packets present at the switch control module, said switch control module comprising:
(a) at least one Ethernet port, and (b) a clock capable of generating a time value that can be used as a centralized single time-base clock, wherein the centralized time-base clock value being distributed to each said media control modules.
- 12. A media control module comprising:
(a) at least one port capable of receiving an externally originating sequence of one or more packets, or transmitting externally a sequence of one or more packets, (b) a clock capable of generating a time value that can be used to determine a time at which each externally originating packet is received at the port, or an approximate time for transmitting externally each packet from the port, (c) at least one processor capable of processing each packet according to the respective time determined for the packet by the clock, to schedule selected ones of the packets for transmission, and (d) an interface including a media access control circuit, a selector and two physical layer circuits, each physical layer circuit having a transmit input commonly connected to a transmit output of the interface, so that each physical layer circuit is capable of outputting a mirror image copy of externally received packets to each of a primary switch module and a backup switch module, each physical layer circuit having a receive input connected to respective first and second selectable outputs of the switch, the switch having a switchable input connected to the receive input of the media access control circuit, so that the media access control circuit is capable of selectively receiving the to-be-externally transmitted packets from only the active one of the primary and backup switch modules, wherein each physical layer circuit is capable of receiving duplicate sets of addressed packets from, respectively, the primary switch module and the backup switch module, but the switch permits only one set to be received at the media access control circuit from whichever of the primary switch module and the backup switch module is currently deemed active.
- 13. A redundant remultiplexer comprising:
(a) a primary module for processing received packets in order to output selected ones of the received packets from the remultiplexer at a particular time relative to other selected packets, at least some of the outputted packets containing information to be received according to a specific time schedule at a receiver relative to other related outputted ones of the packets, the primary output module having an output for transmitting ones of the received packets, (b) a backup module for processing copies of at least some of the same packets received at the primary output module in order to output selected ones of the received packets from the remultiplexer at a particular time relative to other selected packets, the backup module having an output which is disabled except upon determining that the primary module has failed, and (c) a switch module connected to the primary and backup module for switching packets received from outputs of active primary and backup modules to inputs of active primary and backup output modules, wherein, in response to detecting a failure of the primary module, the backup module activates its output to transmit copies of the ones of the received packets otherwise to be transmitted by the primary module and which have already been processed by the backup module prior to detecting the failure, so as to reduce a number of packets omitted from the remultiplexer output carrying information to be delivered according to the strict time schedule.
- 14. The remultiplexer of claim 13 wherein the primary module is a primary input module comprising an external input for receiving externally supplied packets and an output for outputting the selected ones of the packets to the switch module, and the backup module is a backup input module comprising an external input for receiving an identical copy of the externally supplied packets, wherein each of the primary and backup input modules comprises a mechanism to access a centralized single time base clock at the switch module for generating a receipt time of each selected packet to be outputted, and wherein the receipt time generated for a specific selected packet is used to determine a correct time at which to output the selected packet from the remultiplexer.
- 15. The remultiplexer of claim 13 wherein the primary module is a primary output module comprising an input for receiving the selected packets from the switch module and an external output for outputting the selected packets from the remultiplexer, and the backup module is a backup output module comprising an input for receiving an identical copy of the selected packets, wherein each of the primary and backup input modules comprises a mechanism to access a centralized single time base clock at the switch module clock for generating a dispatch time for each selected packet to be outputted, and wherein the dispatch time is used to output the selected packet externally from the remultiplexer according to the schedule.
- 16. A circuit for transmitting encoded signals via two external devices, comprising:
at least one processor; a memory; an interface, and at least one bus connecting said at least one processor, said memory, and said interface, wherein said interface comprises:
a MAC circuit, a switch, and two physical layer circuits, wherein a transmit output of the MAC circuit is connected to a transmit input of each of said two physical layer circuits, and wherein a receive output of each of said two physical layer circuits is connected to selectable inputs of said switch, whereby said interface is capable of transmitting a signal simultaneously to the two external devices but only capable of receiving a signal from an active one of the two external devices, so that both of said two external devices can be processing the transmitted data simultaneously to enable a seamless change to the active external device.
- 17. The circuit of claim 16, wherein said interface is an Ethernet interface, and said switch is a multiplexer.
RELATED APPLICATIONS
[0001] The subject matter of this application is related to the subject matter of the following patent applications, all of which are commonly assigned to the same assignee as is this application:
[0002] (1) U.S. patent application Ser. No. 09/007,212, entitled “Receipt and Dispatch Timing of Transport Packets in a Video Program Bearing Stream Remultiplexer,” filed on Jan. 14, 1998 for Regis Gratacap and William Slattery, and issued as U.S. Pat. No. 6,292,490;
[0003] (2) U.S. patent application Ser. No. 09/007,334, entitled “Dynamic Video Program Bearing Stream Remultiplexer,” filed on Jan. 14, 1998 for Regis Gratacap;
[0004] (3) U.S. patent application Ser. No. 09/007,203, entitled “Retiming of Video Program Bearing Streams Transmitted by an Asynchronous Communication Link,” filed on Jan. 14, 1998 for Regis Gratacap, now issued as U.S. Pat. No. 6,195,368;
[0005] (4) U.S. patent application Ser. No. 09/007,211, entitled “Bandwidth Optimization of Video Program Bearing Transport Streams,” filed on Jan. 14, 1998 for Robert Robinett and Regis Gratacap;
[0006] (5) U.S. patent application Ser. No. 09/007,210, entitled “Network Distributed Remultiplexer for Video Program Bearing Transport Streams,” filed on Jan. 14, 1998 for Robert Robinett, Regis Gratacap and William Slattery;
[0007] (6) U.S. patent application Ser. No. 09/007,204, entitled “Remultiplexer for Video Program Bearing Transport Streams with Assisted Output Timing for Asynchronous Communication Output,” filed on Jan. 14, 1998 for Regis Gratacap;
[0008] (7) U.S. patent application Ser. No. 09/006,964, entitled “Remultiplexer for Video Program Bearing Transport Streams with Program Clock Reference Time Stamp Adjustment,” filed on Jan. 14, 1998 for William Slattery and Regis Gratacap, now issued as U.S. Pat. No. 6,111,896;
[0009] (8) U.S. patent application Ser. No. 09/007,198, entitled “Remultiplexer Cache Architecture and Memory Organization for Storing Video Program Bearing Transport Packets and Descriptors,” filed on Jan. 14, 1998 for William Slattery and Regis Gratacap, now issued as U.S. Pat. No. 6,064,676;
[0010] (9) U.S. patent application Ser. No. 09/007,199, entitled “Scrambling and Descrambling Control Word Control in a Remultiplexer for Video Bearing Transport Streams,” filed on Jan. 14, 1998 for William Slattery and Regis Gratacap, now issued as U.S. Pat. No. 6,148,082;
[0011] (10) U.S. pat. application Ser. No. 09/006,963, entitled “Reference Time Clock Locking in a Remultiplexer for Video Program Bearing Transport Streams,” filed on Jan. 14, 1998 for William Slattery, now issued as U.S. Pat. No. 6,246,701; and
[0012] (11) U.S. patent application Ser. No. 09/393,227, entitled “Remultiplexer Architecture for Controlling the Supply of Data to be Combined With Constant End-to-End Delay Information,” filed on Sep. 9, 1999 for John R. Mick, Jr.