Patent Application
20080019249
This application claims the benefit of priority of Japanese Patent Application No. 2006-181619, filed Jun. 30, 2006, the entire contents of which are incorporated herein by reference.
1. Field
The present invention relates to apparatuses for reproducing data on recording media and methods for reproducing data on the recording media. More particularly, the present invention relates to an apparatus for reproducing data on a recording medium and a method for reproducing data on the recording medium, which perform analog-to-digital conversion (A/D conversion) to a reproduction signal to process the converted reproduction signal.
2. Description of the Related Art
High definition (HD) digital versatile disk (DVD) players playing back HD videos recorded on HD DVDs, which are high-capacity optical discs, have been in widespread use in recent years. Such an HD DVD player uses a blue-violet laser beam having a wavelength of 405 nm to read data on an HD DVD. HD DVD-read only memory (ROM) has a single-layer capacity of 15 GB and a dual-layer capacity of 30 GB. Rewritable HD DVD-random access memory (RAM) has a single-layer capacity of 20 GB. In order to realize these high capacities, the HD DVD players use laser beams having shorter wavelengths and adopts Partial Response Maximum Likelihood (PRML) technology as the signal processing method for reproduction of data.
The PRML technology is disclosed in, for example, JP-A 2001-195830. The PRML technology will now be briefly described.
Partial Response (PR) is provided as a method for carrying out data reproduction while compressing a necessary signal bandwidth by actively utilizing intersymbol interference (interference between reproduction signals corresponding to bits that are recorded side by side). The PR can be further classified into multiple types and classes depending on how the intersymbol interference occurs. For example, in the case of Class 1, reproduction data is reproduced as two-bit data “11” in response to recording data “1” to cause the intersymbol interference to occur in the subsequent one bit. Viterbi decoding algorithm is one kind of a maximum likelihood sequence estimation scheme. This scheme effectively utilizes a rule on the intersymbol interference of a reproduced waveform to reproduce data on the basis of information concerning signal amplitudes at multiple points of times. In order to perform the reproduction, a synchronizing clock is generated in synchronization with a reproduced waveform obtained from a recording medium and the reproduced waveform is sampled in response to the synchronization clock to convert the sampled waveform into amplitude information.
Then, appropriate waveform equalization is performed to convert the amplitude information into a response waveform of a predetermined partial response. Past sample data and current sample data are used in a Viterbi decoding unit to output the most probable data sequence as the reproduction data. Combination of the partial response method and the Viterbi decoding algorithm (maximum likelihood decoding), described above, is referred to as a PRML method. In order to realize this PRML technology, it is necessary to use an adaptive equalization technique with a high precision and a clock recovery technique with a high precision supporting the adaptive equalization technique so that the reproduction signal is produced as a response of a predetermined PR class.
Run Length Limited (RLL) codes for use in the PRML technology will now be described. In a PRML reproducing circuit, a clock signal in synchronization with a reproduction signal reproduced from the recording medium is generated from the reproduction signal itself. In order to generate a stable clock signal, it is necessary to invert the signal recorded on the recording medium in polarity within a predetermined time period. At the same time, the polarity of the reproduction signal is prevented from being inverted during a predetermined time period in order to decrease the maximum frequency of the recorded signal. A maximum data length in which the polarity of the reproduction signal is not inverted is referred to as a maximum run length, and a minimum data length in which the polarity of the reproduction signal is not inverted is referred to as a minimum run length.
For example, a modulation rule in which the maximum run length is seven bits and the minimum run length is one bit is represented by (1,7)RLL. A code having a modulation rule of (1,7)RLL is also called “min-2T-system code” because a minimum value (Tmin) in length in which the same code continuously appears is equal to “2T” when the code has a unit length of “T”.
A modulation rule in which the maximum run length is seven bits and the minimum run length is two bits is represented by (2,7)RLL. A code having a modulation rule of (2,7)RLL is also called “min-3T-system code” because Tmin is equal to “3T”.
Typical modulation and demodulation schemes used in the optical discs include Eight to Twelve Modulation (ETM) for the min-2T-system code used in the HD DVDs and Eight to Sixteen Modulation (EFM Plus) for the min-3T-system code used in DVDs in related art.
Reproducing circuits adopting the PRML technology are expected to have greatly improved reproduction performance at higher recording densities, compared with reproducing circuits adopting binary slicing (circuits in which analog reproduction signals are not subjected to the A/D conversion and are sliced and binarized by using appropriate thresholds). Accordingly, the HD DVD standard adopts the PRML technology to further improve the linear recording densities.
However, the signal processing circuits adopting the PRML technology are greatly increased in size because of the complicated configurations, compared with the reproducing circuits adopting the binary slicing. Accordingly, how the power consumption during operation is reduced is a big technical problem for the PRML signal processing circuits. Particularly, since the power consumption of analog-to-digital converters (ADCs) forms a larger proportion of the power consumption of the entire signal processing circuits and the sampling rates of the ADCs are proportionally increased at higher double speeds, it is desirable to achieve power saving in the ADCs.
An approach to this technical problem about the power consumption is a half rate technology disclosed in, for example, JP-A 2002-269925.
The technology disclosed in JP-A 2002-269925 is based on the eight-to-sixteen modulation (EFM plus) scheme using the “min-3T-system code”, adopted in the DVDs in the related art. In this technology, little presence of signal bandwidths having frequencies higher than one-fourth of a channel rate Fch in mutual transfer function (MTF) characteristics, as in an example shown in
Accordingly, in the technology disclosed in JP-A 2002-269925, both a channel-rate data demodulating unit that uses the channel rate to reproduce data and a half rate data demodulating unit that uses the half rate to reproduce data are provided and either of the data modulating units is selected depending on the signal quality in order to resolve the problem of the degradation in performance.
However, since the technology disclosed in JP-A 2002-269925 restricts application thereof to the min-3T-system code, it is not possible to directly apply this half rate technology to the HD DVDs adopting the min-2T-system code.
This is because, in the min-2T-system code adopted in the HD DVDs, the frequency components in areas having frequencies higher than 2T frequency (a one-fourth of the channel rate Fch) exist in the signal bandwidth, as shown in
Also in a phase control loop, the effect of the reduction in the amount of information concerning the time-base components apparently appears in the min-2T-system code, compared with the min-3T-system code. Accordingly, the operational stability can be threatened with the technology disclosed in JP-A 2002-269925.
Furthermore, the technology disclosed in JP-A 2002-269925 has a problem about a switching shock in rate switching.
The rate switching before data transfer (an operation of reproducing user data recorded on the optical disc and transferring the reproduced user data to, for example, a computer) has no problem because frequency acquisition, phase acquisition, adaptive learning, and the like are performed again after the rate switching. However, the rate switching during the data transfer can cause a loss of the user data or can damage the user data due to the switching shock. Consequently, there is room for improvement in the technology disclosed in JP-A 2002-269925.
Accordingly, it is an object of the present invention to provide an apparatus for reproducing data on a recording medium and a method for reproducing data on the recording medium, which are capable of switching from a normal sampling rate to a lower sampling rate even in the min-2T-system code used in HD DVDs and others without spoiling the operational stability to reduce the power consumption.
According to an embodiment of the present invention, an apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method, the digital data being recorded in a code pattern in which the same code continuously appears at least two times, includes an analog-to-digital converting unit that samples an analog reproduction signal recorded on the recording medium and converts the sampled analog reproduction signal into a digital signal; a sampling rate switching unit that adaptively switches the sampling rate in the analog-to-digital converting unit from a higher rate to a lower rate; and a data demodulating unit that reproduces and demodulates the digital signal subjected to the analog-to-digital conversion in the analog-to-digital converting unit by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate.
According to another embodiment of the present invention, an apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method includes an analog-to-digital converting unit that samples an analog reproduction signal recorded on the recording medium and converts the sampled analog reproduction signal into a digital signal; a sampling rate switching unit that adaptively switches the sampling rate in the analog-to-digital converting unit from a higher rate to a lower rate; and a data demodulating unit that reproduces and demodulates the digital signal subjected to the analog-to-digital conversion in the analog-to-digital converting unit by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate. The sampling rate switching unit switches the sampling rate from the higher rate to the lower rate during a period other than the period when user data is reproduced.
According to another embodiment of the present invention, an apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method includes an analog-to-digital converting unit that samples an analog reproduction signal recorded on the recording medium and converts the sampled analog reproduction signal into a digital signal; a sampling rate switching unit that adaptively switches the sampling rate in the analog-to-digital converting unit from a higher rate to a lower rate; and a data demodulating unit that reproduces and demodulates the digital signal subjected to the analog-to-digital conversion in the analog-to-digital converting unit by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate. The data demodulating unit selects different partial response classes, used in the Partial Response Maximum Likelihood method, at the higher rate and at the lower rate.
According to another embodiment of the present invention, an apparatus for reproducing digital data recorded on a recording medium by a binary slicing method and a Partial Response Maximum Likelihood method includes a first data demodulating unit that includes an analog-to-digital converting unit sampling an analog reproduction signal recorded on the recording medium and converting the sampled analog reproduction signal into a digital signal and that reproduces and demodulates the digital signal subjected to the analog-to-digital conversion in the analog-to-digital converting unit by the Partial Response Maximum Likelihood method; a second data demodulating unit that slices the analog reproduction signal into a binary value and demodulates the binary value; and a demodulation selecting unit that, at least if the second data demodulating unit is selected, stops the operation of the first data demodulating unit to selectively perform switching between the first data demodulating unit and the second data demodulating unit.
According to another embodiment of the present invention, a reproducing method for an apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method, the digital data being recorded in a code pattern in which the same code continuously appears at least two times, includes the steps of sampling an analog reproduction signal recorded on the recording medium and converting the sampled analog reproduction signal into a digital signal; adaptively switching the sampling rate in the analog-to-digital conversion from a higher rate to a lower rate; and reproducing and demodulating the digital signal subjected to the analog-to-digital conversion by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate.
According to another embodiment of the present invention, a reproducing method for an apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method includes the steps of sampling an analog reproduction signal recorded on the recording medium and converting the sampled analog reproduction signal into a digital signal; adaptively switching the sampling rate in the analog-to-digital conversion from a higher rate to a lower rate; and reproducing and demodulating the digital signal subjected to the analog-to-digital conversion by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate. The switching step switches the sampling rate from the higher rate to the lower rate during a period other than the period when user data is reproduced.
According to another embodiment of the present invention, a reproducing method for an apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method includes the steps of sampling an analog reproduction signal recorded on the recording medium and converting the sampled analog reproduction signal into a digital signal; adaptively switching the sampling rate in the analog-to-digital conversion from a higher rate to a lower rate; and reproducing and demodulating the digital signal subjected to the analog-to-digital conversion by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate. The reproducing and demodulating step selects different partial response classes, used in the Partial Response Maximum Likelihood method, at the higher rate and at the lower rate.
According to another embodiment of the present invention, a reproducing method for an apparatus for reproducing digital data recorded on a recording medium by a binary slicing method and a Partial Response Maximum Likelihood method includes a first data demodulating step of reproducing and demodulating a digital signal subjected to analog-to-digital conversion in an analog-to-digital converting unit by the Partial Response Maximum Likelihood method, the analog-to-digital converting unit sampling an analog reproduction signal recorded on the recording medium and converting the sampled analog reproduction signal into the digital signal; a second data demodulating step of slicing the analog reproduction signal into a binary value and demodulating the binary value; and a demodulation selecting step of stopping the first data demodulating step, at least if the second data demodulating step is selected, to selectively perform switching between the first data demodulating step and the second data demodulating step.
According to the apparatuses for reproducing data on recording media and the methods for reproducing data on the recording media, it is possible to switch from the normal sampling rate to the lower sampling rate even in the min-2T-system code used in HD DVDs and others without spoiling the operational stability to reduce the power consumption.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.
Apparatuses for reproducing data on recording media and methods for reproducing data on the recording media according to embodiments of the present invention will be described with reference to the attached drawings.
The reproducing apparatus 1 according to the first embodiment of the present invention is of a synchronous type in which switching between a higher rate and a lower rate is performed to sample analog reproduction signals recorded on the recording medium.
The synchronous type means that the higher sampling rate in the A/D conversion is synchronized with a channel rate (a reproduction rate in units of bits recorded on the recording medium). An operating clock in digital processing after the A/D conversion is also synchronized with a sampling clock in the synchronous reproducing apparatus 1. The synchronous type is generally used in the PRML signal processing.
At the lower rate, the analog reproduction signals are sampled at a sampling clock lower than the higher rate (the channel rate in this case). It is assumed that the lower rate is equal to the half rate (half of the channel rate) in the following description. However, the lower rate is not limited to the half rate.
Referring to
The data demodulating unit 40 includes, as internal components, a phase locked loop (PLL) unit 20, an offset control circuit 41 supporting varied rates, an asymmetry control circuit 42 supporting varied rates, an adaptive equalizer 30 supporting varied rates, a Viterbi decoder 43 supporting varied rates, a synchronous demodulation circuit 44, and an error correcting code (ECC) circuit 45.
The PLL unit 20 includes, as internal components, a frequency detector 23 supporting varied rates, a phase comparator 24 supporting varied rates, a loop filter 22, and a voltage controlled oscillator (VCO) 21. The adaptive equalizer 30 includes, as internal components, a finite impulse response (FIR) filter 31 and an equalization coefficient learning circuit 32.
The sampling rate switching unit 50 includes, as internal components, a variable frequency oscillator (VFO) area detection circuit 51, a signal quality evaluation circuit 52, and a sampling-rate switching control circuit 53.
An operation of the reproducing apparatus 1 having the above configuration will now be described.
The recording medium D is irradiated with a laser beam emitted from the PUH 10 with reproduction laser power. The PUH 10 detects light reflected from the recording medium D to output an analog reproduction signal. The analog reproduction signal output from the PUH 10 is supplied to the preamplifier 11 where the analog reproduction signal is subjected to, for example, signal amplification.
The pre-equalizer 12 performs pre-equalization of waves. The waveform equalization characteristics are formed by, for example, a seventh-order equiripple filter. A preferable cutoff frequency, boost frequency, amount of boost are set for each rate in response to a rate switching signal supplied from the sampling-rate switching control circuit 53 and the waveform equalization is performed.
At the higher rate (at the channel rate), it is desirable to set the waveform equalization characteristics so as to boost signal components near the 2T frequency component. In contrast, at the half rate, the waveform equalization characteristics are set such that the cutoff frequency is reduced to remove the signal components in a higher frequency range and to suppress the effect of the aliasing noise as much as possible.
However, since removing the signal components in the higher frequency range too much increases a bit error rate (bER), it is preferable to evaluate the bER in advance so that the removal of the aliasing noise is balanced with the removal of the signal components.
The amplitude control circuit 13 adjusts the amplitude of the signal subjected to the waveform equalization. The A/D converter 14 converts the analog reproduction signal into a digital value.
The PLL unit 20 extracts the sampling clock from the reproduction signal itself such that the appropriate sampling timing is yielded. Specifically, the frequency detector 23 detects a difference in frequency between the reproduced waveform and the channel rate or the half rate and the phase comparator 24 detects a difference in phase between the reproduced waveform and an ideal sampling point to control the frequency and the phase.
Both the frequency and the phase are controlled by the loop filter 22. The VCO 21 generates the sampling clock. The sampling clock is supplied to the A/D converter 14 in synchronization with the channel rate at the higher rate while the half-frequency clock is supplied to the A/D converter 14 at the half rate.
Since the precision of information concerning the detected phase is lowered at the half rate in the phase control loop, upsampling may be performed using an interpolation circuit at the half rate to increase the amount of information in order to improve the stability.
The offset control circuit 41 and the asymmetry control circuit 42 perform digital waveform shaping to the digital signal. The offset control circuit 41 is configured so as to set the duty ratio of the signal components to a predetermined value. In this case, since the offset control circuit 41 is capable of operating in principle at both the channel rate and the half rate although the precision can be varied, the offset control circuit 41 can support varied rates.
The asymmetry control circuit 42 is configured, for example, so as to detect the average value of the reproduction signal subjected to the offset adjustment to detect the asymmetry of the signal in the amplitude direction. In this case, since the asymmetry control circuit 42 is capable of asynchronously operating although the precision can be varied, the asymmetry control circuit 42 can support varied rates.
The adaptive equalizer 30 performs waveform equalization to the waveform resulting from the digital waveform shaping in the offset control circuit 41 and the asymmetry control circuit 42 so as to make a response in a predetermined PR class, typified by a PR(3443) response.
Specific configurations of the adaptive learning process are described in many documents including JP-A 2001-195830. An adaptive learning method by using the most common least mean square (LMS) algorithm will now be described with reference to
Referring to
Although a three-tap digital filter using the three multiplier circuits is exemplified in
An output Y(k) from the adaptive equalizer is calculated according to Equation (1):
Y(k)=x(k)*c1+x(k−1)*c2+x(k−2)*c3 (1)
where an input signal into the adaptive equalizer at a time k is denoted by x(k) and the coefficients input into the multiplier circuits 203, 204 and 205 are denoted by c1, c2, and c3, respectively.
The desired output Z(k) from the adaptive equalizer at the time k is calculated according to Equation (2), provided that a target PR class is, for example, PR(3443) and binary data A(k) is yielded by the Viterbi decoder 43 for the output Y(k) correctly.:
Z(k)=3*A(k)+4*A(k−1)*4*A(k−2)+3*A(k−3)−7 (2)
An equalization error E(k) at the time k is defined by Equation (3):
E(k)=Y(k)−Z(k) (3)
In the adaptive learning, the coefficients of the multiplier circuits are updated according to Equations (4) to (6).
c1(k+1)=C1(k)−α*x(k)*E(k) (4)
c2(K+1)=c2(k)−α*x(k−1)*E(k) (5)
c3(K+1)=c3(k)−α*x(k−2)*E(k) (6)
“α” in Equation (4) to (6) denotes an update coefficient and is set to a small positive value (for example, 0.01). The process shown in Equation (2) is performed by a waveform synthesis circuit 216. A delay circuit 215 delays the output Y(k) from the adder circuit 208 for a time corresponding to the processing time in the Viterbi decoder 43. An adder circuit 217 performs the processing shown in Equation (3). A coefficient update circuit 212 performs the processing shown in Equation (4) to update the coefficient of the multiplier circuit 203. The update result is stored in a register 209. A coefficient update circuit 213 performs the processing shown in Equation (5) to update the coefficient of the multiplier circuit 204. The update result is stored in a register 210. A coefficient update circuit 214 performs the processing shown in Equation (6) to update the coefficient of the multiplier circuit 205. The update result is stored in a register 211.
The adaptive learning is performed in the above manner. However, in order to support varied rates in the adaptive learning, it is necessary to introduce some schemes.
The adaptive equalizer 30 includes many delay circuits, such as the coefficient update circuits 212 to 214, for adjusting the delay corresponding to the processing time in the Viterbi decoder 43. The number of flip-flops should be switched between at the channel rate and at the half rate. For example, when a delay of 30T occurs in the Viterbi decoder 43, 30 flip-flops are necessary at the channel rate while, at the half rate, it is enough to provide 15 flip-flops at the half rate to realize the delay 30T because one clock corresponds to a delay of 2T. Accordingly, as shown in
As shown in
Accordingly, it is necessary to switch the operation of the equalization coefficients between at the channel rate and at the half rate. It is also necessary to separately set the initial equalization coefficients, which are very important in the adaptive learning, at the channel rate and the half rate.
Referring back to
Specifically, it is necessary to operate the Viterbi decoder 43 in response to the operating clock in synchronization with the channel rate even at the lower rate to supply the binary data to the downstream components (it is necessary to finally be in synchronization with the channel rate although the Viterbi decoder 43 can operate at the lower rate during some of the internal processings).
Accordingly, the Viterbi decoder 43 performs branch metric calculation and path selection every 1T at the channel rate and performs the branch metric calculation and path selection every 2T at the half rate to estimate an intermittent signal on the basis of the selected path.
As disclosed in JP-A 2002-269925, Nyquist interpolation from the half rate to the channel rate may be performed upstream of the Viterbi decoder 43.
The PRML method supporting varied rates is realized in the above manner. Supply of the binary data decoded by the Viterbi decoder 43 to a host apparatus, such as a personal computer, as user data will now be simply described.
The binary data output from the Viterbi decoder 43 is supplied to the synchronous demodulation circuit 44. In the HD DVD, the binary data sequence is recorded in frames each corresponding to 1116-bit data. A synchronization unit in the synchronous demodulation circuit 44 detects 24-bit binary data sequence (SYNC code) representing the start position of each frame to generate a 12-bit synchronization signal for a downstream demodulating unit. The demodulating unit in the synchronous demodulation circuit 44 demodulates the 12-bit binary data into 8-bit reproduction data in accordance with a demodulation rule defined in advance in the ETM. The signal (demodulation data), which is 8-bit data (Byte data), is supplied to the ECC circuit 45.
The ECC circuit 45 corrects an error caused by, for example, any defect on the recording medium D and, then, supplies the user data to the host apparatus.
In order to further improve the performance at each rate, not only the characteristics of the pre-equalizer 12 are switched at each rate but also the PR class set by the Viterbi decoder 43 is switched.
For example, in the case in which a target PR characteristic at the channel rate in the HD DVD is a PR(3443), since the MTF characteristics of the HD DVD is very close to the PR(3443) characteristic, as shown in
However, the PR(3443) characteristic is not necessarily optimal at the half rate. This is because it is assumed that the PR(3443) characteristic is formed at the channel rate, as shown in
A preferred PR characteristic at the half rate is, for example, a PR(34) characteristic resulting from half-rating of the PR(3443) characteristic itself. As shown in
Generally, it is possible to realize switching between a PR(abba) characteristic at the channel rate and a PR(ab) characteristic at the half rate or switching between a PR(abbba) characteristic at the channel rate and a PR(aba) characteristic at the half rate. However, it is not limited to the switching of a filter characteristic that cannot be formed at the half rate, and only frequency characteristics may be switched. For example, switching between a PR(3443) characteristic and a PR(1221) characteristic may be realized.
The application of the method of switching the PR characteristic in conjunction with the switching of the sampling rate is not limited to the min-2T-system code used in, for example, HD DVDs. This method is applicable to the reproduction of the min-3T-system code used in, for example, DVDs in related art, as shown in
Deteriorations in performance at lower rates include a deterioration in detection accuracy in frequency and phase control. Short of time-base components at lower rates has a great effect on the frequency and phase control. In addition, since the data reproduction process cannot be started unless the phase control is finished, an acquisition operation in the frequency and phase control is very important.
According to the first embodiment of the present invention, the reproduction is performed at a higher rate in the frequency and phase acquisition and the higher rate is switched to a lower rate after the acquisition.
As a result, it is possible to maintain a higher accuracy in the frequency and phase detection by performing the acquisition at the higher rate even in the HD DVD adopting the min-2T-system code. Since the capture range can be expanded, it is possible to stabilize the reproduction operation. The higher rate may be set to a rate higher than the channel rate to perform oversampling. In this case, the accuracy can be further increased.
Referring to
In Step ST3, the reproducing apparatus 1 starts the frequency and phase acquisition at the higher rate. Various methods can be used to determine whether the frequency and phase acquisition is completed. For example, a SYNC code detection signal output from the synchronous demodulation circuit 44 may be used.
Specifically, the SYNC code detection signal is supplied from the synchronous demodulation circuit 44 to the sampling-rate switching control circuit 53, as shown in
The sampling-rate switching control circuit 53 supplies the rate switching signal to each circuit supporting varied rates and to the pre-equalizer 12 supporting varied characteristics. Each circuit supporting varied rates switches the rate of the circuit mode in response to the received rate switching signal. Particularly, the adaptive equalizer 30 resets the current learning value and resets the initial equalization coefficients for every rate in response to the rate switching signal.
The pre-equalizer 12 switches the characteristic for each rate to which the waveform equalization characteristics are set in advance to an optimal characteristic in response to the rate switching signal.
This switching realizes the waveform equalization characteristics in which the cutoff frequency, the boost frequency, and the amount of boost are adapted to the sampling rate.
As described above, performing the reproduction at the higher rate until the frequency and phase are locked and performing the reproduction at the lower rate after the frequency and phase are locked can realize both the stability of the acquisition and low power consumption.
In Step ST7, the reproducing apparatus 1 determines whether it is necessary to acquire the frequency and phase again. If the reproducing apparatus 1 determines that it is necessary to acquire the frequency and phase again because the frequency and phase is unlocked, the reproducing apparatus 1 goes back to Step ST3. In Step ST8, the reproducing apparatus 1 determines whether the reproduction operation is completed.
Sampling at a lower rate, such as the half rate, can decrease the amount of information concerning the time-base components to degrade the decoding result. Specifically, the BER (Byte Error Rate) derived from the correction result in the ECC circuit 45 can be increased. However, the apparatus is not damaged if the BER is 5×10−3 or less in view of the error correction capability of HD DVDs or DVDs in related art. Accordingly, if the quality of the reproduction signal in the PUH 10 is sufficiently higher than the above reference value (for example, 10−5 or less), the reproduction operation at the lower rate causes no problem. Performing the reproduction operation at a higher rate only if the BER is increased can keep the balance between the performance and the power consumption.
Although the sampling-rate switching control circuit 53 may be configured so as to switch the sampling rate on the basis of the BER information supplied from the ECC circuit 45, it is necessary to ensure at least the data size called an ECC block (182×208 Bytes in DVDs in related art and a double of 182×208 Bytes in HD DVDs) in order to measure the BER. Accordingly, this configuration is suitable for the rate switching in rereading (the operation of reading the same ECC black again because any uncorrectable error) but is impractical in switching of the sampling rate in real time (during the data transfer) because of too many delays.
According to the first embodiment of the present invention, as shown in
Referring to
In Step ST13, the signal quality evaluation circuit 52 evaluates an index of the signal quality. For example, an equalization error mean square value calculated on the basis of an equalization error signal supplied from the Viterbi decoder 43, a simulated bit error rate (SbER), a partial response signal-to-noise ratio (PRSNR), or a sequence amplitude margin (SAM) is used as the evaluation index of the signal quality.
If the evaluation index of the signal quality is worse than a predetermined threshold (the determination in Step ST 14 is affirmative) and if the lower sampling rate is used (the determination in Step ST15 is negative), then in Step ST16, the reproducing apparatus 1 switches the sampling rate from the lower rate to the higher rate to improve the signal quality.
In contrast, if the evaluation index of the signal quality is better than the predetermined threshold (the determination in Step ST14 is negative) and if the higher sampling rate is used (the determination in Step ST17 is negative), then in Step ST18, the reproducing apparatus 1 switches the sampling rate from the higher rate to the lower rate to reduce the power consumption.
The timing of the rate switching is important during the data transfer. The rate switching is accompanied by switching of the initial equalization coefficient or the sampling clock to prevent the switching from being smoothly performed. As a result, the data can be damaged or any loss of the data can be caused during the rate switching.
Accordingly, according to the first embodiment of the present invention, the switching between the higher rate and the lower rate is performed during a period other than the period when the user data is reproduced (the period when the data is transferred). The period other than the period when the user data is reproduced is exemplified by a reproduction period in a VFO (Variable Frequency Oscillator) area.
Referring to
In Step ST23, the reproducing apparatus 1 detects the VFO area. The detection of the VFO area is performed by the VFO area detection circuit 51.
The VFO area can be detected by using the VFO area detection circuit 51 having, for example, a configuration shown in
Referring to
The correlation calculating section 300 calculates the autocorrelation of an input signal to detect a constant periodical pattern specific to the VFO area. Specifically, in the correlation calculating section 300, flip-flops 301 are used to delay an input signal Y(k) for 4T. In other words, the output from the flip-flops 301 is denoted by Y(k−4) delayed from the input signal Y(k) by 4T.
A multiplier circuit 303 in the correlation calculating section 300 calculates Y(k)*Y(k−4). The 4T waveform pattern shown in
A counter 308 in the detecting section 305 counts up by one if the “UP input” is “1” and the output from the counter 308 is reset to zero if the “RST input is “1”. In other words, the counter 308 is counted up if a negative value is output from the averaging section 304 (in this case, the output of a comparator 306 is “1”) and the counter 308 is reset to zero if a positive value is output from the averaging section 304 (in this case, the output of an inverter 307 is “1”).
The output from the counter 308 is compared with a predetermined threshold (VFth) by a comparator 309. If the output from the counter 308 is larger than the threshold (VFth), the detection signal from the VFO area becomes “1”. With this configuration, the detection signal from the VFO area becomes “1” after about VFth+α bits since the reproduction operation in the VFO area is started and the detection signal from the VFO area becomes “0” almost simultaneously with the completion of the reproduction operation in the VFO area. It is possible to detect an occurrence of the VFO area in the above manner even in a certain level of the asynchronous state.
However, at the half rate, since the two flip-flops 301 cause the delay 4T, as shown in
In HD DVDs (HD DVD-Rs, HD DVD-RWs, and HD DVD-RAMs) supporting recording and reproduction, wobble signals may be used to detect the VFO area.
Accordingly, a wobble synchronization detection signal (refer to
For example, as shown in
Referring back to
If the reproducing apparatus 1 determines that the sampling rate is to be switched, in Step ST25, the reproducing apparatus 1 determines whether the reproduction signal reaches the VFO area. If the reproducing apparatus 1 determines that the reproduction signal reaches the VFO area, then in Step ST26, the reproducing apparatus 1 switches the sampling rate. If the reproducing apparatus 1 determines that the reproduction signal does not reach the VFO area, the reproducing apparatus 1 waits until the reproduction signal reaches the VFO area and switches the sampling rate. In Step ST27, the reproducing apparatus 1 determines whether the data transfer is completed.
In the switching of the sampling rate, the sampling-rate switching control circuit 53 supplies the rate switching signal to the pre-equalizer 12 and to each circuit supporting varied rates, as described above.
Setting the control gain of each circuit supporting varied rates (the offset control circuit 41, the asymmetry control circuit 42, and the phase comparator 24) to a higher value for a predetermined time period allows high-speed acquisition operation and smooth rate switching.
However, it is not possible to perform the adaptive learning in the VFO area because the adaptive learning tends to diverge in principle with a signal having a higher autocorrelation. Accordingly, only the initial equalization coefficient is set in the VFO area and the adaptive learning is started after the detection signal of the VFO area falls. However, the detection signal can temporarily fall during the rate switching. In such a case, the adaptive learning is performed when the second detection signal of the VFO area falls, the second detection signal being detected immediately after the rate switching.
The lower sampling rate is not limited to the half rate and is set to a rate two-thirds of the channel rate in the second embodiment of the present invention.
Digital processing circuits have increasingly lowered the power consumption in recent years. In the reproducing apparatus 1a, the A/D converter 14 performing high-speed analog processing consumes several tens percent of the entire power. Accordingly, decreasing the sampling rate only in the A/D converter 14 can achieve power saving.
The lower sampling rate is set to the rate two-thirds of the channel rate in the second embodiment of the present invention because the signal bandwidth exists in an area having frequencies higher than one-fourth of the channel rate in HD DVDs adopting the min-2T-system code, as shown in
An operation of the reproducing apparatus 1a according to the second embodiment of the present invention will now be described.
At the higher rate (the channel rate), the reproduction signal subjected to the A/D conversion in the A/D converter 14 is supplied to an upsampling circuit 47. Since the sampling rate is set to the higher rate, it is not necessary to perform an upsampling process. Accordingly, the reproduction signal passes through the upsampling circuit 47 and is supplied an offset control circuit 41a. Since the subsequent processing is the same as in the first embodiment, a description is omitted herein.
After the rate switching signal is output from the sampling-rate switching control circuit 53, the sampling clock in the A/D converter 14 is switched from the higher rate to the lower rate. In this case, the sampling clock in the A/D converter 14 is set to two thirds of the channel rate.
In the case of a single speed HD DVD, since the channel rate is equal to 64.8 MHz, the reproduction signal is sampled at a sampling rate of 43.2 MHz. The reproduction signal subjected to the A/D conversion at this sampling clock is supplied to the upsampling circuit 47 where the reproduction signal is subjected to data interpolation into a channel rate of 64.8 MHz and the interpolated signal is output. The subsequent processing is the same as at the higher rate and is performed at the channel rate. According to the second embodiment of the present invention, since the digital circuit downstream of the upsampling circuit 47 operates at the sampling rate corresponding to the channel rate regardless of the higher rate and the lower rate, the same configuration as in the first embodiment can be used and there is no need for the circuit components to support varied rates.
However, since it is necessary to switch the sampling clock to be supplied to the A/D converter 14, the rate switching signal is supplied to a VCO 21a where the division ratio is controlled so as to output the clock signal at a rate two thirds of the channel rate. The rate switching signal may be supplied to the loop filter 22 where the division ratio is controlled so as to output the clock signal at a rate two thirds of the channel rate.
An example of application of the asynchronous sampling method to an optical disc is disclosed in JP-A 2001-195830. In the asynchronous sampling method, the A/D converter 14 samples the reproduction signal asynchronously with the channel clock included in the reproduction signal and the signal asynchronously sampled is synchronized with the channel clock in a downstream digital phase locking unit 60 including a digital interpolation filter 61.
This signal processing method has several advantages. Particularly, since the phase control loop need not include the A/D converter 14, it is possible to ignore any delay in the A/D converter 14 and to ensure sufficient phase margin in the control loop.
In addition, when the output signal from the adaptive equalizer 30 is used to control the phase, as shown in
Since this asynchronous sampling method is presented as a reference method in HD DVD standard, it is necessary to measure SbER and PRSNR by this method.
In this asynchronous sampling method, the asynchronous sampling rate should generally be set to a rate five to ten percent higher than the reproduction rate in order to ensure the accuracy of the digital interpolation filter 61 used for the phase control. In HD DVD standard, the asynchronous sampling rate is set to 72 MHz, which is 1.1 times higher than the channel rate.
Accordingly, when the HD DVD standard is applied to the third embodiment of the present invention, for example, the higher sampling rate is set to a rate 1.1 times higher than the channel rate and the lower sampling rate is set to a rate 0.55 (0.5×1.1) times higher than the channel rate.
An operation of the reproducing apparatus 1b according to the third embodiment of the present invention will now be described with reference to
At the higher rate, the digital reproduction signal subjected to the A/D conversion at the sampling rate 1.1 times higher than the channel rate is subjected to the waveform shaping in the offset control circuit 41 supporting the varied rates and the asymmetry control circuit 42 supporting varied rate. Since both the offset control circuit 41 and the asymmetry control circuit 42 support asynchronous processing, the offset control circuit 41 and the asymmetry control circuit 42 are capable of operating in the asynchronous state in which the sampling rate is 1.1 times higher than the channel rate.
The adaptive equalizer 30 performs the adaptive learning to the signal subjected to the waveform shaping to equalize the signal to a desired PR class. The adaptive learning should be performed so as to equalize the waveform at the sampling rate 1.1 times higher than the channel rate. However, since the downstream Viterbi decoder 43 operates at the channel rate, the equalization error signal supplied from the Viterbi decoder 43 to the equalization coefficient learning circuit 32 in the adaptive equalizer 30 also has the channel rate. In other words, since the reproduction signal supplied to the adaptive equalizer 30 is asynchronous with the equalization error signal supplied thereto, it is necessary for the equalization coefficient learning circuit 32 to synchronize the reproduction signal with the equalization error signal to determine the amount of update of the equalization coefficient.
The signal output from the adaptive equalizer 30 is supplied to the digital interpolation filter 61. A phase comparator 63 supporting varied rates and a phase control loop filter 62 control the phase of the signal supplied to the digital interpolation filter 61 so as to be synchronized with the channel rate. The digital interpolation filter 61 is, for example, an FIR filter having several taps, as disclosed in JP-A 2001-195830, and selects a tap coefficient on the basis of the phase information.
Since the reproduction signal supplied from the digital interpolation filter 61 is synchronized with the channel rate, the reproduction signal is supplied to the Viterbi decoder 43 where the reproduction signal is decoded into binary data, and the binary data is supplied to the downstream components.
A frequency detector 23b supporting varied rates in a frequency lock loop unit 20b detects a difference in frequency between the frequency of the reproduction signal subjected to the waveform shaping and the rate 1.1 times higher than the channel rate. The frequency detector 23b supplies the difference in frequency to a frequency control loop filter 22b. The frequency control loop filter 22b controls the VCO 21 so as to generate an asynchronous clock signal having a rate 1.1 times higher than the channel rate.
The basic operation is the same as the above operation also when the lower sampling rate is selected in response to the rate switching signal. The sampling rate in the A/D converter 14 is set to a rate 0.55 times higher than the channel rate. The data sampled at the sampling rate 0.55 times higher than the channel rate is output from the digital interpolation filter 61 at a rate (half rate) 0.5 times higher than the channel rate.
Although both the oversampling ratios of the higher rate and the lower rate are 10% in the third embodiment of the present invention, it is not necessary to set the same oversampling ratio for the higher rate and the lower rate. The oversampling ratio for the higher rate may be different from that for the lower rate.
A binary slicing circuit, on which the DVD standard in the related art adopting the min-3T-system code is premised, can be used to ensure a desired BER.
Since the read-in area on each HD DVD adopting the min-2T-system code has a liner density half of that of the data area, the binary slicing circuit can be used to read data.
With the object of the power consumption, the binary slicing circuit consumes much lower power than the PRML signal processing method because, for example, the A/D converter is not necessary.
An apparatus 1c for reproducing data on a recording medium (hereinafter referred to as a reproducing apparatus 1c) according to a fourth embodiment of the present invention includes both a binary slicing circuit and a PRML signal processing circuit and performs switching between the binary slicing circuit and the PRML signal processing circuit on the basis of the signal quality.
Referring to
As in the first embodiment of the present invention, the analog reproduction signal (radio frequency (RF) signal) of which the amplitude control is completed in the amplitude control circuit 13 is supplied to both the PRML signal processing circuit 70 and the binary slicing circuit 71. However, only one of the PRML signal processing circuit 70 and the binary slicing circuit 71 operates in response to a data-demodulating-unit switching signal supplied from a data-demodulating-unit switching control circuit 74 described below. For example, if the binary slicing circuit 71 is selected, the PRML signal processing circuit 70 does not operate because of gated clock and the power of an A/D converter 14 is reduced to prevent the power from being wastefully consumed.
The binary data demodulated by the PRML signal processing circuit 70 or the binary slicing circuit 71 is supplied to the synchronous demodulation circuit 44. The synchronous demodulation circuit 44 operates in the manner described above in the first embodiment to convert the binary data into demodulation data, which is Byte data. The demodulation data is supplied to the ECC circuit 45 where the demodulation data is subjected to error correction. The ECC circuit 45 counts the number of errors in the ECC block subjected to the error correction to measure the BER. The BER information is supplied to the data-demodulating-unit switching control circuit 74.
For example, when the binary slicing circuit 71 is selected, the data-demodulating-unit switching control circuit 74 does not perform the switching if the BER information indicates that a sufficiently low error rate is maintained. In contrast, the data-demodulating-unit switching control circuit 74 outputs the data-demodulating-unit switching signal to perform switching from the binary slicing circuit 71 to the PRML signal processing circuit 70 if the error rate is lowered or if an uncorrectable error occurs to read the data again. As described above, the binary slicing circuit 71, which does not use the A/D converter 14, is used if a sufficient high signal quality is maintained while the PRML signal processing circuit 70 is used if the signal quality is to be improved.
A difference in performance between the binary slicing circuit 71 and the PRML signal processing circuit 70 involved in the improvement of the signal quality is shown in
As apparent from
As described above in the first embodiment, since it takes time to release the measurement result of the BER, the performance may be evaluated with performance evaluating means that takes only a short time to release the measurement result.
If the PRML signal processing circuit 70 is selected, an evaluation index generated by processing the equalization error signal, such as the SbER, output from the PRML signal processing circuit 70 is used.
If the binary slicing circuit 71 is selected, the amount of timing fluctuation (the amount of jitter) between a data edge and a clock edge is generally used as the evaluation index.
In the reproducing apparatus 1c shown in
Referring back to
If the signal quality is low (the determination in Step ST34 is affirmative) and if the binary slicing circuit 71 is selected (the determination in Step ST37 is negative), then in Step ST38, the reproducing apparatus 1c performs switching from the binary slicing circuit 71 to the PRML signal processing circuit 70.
In contrast, if the signal quality is high (the determination in Step ST34 is negative) and if the PRML signal processing circuit 70 is selected (the determination in Step S35 is negative), then in Step ST36, the reproducing apparatus 1c performs switching from the PRML signal processing circuit 70 to the binary slicing circuit 71.
The data-demodulating-unit switching signal is also supplied to the pre-equalizer 12 supporting varied characteristics. The pre-equalizer 12 is configured so as to perform switching between equalizer characteristics optimal to the PRML signal processing circuit 70 and equalizer characteristics optimal to the binary slicing circuit 71.
For example, if the PRML signal processing circuit 70 is selected, the evaluation index of the signal quality, such as the SbER, is set so as to be a minimum value. If the binary slicing circuit 71 is selected, the amount of jitter is set so as to be a minimum value. Since different parts of the reproduction signal are evaluated when the evaluation index of the signal quality is used and when the amount of jitter is used, the optimal characteristics for the evaluation index of the signal quality do not necessarily coincide with those for the amount of jitter. Consequently, it is desirable that the characteristics be switched depending on the used signal processing circuit.
As described above, in the reproducing apparatuses 1, 1a, and 1b according to the first to third embodiments of the present invention, it is possible to switch from the normal sampling rate to the lower sampling rate even in the min-2T-system code used in HD DVDs without spoiling the operational stability, thus reducing the power consumption.
In the min-3T-system code, appropriately setting the timing of switching from the higher rate to the lower rate allows the switching stability to be improved. In addition, changing the PR class between at the higher rate and at the lower rate improves the performance.
In the reproducing apparatus 1c according to the fourth embodiment of the present invention, the provision of both the PRML method and the binary slicing method without the A/D conversion and the switching between the PRML method and the binary slicing method on the basis of the signal quality allow the power consumption to be reduced while maintaining the signal quality.
Although the optical disc is exemplified as the recording medium in the above description, the embodiments of the present invention are applicable to another recording medium adopting the PRML method, such as a magneto-optical disk or a magnetic disk.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006181619 | Jun 2006 | JP | national |
