1. Technical Field
The present invention relates to data processing in general, and in particular to an apparatus for solving differential equations. Still more particularly, the present invention relates to an apparatus for solving very-large scale systems of time-continuous differential equations.
2. Description of Related Art
Generally, analog computers can be set up to solve very-large scale systems of time-continuous differential equations. However, difficulties may arise due to a number of factors. For example, magnitude scaling problems arise when analog components exceed the limits imposed by supply voltages, and time scaling problems may occur from time constants associated with analog integrators. In addition, accuracy problems can be caused by factors such as components not being of desired values, circuit analysis approximations, and intrinsic electronic noise generated by resistors (thermal noise), direct currents (shot noise), active devices (flicker and popcorn noise), etc. Hence, although analog computers can be a powerful tool for solving very-large scale systems of differential equations, their power is severely restrained by the above-mentioned problems.
On the other hand, time-continuous differential equations may be simulated and numerically solved by using digital computers with an appropriate numerical method. With derivatives approximated by finite differences, a system of time-continuous differential equations can be converted into an equivalent system of time-discrete difference equations. However, solving a dynamic system using difference equations may lead to numerical instability and accuracy problems, which include stiff system issues, function smoothness difficulties, rounding and truncation errors, and error buildup. Thus, the usage of digital computers to solve time-continuous differential equations also suffer from various limitations.
Consequently, it would be desirable to provide an improved apparatus for solving very-large scale systems of time-continuous differential equations.
In accordance with a preferred embodiment of the present invention, an apparatus for solving systems of time-continuous differential equations includes a group of hybrid integrators interconnected to each other. Each one of the hybrid integrators includes an analog integrator, a conversion logic and multiple digital registers. The analog integrator generates an analog output, and the conversion logic along with the digital registers converts the analog output to a digital output. The analog output and the digital output are then combined to yield an integrated output. The integrated output is fed to the hybrid integrators within the group.
All features and advantages of the present invention will become apparent in the following detailed written description.
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
In general, a differential equation has a derivative x′=dx/dt, and the derivative can be expressed as:
X/=f(X,t) (1)
Equation (1) is written in vector form. With f(X,t) being linear, equation (1) can be represented by a system of linear equations as follows:
for k=1, 2, . . . , n. The right-hand side of equation (2) can be integrated into states xk(t) by using an analog computer having multiple integrators. Algebraic operations such as additions, multiplications, and divisions inherent in f(X,t) can be implemented with active analog circuits such as operational amplifiers, augmented with digital circuits such as embedded logic.
Referring now to the drawings and in particular to
Since hybrid integrators 11-14 are substantially identical to each other, only hybrid integrator 11 will be further described. With reference now to
Referring now to
Instead of placing initial charges onto capacitors 33 as is done in the prior art, the initial conditions of hybrid integrator 11 can be set by loading a set of binary numbers into exponent register 37a and mantissa registers 37b.
A register value m within mantissa register 37b may be adjusted when output λ1 of operational amplifier 32 is approximately equal to an overflow value or an underflow value. A register value p within exponent register 37a may be adjusted in response to a change in register value m within mantissa register 37b. The exponent register 37a along with exponent registers from other integrators influence multiplier register 37c.
During operation, register values p and m within registers 37a and 37b, respectively, change continuously. In order to record the solution of a differential equation, the contents of registers 37a and 37b may be transferred to a system memory within a digital computer (not shown). The smallest “time step” δt for fetching the solution may be limited by the rate of data transfer to the system memory of the digital computer. By controlling the sizes of various capacitors and resistors within hybrid integrator 11 and the rate of presentation of input signals g1, x1 and xj, where j=2 to 4, the digital computer may control the output speed of the differential equation solution.
Combination circuit 26, which includes a resistor ladder 35 and an operational amplifier 36, combines the analog output of x1 (λ1) and the digital output of x1 to yield integrated output x1. Operational amplifier 36 provides integrated output x1 that is approximately equal to an analog output Vm of m of mantissa register 37b plus the output λ1 of operational amplifier 32. Integrated output x1 from operation amplifier 36 can be scaled.
The threshold voltage Vo=2(1-N) Vs at node y is the nodal voltage for the least significant bit of resistor ladder 35, where N is the number of bits for resistor ladder 35.
During operation, a positive input voltage Vi applied to analog integrator 22 may pass through two operational amplifiers 32, 36, rendering a positive integrated output x1. For the sign of component Vm to be consistent, the supply voltage Vs to resistor ladder 35 may be set to a negative value, since resistor ladder 35's output passes through the negative input of operational amplifier 36. For resistor ladder 35 to provide negative values, a sign bit and an appropriate arithmetic, such as 2's complement arithmetic, should be included. To implement 2's complements in the converter output voltages, when the sign bit is set, an additional voltage can be added to operational amplifier 36.
Although the above-mentioned scheme may extend the range of operational amplifier 32, registers 37a, 37b may eventually overflow or underflow, creating a different magnitude scaling problem. For example, if all bits (excluding the sign bit) of the mantissa m are set, overflow of operational amplifier 32 initiates an increment sequence, and register 37b will be overflowed. Such situation can be avoided by introducing an exponent p and extending x to floating point numbers: (m+λ) now becomes an extended mantissa, and the integral is augmented to x=(m+λ) 2p. The value of the exponent p may be increased or decreased to prevent saturation of operational amplifier 32, or to compensate for overflow or underflow of the mantissa m.
Several benefits may accrue. For example, the exponent factor 2p may be used to scale the variable (m+λ), “sliding” the operating range of hybrid integrator 11 up or down as needed to avoid operational amplifier saturation, or “wash out” of small signals by underlying noise. The floating point representation (m+λ)2p is compatible with the digital computer. A logic block 39 can be used to change the gains of operational amplifier 32 and to move or “slide” the voltage range of hybrid integrator 11. Furthermore, overflow can be compensated by rotating mantissa register 37b to the right one single bit, followed by incrementing exponent p. Rotating right divides the mantissa and voltage Vm in half. In order to compensate for such effect, exponent p may be incremented.
Such operations may scale the local state variable xk={overscore (x)}k 2p
Since the other hybrid integrators expect xk and not {overscore (x)}k, the scaling factor 2p
For other hybrid integrators feeding their scaled variables xk={overscore (x)}k 2p
This redefines the gain from other hybrid integrators from ajk to {overscore (a)}jk=2p
As has been described, the present invention provides an apparatus for solving differential equations.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
The present application claims benefit of priority under 35 U.S.C. §§ 120, 365 to the previously filed international patent application number PCT/US2004/019476 entitled, “Hybrid Computation Apparatus, Systems, and Methods,” filed on Jun. 17, 2004 having a priority date of Jun. 17, 2003 based upon U.S. Patent Application No. 60/479,197, both of which are incorporated by reference herein.
Number | Date | Country | |
---|---|---|---|
60479197 | Jun 2003 | US |
Number | Date | Country | |
---|---|---|---|
Parent | PCT/US04/19476 | Jun 2004 | US |
Child | 11303172 | Dec 2005 | US |