Claims
- 1. An apparatus for the synchronization control of a plurality of inverters, comprising:
- a reference pulse oscillator;
- synchronizing signal generating means responsive to the output of the reference pulse oscillator for generating distinct synchronizing signals having different widths from that of the output of the reference pulse oscillator, for adding said generated synchronizing signals to the output of the reference pulse oscillator, and for supplying an output corresponding to the sum thereof; and,
- a plurality of gate control means responsive to the output of the synchronizing signal generator for controlling the gates of said inverters, each gate control means coupled to a respective inverter and including means for detecting the synchronizing signals from the output of said synchronizing signal generating means and means for synchronizing the gates of said inverters by means of said detected synchronizing signals.
- 2. An apparatus for the synchronization control of a plurality of inverters, comprising:
- a reference oscillator;
- synchronizing signal generating means responsive to the output of said reference oscillator for generating distinct synchronizing signals having different widths from that of the output of said reference pulse oscillator, for adding the generated synchronizing signals to the output of said reference oscillator, and for supplying an output corresponding to the sum thereof; and
- a plurality of gate control means responsive to the output of said synchronizing signal generator for controlling the gates of said inverters, each gate control means coupled to a respective inverter, and comprising a synchronizing signal detector for detecting synchronizing signals from the output of said synchronizing signal generating means, and a ring counter responsive to the output of said synchronizing signal generating means and controlled by the output of said synchronizing signal detector signal means wherein each of said gate control means includes a synchronizing signal detector, and an AND logic gate having one input terminal connected to the output terminal of said synchronizing signal detector and another input terminal for receiving run command signals, a flip-flop having a set terminal connected to the output terminal of said AND logic gate, said flip-flop having a reset terminal for receiving stop command signals, and a monostable multivibrator connected to the output terminal of said flip-flop.
Parent Case Info
This is a continuation of application Ser. No. 762,279, filed Jan. 25, 1977, now U.S. Pat. No. 4,171,517, issued Oct. 16, 1979.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
3581213 |
Grump |
May 1971 |
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3586884 |
Gassmann |
Jun 1971 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
762279 |
Jan 1977 |
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