BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing the top view of a commercial electronic product.
FIG. 2 is a diagram showing an exemplary apparatus for testing an integrated circuit according to the present invention.
FIGS. 3A and 3B are diagrams showing other apparatus for testing an integrated circuit according to the present invention.
FIG. 4 is a diagram showing a single-chip socket of the present invention.
FIG. 5 is a diagram showing a multi-chip socket of the present invention.
FIGS. 6A, 6B, 6C, and 6D are diagrams showing example detector circuits of the present invention.
FIG. 7 is a diagram schematically representing a detector circuit of the present invention.
FIG. 8 is a diagram showing a top view of an apparatus of the present invention.
FIG. 9 is a diagram showing a side view of the apparatus of FIG. 8.
FIGS. 10A and 10B are diagrams showing an alternative embodiment of the present invention.
FIG. 11 is a diagram showing top view of yet another apparatus of the present invention.
FIG. 12 is a diagram showing a side view of another apparatus of the present invention.
FIG. 13 is a diagram showing detail of Area A of FIG. 12.
FIG. 14 is a diagram showing an other apparatus of the present invention.
FIG. 15 is a diagram showing an exemplary apparatus for testing an integrated circuit according to the present invention.
FIG. 16 is a diagram showing another exemplary apparatus for testing an integrated circuit according to the present invention.
FIG. 17 is a diagram showing yet another exemplary apparatus for testing an integrated circuit according to the present invention.