Claims
- 1. A switch comprising
a plurality of field effect transistors (FETs) connected together in series; and a bypass resistance topology coupled in parallel to at least some subset of said plurality of FETs.
- 2. The switch of claim 1, wherein said bypass resistance topology is coupled between a source of a first FET of said plurality of FETs and a drain of a last FET of said plurality of FETs.
- 3. The switch of claim 2, wherein said bypass resistance topology includes at least one resistor coupled between the source of the first FET and the drain of the last FET.
- 4. The switch of claim 2, wherein said bypass resistance topology includes a plurality of resistors, at least one resistor coupled between a source and a drain for each FET of said plurality of FETs.
- 5. The switch of claim 1, wherein said bypass resistance topology provides an alternative path for current to flow from a source voltage input to an output.
- 6. The switch of claim 1, further comprising at least one feed-forward capacitor coupled to at least one of said plurality of FETs.
- 7. The switch of claim 6, wherein said at least one feed-forward capacitor is coupled to a gate and a source of at least one of said plurality of FETs.
- 8. The switch of claim 6, wherein said at least one feed-forward capacitor is coupled to a gate and a drain of at least one of said plurality of FETs.
- 9. The switch of claim 6, wherein said at least one feed-forward capacitor includes a first feed-forward capacitor coupled to a first FET of said plurality of FETs and a second feed-forward capacitor coupled to a last FET of said plurality of FETs.
- 10. The switch of claim 9, wherein the first feed-forward capacitor is coupled to a source and a gate of the first FET and the second feed-forward capacitor is coupled to a drain and a gate of the last FET.
- 11. The switch of claim 1, wherein a first FET of said plurality of FETs is connected to a source voltage input.
- 12. The switch of claim 1, wherein a last FET of said plurality of FETs is connected to an output.
- 13. The switch of claim 1, wherein a gate of each FET of said plurality of FETs is connected to a control voltage input.
- 14. The switch of claim 13, further comprising a resistance coupled between at least a subset of the gates and the control voltage input.
- 15. The switch of claim 14, wherein said resistance includes a plurality of first resistors, at least one first resistor coupled between a gate of each of said plurality of FETs and the control voltage input.
- 16. The switch of claim 15, wherein each of the at least one first resistors is parallel to each other.
- 17. The switch of claim 15, wherein said resistance further includes a second resistor coupled between each of the at least one first resistors and the control voltage input.
- 18. The switch of claim 17, wherein the second resistor is coupled in series to each of the at least one first resistors.
- 19. The switch of claim 15, wherein said resistance further includes a plurality of second resistors, at least one second resistor coupled between each of two successive at least one first resistors and the control voltage input.
- 20. The switch of claim 19, wherein each of the at least one second resistors is in parallel with each other at least one second resistor and in series with each of the at least one first resistors it is coupled to.
- 21. The switch of claim 14, wherein said resistance includes
a plurality of first resistors, at least one first resistor coupled between the gate of a first FET and the control voltage input and at least one first resistor coupled between the gate of a last FET and the control voltage input; a plurality of second resistors, at least one second resistor coupled to the gate of each remaining FET; and a third resistor coupled between each of the at least one second resistors and the control voltage input.
- 22. The switch of claim 21, wherein each of the at least one second resistors is in parallel with each other, the third resistor is in series to each other of the at least one second resistors, and each of the first resistors is in parallel to each second resistor and third resistor combination.
- 23. The switch of claim 14, wherein said resistance includes
a plurality of first resistors, at least one first resistor coupled between the gate of a first FET and the control voltage input and at least one first resistor coupled between the gate of a last FET and the control voltage input, a plurality of second resistors, at least one second resistor coupled to the gate of each remaining FET; and a plurality of third resistors, at least one third resistor coupled between each of two successive second resistors and the control voltage input.
- 24. The switch of claim 23, wherein the each of two successive second resistors is in parallel with each other, each of the at least one third resistors is in parallel with each other and is in series with the two successive second resistors it is coupled to, and each of the first resistors is in parallel to each second resistor and third resistor combination.
- 25. The switch of claim 1, wherein said plurality of FETs includes six gates.
- 26. The switch of claim 25, further comprising a first feed-forward capacitor coupled to a source and a gate of a first FET of said plurality of FETs and a second feed-forward capacitor coupled to drain and a gate of a last FET of said plurality of FETs
- 27. The switch of claim 1, wherein said plurality of FETs have a single gate architecture.
- 28. The switch of claim 1, wherein said plurality of FETs have a multi gate architecture.
- 29. The switch of claim 1, wherein said plurality of FETs have a mixed gate architecture.
- 30. A switch comprising:
a plurality of field effect transistors (FETs) connected together in series, each FET having a source, a drain and at least one gate, the plurality of FETs having a total of six gates therebetween; a bypass resistance topology connected between the source of a first FET of said plurality of FETs and the drain of a last FET of said plurality of FETs; a first feed-forward capacitor coupled between the source and the gate of the first FET; and a second feed-forward capacitor coupled between the drain and the gate of the last FET.
- 31. The switch of claim 30, wherein said bypass resistance topology includes a single resistor.
- 32. The switch of claim 30, wherein said bypass resistance topology includes a plurality of resistors.
- 33. The switch of claim 32, wherein at least one resistor is coupled between a source and drain for each FET of said plurality of FETs.
- 34. The switch of claim 30, further comprising a gate resistance topology coupled between the six gates and a control voltage input.
- 35. The switch of claim 34, wherein said gate resistance topology includes at least one resistor coupled between each gate and the control voltage input.
- 36. The switch of claim 35, wherein each of the at least one resistors coupled between each gate and the control voltage input is in parallel with all other of the at least one resistors.
- 37. The switch of claim 35, wherein at least some portion of the at least one resistor coupled between a gate and the control voltage input includes a plurality of resistors in series with each other.
- 38. A device having a plurality of switches in parallel to each other and tied to same source voltage input, each switch comprising:
a plurality of field effect transistors (FETs) connected together in series, said plurality of FETs including an uppermost FET connecting to the source voltage input and a lowermost FET connecting to an output; and a bypass resistance topology connected between a source of the first FET of said plurality of FETs and a drain of the last FET of said plurality of FETs.
- 39. The device of claim 38, wherein each switch further comprises
a first feed-forward capacitor coupled between the source and a gate of the uppermost FET; and a second feed-forward capacitor coupled between the drain and a gate of the lowermost FET.
- 40. The device of claim 38, wherein each switch further comprises a gate resistance topology coupled between gates of each FET and a control voltage input.
- 41. The device of claim 38, wherein each switch includes six gates.
- 42. A method for producing a switch having a sharpened control voltage, the method comprising:
forming a plurality of field effect transistors (FETs) connected together in series; connecting a first FET to a source voltage source; connecting each gate to a control voltage source; connecting a last FET to an output; and connecting a resistance from the source voltage source to the output so as to be in parallel with the plurality of FETs.
- 43. The method of claim 42, wherein said connecting a resistance includes connecting a resistor in parallel to all of the plurality of FETs.
- 44. The method of claim 42, wherein said connecting a resistance includes connecting a resistor in parallel to each FET of the plurality of FETs.
- 45. The method of claim 42, further comprising connecting at least one feed forward capacitor to one of the plurality of FETs.
- 46. The method of claim 45, wherein said connecting at least one feed forward capacitor includes connecting the feed forward capacitor between a gate and either a source or a drain of the one of the plurality of FETs.
- 47. The method of claim 45, wherein said connecting at least one feed forward capacitor includes connecting a first feed-forward capacitor to a source and a gate of a first FET and a second feed-forward capacitor to a drain and a gate of a last FET.
- 48. The method of claim 42, further comprising connecting a resistance between at least a subset of the six gates and the control voltage source.
- 49. The method of claim 42, wherein said forming includes forming a plurality of FETs having a total of six gates.
- 50. A method for sharpening the control voltage of a solid state switch including a plurality of field effect transistors (FETs) connected together in series, the method comprising forming at least one resistive path in parallel with at least one FET so as to provide an alternative current path from a source voltage source to an output.
- 51. The method of claim 50, wherein said forming includes forming a single resistive path in parallel with all of the plurality of FETs.
- 52. The method of claim 50, wherein said forming includes forming a separate resistive path in parallel to each FET of the plurality of FETs.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims the priority of U.S. Provisional Patent Application Serial No. 60/410647, filed on Sep. 13, 2002, which is herein incorporated in its entirety by reference.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60410647 |
Sep 2002 |
US |