BRIEF DESCRIPTION OF THE DRAWINGS
The various objects and advantages of the invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:
FIG. 1 is a block diagram of a conventional Viterbit decoder applied in a partial response maximum likelihood device;
FIG. 2 shows trellis diagrams of the invention with a channel memory length n=3 and a coding constraint d=0, 1, 2, and ½, respectively;
FIG. 3 shows trellis diagrams of the invention with a channel memory length n=4 and a coding constraint d=0, 1, 2, and ½, respectively;
FIG. 4 shows trellis diagrams of the invention with a channel memory length n=3, 4 and ¾ and a coding constraint d=½, respectively;
FIG. 5 shows a trellis diagram of the invention with a channel memory length n=¾ and a coding constraint d=½;
FIG. 6A is a system block diagram of an apparatus for maximum likelihood signal detection according to a first embodiment of the invention;
FIG. 6B is a more detailed system block diagram for an apparatus of maximum likelihood signal detection according to the first embodiment of the invention;
FIG. 7 is a system block diagram of an apparatus for maximum likelihood signal detection according to a second embodiment of the invention;
FIG. 8 is a system block diagram of an apparatus for maximum likelihood signal detection according to a third embodiment of the invention;
FIG. 9A is a system block diagram of an apparatus for maximum likelihood signal detection according to a fourth embodiment of the invention;
FIG. 9B is another system block diagram of an apparatus for maximum likelihood signal detection according to the fourth embodiment of the invention;
FIGS. 10A and 10B are trellis diagrams of the invention with a channel memory length n=3, a coding constraint d=½ and a number of read bit M=2;
FIGS. 11A and 11B are trellis diagrams of the invention with a channel memory length n=4, a coding constraint d=½ and a number of read bit M=2;
FIG. 12 is a trellis diagram of the invention with a channel memory length n=¾, a coding constraint d=½ and a number of read bit M=2;
FIG. 13 is another trellis diagram of the invention with a channel memory length n=¾, a coding constraint d=½ and a number of read bit M=2; and
FIG. 14 is yet another trellis diagram of the invention with a channel memory length n=¾, a coding constraint d=½ and a number of read bit M=2.