Patent Grant
11573909
This invention relates to solid-state storage and more particularly relates to efficiently managing command execution in solid-state storage using a bank interleave controller.
Data storage devices are typically write-in-place in that data accessed at a particular location can be modified and then put back in the same location. A file or object may be divided and placed piecemeal in the data storage device in various locations where no data is stored or where data is marked invalid. While this method works well for devices such as a hard disk drive (“HDD”), using write-in-place for solid-state storage can be inefficient and can cause premature failure.
Using write-in-place for solid-state storage can be inefficient because typically writing data often takes much longer than reading data. For flash memory, which is a type of solid-state storage, changing a bit from a “zero” state (“zero”) to a “one” state (“one”) usually takes longer than changing a bit from a one to a zero. This is the case for typical flash memory that uses capacitors as cells where a zero equates to a discharged capacitor in a cell and a one equates to a charged capacitor in a cell. Typically, charging a capacitor takes longer than discharging a capacitor.
Using write-in-place for solid-state storage can lead to premature failure of the solid-state storage because typically each cell in a solid-state storage device can only be written to a certain number of times before the cell begins to fail. Write-in-place typically does not evenly distribute writing data over the solid-state storage so some regions or addresses are used much more than other areas. This overuse of some areas can lead to premature failure of all or a portion of a solid-state storage device.
Traditional write-in-place and other data handling techniques associated data management techniques associated with write-in-place and other traditional storage prevent solid-state storage from achieving much higher possible performance.
From the foregoing discussion, it should be apparent that a need exists for an apparatus, system, and method that efficiently manage commands of a solid-state storage device. Beneficially, such an apparatus, system, and method would queue commands for each bank of a solid-state storage device and coordinate execution of the commands.
The present invention has been developed in response to the present state of the art, and in particular, in response to the problems and needs in the art that have not yet been fully solved by currently available solid-state storage. Accordingly, the present invention has been developed to provide an apparatus, system, and method for efficiently managing commands for solid-state storage using a bank interleave that overcome many or all of the above-discussed shortcomings in the art.
The apparatus includes a solid-state storage device to manage commands of a solid-state storage device is provided with a plurality of modules and hardware configured to functionally execute the necessary steps of directing commands to queues for each bank of a solid-state storage device and coordinate execution of the commands. The solid-state storage device in the described embodiments includes a solid-state storage arranged in two or more banks, each bank being separately accessible and each bank including two or more solid-state storage elements accessed in parallel by a storage input/output (“I/O”) bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave controller. The bank interleave controller directs one or more commands to two or more queues. The one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.
In one embodiment, the set of queues for a bank include a read queue to store read commands, a write queue to store write commands, an erase queue to store erase commands, and a management queue to store management commands and wherein the command types comprise at least read, write, and erase commands. In another embodiment, a read command reads data from a location within a page in the solid-state storage, a write command writes data to a storage write buffer, the storage write buffer located in the solid-state storage and comprising data for transfer to a designated page in the solid-state storage in response to a program command that programs data in the storage write buffer to the designated page, and an erase command to erase data in an erase block, an erase block comprising a plurality of pages in the solid-state storage.
In one embodiment, the command types also include a reset command to reset a bank and a read configuration register command to read a configuration register of a bank. The reset and read configuration register commands are stored in the management queue of each bank. In another embodiment, the bank interleave controller also coordinates execution of commands not stored the queues with execution of commands stored in the queues.
In one embodiment, the solid-state storage device includes a bank controller for each bank, where a bank controller for a bank receives and interprets a command from a queue of the bank and creates one or more subcommands from the received command. The one or more subcommands include commands directed at the bank. In the embodiment, the solid-state storage device also includes a bus arbiter that coordinates execution of the subcommands. In a further embodiment, the bank interleave controller uses predicted command execution duration information of commands and subcommands and status information received from the solid-state storage to predict and verify command completion as part of coordinating execution of the commands stored in the sets of queues.
In one embodiment, the bank interleave controller combines one or more data packets stored in a write buffer with a write command prior to sending the data packets and write command to the solid-state storage via a storage input/output (“I/O”) bus and receives one or more data packets and corresponding status and management data and forwards the data packets read from the solid-state storage to a read buffer and the corresponding status and management data to a management buffer. In one embodiment, the bank interleave controller coordinates execution of read commands, write commands, and erase commands on the two or more banks, where the read commands, write commands, and erase commands are stored in the set of queues for each bank, so that when a read, write, or erase command completes on one bank, another read, write, or erase command is sent to the bank.
In another embodiment, the storage I/O bus is asynchronous and transports data packets comprising control information and data. In another embodiment, the solid-state storage device includes a controller with a write data pipeline and a read data pipeline. The bank interleave controller coordinates reading and writing data with the write data pipeline and the read data pipeline. In various embodiments, the solid-state storage device may be configured in a dual-inline memory module (“DIMM”), a daughter card, a micro-module, etc. In other embodiments, the solid-state storage of the solid-state storage device may be flash memory, nano random access memory (“nano RAM” or “NRAM”), magneto-resistive RAM (“MRAM”), dynamic RAM (“DRAM”), phase change RAM (“PRAM”), etc. In yet another embodiment, commands sent to the solid-state storage are sent asynchronously.
In one embodiment, storage locations within a solid-state storage element of the two or more solid-state storage elements are accessed with a logical address mapped to one or more storage location by corresponding physical addresses of the one or more storage locations. In the embodiment, the solid-state storage device includes a remapping module that remaps a first logical address mapped to a first physical address to a second physical address such that data commands sent to a storage location represented by the first logical address are directed to the first physical address prior to remapping and to the second physical address after remapping.
In another embodiment, a write buffer accessible to the bank interleave controller and a storage write buffer within the solid-state storage, where the write buffer and the storage write buffer have a storage capacity equal to or greater than a page within the solid-state storage. In the embodiment, data to be written to the solid-state storage is stored in the write buffer and the bank interleave controller transfers data segments to fill a page of memory to the storage write buffer during a write operation. The data segments in the storage write buffer are subsequently stored in a page within the solid-state storage in response to a program command.
A system of the present invention is also presented to coordinate commands in a solid-state storage device using a bank interleave. The system may be embodied by a computer, a system bus, a solid-state storage device in communication with the computer via the system bus to service at least data read and write requests. In particular, the solid-state storage device, in one embodiment, includes a solid-state storage arranged in two or more banks, where each bank is separately accessible and each bank includes two or more solid-state storage dies accessed in parallel by a storage I/O bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave controller. The bank interleave controller includes a command segregation module that directs one or more commands to two or more queues. The one or more commands are separated by command type into the queues. The bank interleave includes a set of queues for each bank. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.
The system may further include a computer network and a client in communication with the computer through the computer network. The client sends data and management requests to the solid-state storage device through the computer. The computer forwards the data and management requests to the solid-state storage device and returns responses from the solid-state storage device to the client. In one embodiment, the system bus includes a peripheral component interconnect express (“PCI-e”) bus, a universal serial bus (“USB”) connection, an Institute of Electrical and Electronics Engineers (“IEEE”) 1394 bus, Infiniband, Ethernet, or a combination of the system bus types.
In one embodiment, the set of queues for a bank include a read queue to store read commands, a write queue to store write commands, an erase queue to store erase commands, and a management queue to store management commands and wherein the command types comprise at least read, write, program, and erase commands. In another embodiment, the system includes a controller. The controller includes a write data pipeline and a read data pipeline, where the bank interleave controller receives the one or more commands from the controller and coordinates reading and writing data with the write data pipeline and the read data pipeline.
A method of the present invention is also presented for managing commands of a solid-state storage device. The method in the disclosed embodiments substantially includes the steps necessary to carry out the functions presented above with respect to the operation of the described apparatus and system. In one embodiment, the method includes directing one or more commands to two or more queues of a solid-state storage device, where the one or more commands are separated by command type into the queues. The solid-state storage device includes solid-state storage arranged in two or more banks. Each bank is separately accessible and each bank includes two or more solid-state storage elements accessed in parallel by a storage I/O bus. The solid-state storage includes solid-state, non-volatile memory. Each bank includes a set of queues and each set of queues includes a queue for each command type. The method also includes coordinating among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.
Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussion of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.
Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize that the invention may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.
These features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:
Many of the functional units described in this specification have been labeled as modules, in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
Modules may also be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
Indeed, a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. Where a module or portions of a module are implemented in software, the software portions are stored on one or more computer readable media.
Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
Reference to a signal bearing medium may take any form capable of generating a signal, causing a signal to be generated, or causing execution of a program of machine-readable instructions on a digital processing apparatus. A signal bearing medium may be embodied by a transmission line, a compact disk, digital-video disk, a magnetic tape, a Bernoulli drive, a magnetic disk, a punch card, flash memory, integrated circuits, or other digital processing apparatus memory device.
Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
The schematic flow chart diagrams included herein are generally set forth as logical flow chart diagrams. As such, the depicted order and labeled steps are indicative of one embodiment of the presented method. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. Additionally, the format and symbols employed are provided to explain the logical steps of the method and are understood not to limit the scope of the method. Although various arrow types and line types may be employed in the flow chart diagrams, they are understood not to limit the scope of the corresponding method. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the method. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown.
Solid-State Storage System
The system 100 includes at least one solid-state storage device 102. In another embodiment, the system 100 includes two or more solid-state storage devices 102. Each solid-state storage device 102 may include non-volatile, solid-state storage 110, such as flash memory, nano random access memory (“nano RAM or NRAM”), magneto-resistive RAM (“MRAM”), dynamic RAM (“DRAM”), phase change RAM (“PRAM”), etc. The solid-state storage device 102 is described in more detail with respect to
In various embodiments, the solid-state storage device 102 may be in the form of a dual-inline memory module (“DIMM”), a daughter card, or a micro-module. In another embodiment, the solid-state storage device 102 is an element within a rack-mounted blade. In another embodiment, the solid state storage device 102 is contained within a package that is integrated directly onto a higher level assembly (e.g. mother board, lap top, graphics processor). In another embodiment, individual components comprising the solid-state storage device 102 are integrated directly onto a higher level assembly without intermediate packaging.
The solid-state storage device 102 includes one or more solid-state storage controllers 104, each may include a write data pipeline 106 and a read data pipeline 108 and each includes a solid-state storage 110, which are described in more detail below with respect to
The system 100 includes one or more computers 112 connected to the solid-state storage device 102. A computer 112 may be a host, a server, a storage controller of a storage area network (“SAN”), a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, router, or appliance, a database or storage appliance, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. In another embodiment, a computer 112 may be a client and the solid-state storage device 102 operates autonomously to service data requests sent from the computer 112. In this embodiment, the computer 112 and solid-state storage device 102 may be connected using a computer network, system bus, or other communication means suitable for connection between a computer 112 and an autonomous solid-state storage device 102.
In one embodiment, the system 100 includes one or more clients 114 connected to one or more computers 112 through one or more computer networks 116. A client 114 may be a host, a server, a storage controller of a SAN, a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, router, or appliance, a database or storage appliance, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. The computer network 116 may include the Internet, a wide area network (“WAN”), a metropolitan area network (“MAN”), a local area network (“LAN”), a token ring, a wireless network, a fiber channel network, a SAN, network attached storage (“NAS”), ESCON, or the like, or any combination of networks. The computer network 116 may also include a network from the IEEE 802 family of network technologies, such Ethernet, token ring, WiFi, WiMax, and the like.
The computer network 116 may include servers, switches, routers, cabling, radios, and other equipment used to facilitate networking computers 112 and clients 114. In one embodiment, the system 100 includes multiple computers 112 that communicate as peers over a computer network 116. In another embodiment, the system 100 includes multiple solid-state storage devices 102 that communicate as peers over a computer network 116. One of skill in the art will recognize other computer networks 116 comprising one or more computer networks 116 and related equipment with single or redundant connection between one or more clients 114 or other computer with one or more solid-state storage devices 102 or one or more solid-state storage devices 102 connected to one or more computers 112. In one embodiment, the system 100 includes two or more solid-state storage devices 102 connected through the computer network 116 to a client 114 without a computer 112.
Storage Controller-Managed Objects
In one embodiment, the storage controller 152 and data storage device 154 are separate devices. In another embodiment, the storage controller 152 and data storage device 154 are integrated into one storage device 150. In another embodiment, a data storage device 154 is a solid-state storage 110 and the storage controller 152 is a solid-state storage device controller 202. In other embodiments, a data storage device 154 may be a hard disk drive, an optical drive, tape storage, or the like. In another embodiment, a storage device 150 may include two or more data storage devices 154 of different types.
In one embodiment, the data storage device 154 is a solid-state storage 110 and is arranged as an array of solid-state storage elements 216, 218, 220. In another embodiment, the solid-state storage 110 is arranged in two or more banks 214a-n. Solid-state storage 110 is described in more detail below with respect to
The storage devices 150a-n may be networked together and act as a distributed storage device. The storage device 150a coupled to the requesting device 155 controls object requests to the distributed storage device. In one embodiment, the storage devices 150 and associated storage controllers 152 manage objects and appear to the requesting device(s) 155 as a distributed object file system. In this context, a parallel object file system is an example of a type of distributed object file system. In another embodiment, the storage devices 150 and associated storage controllers 152 manage objects and appear to the requesting device 155 as distributed object file servers. In this context, a parallel object file server is an example of a type of distributed object file server. In these and other embodiments the requesting device 155 may exclusively manage objects or participate in managing objects in conjunction with storage devices 150; this typically does not limit the ability of storage devices 150 to fully manage objects for other clients 114. In the degenerate case, each distributed storage device, distributed object file system and distributed object file server can operate independently as a single device. The networked storage devices 150a-n may operate as distributed storage devices, distributed object file systems, distributed object file servers, and any combination thereof having images of one or more of these capabilities configured for one or more requesting devices 155. Fore example, the storage devices 150 may be configured to operate as distributed storage devices for a first requesting device 155a, while operating as distributed storage devices and distributed object file systems for requesting devices 155b. Where the system 101 includes one storage device 150a, the storage controller 152a of the storage device 150a manages objects may appear to the requesting device(s) 155 as an object file system or an object file server.
In one embodiment where the storage devices 150 are networked together as a distributed storage device, the storage devices 150 serve as a redundant array of independent drives (“RAID”) managed by one or more distributed storage controllers 152. For example, a request to write a data segment of an object results in the data segment being striped across the data storage devices 154a-n with a parity stripe, depending upon the RAID level. One benefit of such an arrangement is that such an object management system may continue to be available when a single storage device 150 has a failure, whether of the storage controller 152, the data storage device 154, or other components of storage device 150.
When redundant networks are used to interconnect the storage devices 150 and requesting devices 155, the object management system may continue to be available in the presence of network failures as long as one of the networks remains operational. A system 101 with a single storage device 150a may also include multiple data storage devices 154a and the storage controller 152a of the storage device 150a may act as a RAID controller and stripe the data segment across the data storage devices 154a of the storage device 150a and may include a parity stripe, depending upon the RAID level.
In one embodiment, where the one or more storage devices 150a-n are solid-state storage devices 102 with a solid-state storage device controller 202 and solid-state storage 110, the solid-state storage device(s) 102 may be configured in a DIMM configuration, daughter card, micro-module, etc. and reside in a computer 112. The computer 112 may be a server or similar device with the solid-state storage devices 102 networked together and acting as distributed RAID controllers. Beneficially, the storage devices 102 may be connected using PCI-e, PCIe-AS, Infiniband or other high-performance bus, switched bus, networked bus, or network and may provide a very compact, high performance RAID storage system with single or distributed solid-state storage controllers 202 autonomously striping a data segment across solid-state storage 110a-n.
In one embodiment, the same network used by the requesting device 155 to communicate with storage devices 150 may be used by the peer storage device 150a to communicate with peer storage devices 150b-n to accomplish RAID functionality. In another embodiment, a separate network may be used between the storage devices 150 for the purpose of RAIDing. In another embodiment, the requesting devices 155 may participate in the RAIDing process by sending redundant requests to the storage devices 150. For example, requesting device 155 may send a first object write request to a first storage device 150a and a second object write request with the same data segment to a second storage device 150b to achieve simple mirroring.
With the ability for object handling within the storage device(s) 102, the storage controller(s) 152 uniquely have the ability to store one data segment or object using one RAID level while another data segment or object is stored using a different RAID level or without RAID striping. These multiple RAID groupings may be associated with multiple partitions within the storage devices 150. RAID 0, RAID 1, RAIDS, RAID6 and composite RAID types 10, 50, 60, can be supported simultaneously across a variety of RAID groups comprising data storage devices 154a-n. One skilled in the art will recognize other RAID types and configurations that may also be simultaneously supported.
Also, because the storage controller(s) 152 operate autonomously as RAID controllers, the RAID controllers can perform progressive RAIDing and can transform objects or portions of objects striped across data storage devices 154 with one RAID level to another RAID level without the requesting device 155 being affected, participating or even detecting the change in RAID levels. In the preferred embodiment, progressing the RAID configuration from one level to another level may be accomplished autonomously on an object or even a packet basis and is initiated by a distributed RAID control module operating in one of the storage devices 150 or the storage controllers 152. Typically, RAID progression will be from a higher performance and lower efficiency storage configuration such as RAID1 to a lower performance and higher storage efficiency configuration such as RAIDS where the transformation is dynamically initiated based on the frequency of access. But, one can see that progressing the configuration from RAIDS to RAID1 is also possible. Other processes for initiating RAID progression may be configured or requested from clients or external agents such a storage system management server request. One of skill in the art will recognize other features and benefits of a storage device 102 with a storage controller 152 that autonomously manages objects.
Apparatus for Storage Controller-Managed Objects
The storage controller 152 is substantially similar to the storage controller 152 described in relation to the system 101 of
In one embodiment, the object request is a write request to write all or part of an object to a previously created object. In one example, the write request is for a data segment of an object. The other data segments of the object may be written to the storage device 150 or to other storage devices. In another example, the write request is for an entire object. In another example, the object request is to read data from a data segment managed by the storage controller 152. In yet another embodiment, the object request is a delete request to delete a data segment or object.
Advantageously, the storage controller 152 can accept write requests that do more than write a new object or append data to an existing object. For example, a write request received by the object request receiver module 260 may include a request to add data ahead of data stored by the storage controller 152, to insert data into the stored data, or to replace a segment of data. The object index maintained by the storage controller 152 provides the flexibility required for these complex write operations that is not available in other storage controllers, but is currently available only outside of storage controllers in file systems of servers and other computers.
The apparatus 200 includes a parsing module 262 that parses the object request into one or more commands. Typically, the parsing module 262 parses the object request into one or more buffers. For example, one or more commands in the object request may be parsed into a command buffer. Typically the parsing module 262 prepares an object request so that the information in the object request can be understood and executed by the storage controller 152. One of skill in the art will recognize other functions of a parsing module 262 that parses an object request into one or more commands.
The apparatus 200 includes a command execution module 264 that executes the command(s) parsed from the object request. In one embodiment, the command execution module 264 executes one command. In another embodiment, the command execution module 264 executes multiple commands. Typically, the command execution module 264 interprets a command parsed from the object request, such as a write command, and then creates, queues, and executes subcommands. For example, a write command parsed from an object request may direct the storage controller 152 to store multiple data segments. The object request may also include required attributes such as encryption, compression, etc. The command execution module 264 may direct the storage controller 152 to compress the data segments, encrypt the data segments, create one or more data packets and associated headers for each data packet, encrypt the data packets with a media encryption key, add error correcting code, and store the data packets a specific location. Storing the data packets at a specific location and other subcommands may also be broken down into other lower level subcommands. One of skill in the art will recognize other ways that the command execution module 264 can execute one or more commands parsed from an object request.
The apparatus 200 includes an object index module 266 that creates an object entry in an object index in response to the storage controller 152 creating an object or storing the data segment of the object. Typically, the storage controller 152 creates a data packet from the data segment and the location of where the data packet is stored is assigned at the time the data segment is stored. Object metadata received with a data segment or as part of an object request may be stored in a similar way.
The object index module 266 creates an object entry into an object index at the time the data packet is stored and the physical address of the data packet is assigned. The object entry includes a mapping between a logical identifier of the object and one or more physical addresses corresponding to where the storage controller 152 stored one or more datapackets and any object metadata packets. In another embodiment, the entry in the object index is created before the data packets of the object are stored. For example, if the storage controller 152 determines a physical address of where the data packets are to be stored earlier, the object index module 266 may create the entry in the object index earlier.
Typically, when an object request or group of object requests results in an object or data segment being modified, possibly during a read-modify-write operation, the object index module 266 updates an entry in the object index corresponding the modified object. In one embodiment, the object index creates a new object and a new entry in the object index module 266 for the modified object. Typically, where only a portion of an object is modified, the object includes modified data packets and some data packets that remain unchanged. In this case, the new entry includes a mapping to the unchanged data packets as where they were originally written and to the modified objects written to a new location.
In another embodiment, where the object request receiver module 260 receives an object request that includes a command that erases a data block or other object elements, the storage controller 152 may store at least one packet such as an erase packet that includes information including a reference to the object, relationship to the object, and the size of the data block erased. Additionally, it may further indicate that the erased object elements are filled with zeros. Thus, the erase object request can be used to emulate actual memory or storage that is erased and actually has a portion of the appropriate memory/storage actually stored with zeros in the cells of the memory/storage.
Beneficially, creating an object index with entries indicating mapping between data segments and metadata of an object allows the storage controller 152 to autonomously handle and manage objects. This capability allows a great amount of flexibility for storing data in the storage device 150. Once the index entry for the object is created, subsequent object requests regarding the object can be serviced efficiently by the storage controller 152.
In one embodiment, the storage controller 152 includes an object request queuing module 268 that queues one or more object requests received by the object request receiver module 260 prior to parsing by the parsing module 262. The object request queuing module 268 allows flexibility between when an object request is received and when it is executed.
In another embodiment, the storage controller 152 includes a packetizer 302 that creates one or more data packets from the one or more data segments where the data packets are sized for storage in the data storage device 154. The packetizer 302 is described below in more detail with respect to
In one embodiment, each packet includes a packet identifier that is self-contained in that the packet identifier contains adequate information to identify the object and relationship within the object of the object elements contained within the packet. However, a more efficient preferred embodiment is to store packets in containers.
A container is a data construct that facilitates more efficient storage of packets and helps establish relationships between an object and data packets, metadata packets, and other packets related to the object that are stored within the container. Note that the storage controller 152 typically treats object metadata received as part of an object and data segments in a similar manner. Typically “packet” may refer to a data packet comprising data, a metadata packet comprising metadata, or another packet of another packet type. An object may be stored in one or more containers and a container typically includes packets for no more than one unique object. An object may be distributed between multiple containers. Typically a container is stored within a single logical erase block (storage division) and is typically never split between logical erase blocks.
A container, in one example, may be split between two or more logical/virtual pages. A container is identified by a container label that associates that container with an object. A container may contain zero to many packets and the packets within a container are typically from one object. A packet may be of many object element types, including object attribute elements, object data elements, object index elements, and the like. Hybrid packets may be created that include more than one object element type. Each packet may contain zero to many elements of the same element type. Each packet within a container typically contains a unique identifier that identifies the relationship to the object.
Each packet is associated with one container. In a preferred embodiment, containers are limited to an erase block so that at or near the beginning of each erase block a container packet can be found. This helps limit data loss to an erase block with a corrupted packet header. In this embodiment, if the object index is unavailable and a packet header within the erase block is corrupted, the contents from the corrupted packet header to the end of the erase block may be lost because there is possibly no reliable mechanism to determine the location of subsequent packets. In another embodiment, a more reliable approach is to have a container limited to a page boundary. This embodiment requires more header overhead. In another embodiment, containers can flow across page and erase block boundaries. This requires less header overhead but a larger portion of data may be lost if a packet header is corrupted. For these several embodiments it is expected that some type of RAID is used to further ensure data integrity.
In one embodiment, the apparatus 200 includes an object index reconstruction module 272 that reconstructs the entries in the object index using information from packet headers stored in the data storage device 154. In one embodiment, the object index reconstruction module 272 reconstructs the entries of the object index by reading headers to determine the object to which each packet belongs and sequence information to determine where in the object the data or metadata belongs. The object index reconstruction module 272 uses physical address information for each packet and timestamp or sequence information to create a mapping between the physical locations of the packets and the object identifier and data segment sequence. Timestamp or sequence information is used by the object index reconstruction module 272 to replay the sequence of changes made to the index and thereby typically reestablish the most recent state.
In another embodiment, the object index reconstruction module 272 locates packets using packet header information along with container packet information to identify physical locations of the packets, object identifier, and sequence number of each packet to reconstruct entries in the object index. In one embodiment, erase blocks are time stamped or given a sequence number as packets are written and the timestamp or sequence information of an erase block is used along with information gathered from container headers and packet headers to reconstruct the object index. In another embodiment, timestamp or sequence information is written to an erase block when the erase block is recovered.
Where the object index is stored in volatile memory, an error, loss of power, or other problem causing the storage controller 152 to shut down without saving the object index could be a problem if the object index cannot be reconstructed. The object index reconstruction module 272 allows the object index to be stored in volatile memory allowing the advantages of volatile memory, such as fast access. The object index reconstruction module 272 allows quick reconstruction of the object index autonomously without dependence on a device external to the storage device 150.
In one embodiment, the object index in volatile memory is stored periodically in a data storage device 154. In a particular example, the object index, or “index metadata,” is stored periodically in a solid-state storage 110. In another embodiment, the index metadata is stored in a solid-state storage 110n separate from solid-state storage 110a-110n-1 storing packets. The index metadata is managed independently from data and object metadata transmitted from a requesting device 155 and managed by the storage controller 152/solid-state storage device controller 202. Managing and storing index metadata separate from other data and metadata from an object allows efficient data flow without the storage controller 152/solid-state storage device controller 202 unnecessarily processing object metadata.
In one embodiment, where an object request received by the object request receiver module 260 includes a write request, the storage controller 152 receives one or more data segments of an object from memory of a requesting device 155 as a local or remote direct memory access (“DMA,” “RDMA”) operation. In a preferred example, the storage controller 152 pulls data from the memory of the requesting device 155 in one or more DMA or RDMA operations. In another example, the requesting device 155 pushes the data segment(s) to the storage controller 152 in one or more DMA or RDMA operations. In another embodiment, where the object request includes a read request, the storage controller 152 transmits one or more data segments of an object to the memory of the requesting device 155 in one or more DMA or RDMA operations. In a preferred example, the storage controller 152 pushes data to the memory of the requesting device 155 in one or more DMA or RDMA operations. In another example, the requesting device 155 pulls data from the storage controller 152 in one or more DMA or RDMA operations. In another example, the storage controller 152 pulls object command request sets from the memory of the requesting device 155 in one or more DMA or RDMA operations. In another example, the requesting device 155 pushes object command request sets to the storage controller 152 in one or more DMA or RDMA operations.
In one embodiment, the storage controller 152 emulates block storage and an object communicated between the requesting device 155 and the storage controller 152 comprises one or more data blocks. In one embodiment, the requesting device 155 includes a driver so that the storage device 150 appears as a block storage device. For example, the requesting device 155 may send a block of data of a certain size along with a physical address of where the requesting device 155 wants the data block stored. The storage controller 152 receives the data block and uses the physical block address transmitted with the data block or a transformation of the physical block address as an object identifier. The storage controller 152 then stores the data block as an object or data segment of an object by packetizing the data block and storing the data block at will. The object index module 266 then creates an entry in the object index using the physical block-based object identifier and the actual physical location where the storage controller 152 stored the data packets comprising the data from the data block.
In another embodiment, the storage controller 152 emulates block storage by accepting block objects. A block object may include one or more data blocks in a block structure. In one embodiment, the storage controller 152 treats the block object as any other object. In another embodiment, an object may represent an entire block device, partition of a block device, or some other logical or physical sub-element of a block device including a track, sector, channel, and the like. Of particular note is the ability to remap a block device RAID group to an object supporting a different RAID construction such as progressive RAID. One skilled in the art will recognize other mappings of traditional or future block devices to objects.
Solid-State Storage Device
In one embodiment, at least one solid-state controller 104 is field-programmable gate array (“FPGA”) and controller functions are programmed into the FPGA. In a particular embodiment, the FPGA is a Xilinx® FPGA. In another embodiment, the solid-state storage controller 104 comprises components specifically designed as a solid-state storage controller 104, such as an application-specific integrated circuit (“ASIC”) or custom logic solution. Each solid-state storage controller 104 typically includes a write data pipeline 106 and a read data pipeline 108, which are describe further in relation to
Solid-State Storage
The solid state storage 110 is an array of non-volatile solid-state storage elements 216, 218, 220, arranged in banks 214, and accessed in parallel through a bi-directional storage input/output (“I/O”) bus 210. The storage I/O bus 210, in one embodiment, is capable of unidirectional communication at any one time. For example, when data is being written to the solid-state storage 110, data cannot be read from the solid-state storage 110. In another embodiment, data can flow both directions simultaneously. However bi-directional, as used herein with respect to a data bus, refers to a data pathway that can have data flowing in only one direction at a time, but when data flowing one direction on the bi-directional data bus is stopped, data can flow in the opposite direction on the bi-directional data bus.
A solid-state storage element (e.g. SSS 0.0 216a) is typically configured as a chip (a package of one or more dies) or a die on a circuit board. As depicted, a solid-state storage element (e.g. 216a) operates independently or semi-independently of other solid-state storage elements (e.g. 218a) even if these several elements are packaged together in a chip package, a stack of chip packages, or some other package element. As depicted, a column of solid-state storage elements 216, 218, 220 is designated as a bank 214. As depicted, there may be “n” banks 214a-n and “m” solid-state storage elements 216a-m, 218a-m, 220a-m per bank in an array of n×m solid-state storage elements 216, 218, 220 in a solid-state storage 110. In one embodiment, a solid-state storage 110a includes twenty solid-state storage elements 216, 218, 220 per bank 214 with eight banks 214 and a solid-state storage 110n includes 2 solid-state storage elements 216, 218 per bank 214 with one bank 214. In one embodiment, each solid-state storage element 216, 218, 220 is comprised of a single-level cell (“SLC”) devices. In another embodiment, each solid-state storage element 216, 218, 220 is comprised of multi-level cell (“MLC”) devices.
In one embodiment, solid-state storage elements for multiple banks that share a common storage I/O bus 210a row (e.g. 216b, 218b, 220b) are packaged together. In one embodiment, a solid-state storage element 216, 218, 220 may have one or more dies per chip with one or more chips stacked vertically and each die may be accessed independently. In another embodiment, a solid-state storage element (e.g. SSS 0.0 216a) may have one or more virtual dies per die and one or more dies per chip and one or more chips stacked vertically and each virtual die may be accessed independently. In another embodiment, a solid-state storage element SSS 0.0 216a may have one or more virtual dies per die and one or more dies per chip with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.
In one embodiment, two dies are stacked vertically with four stacks per group to form eight storage elements (e.g. SSS 0.0-SSS 0.8) 216a-220a, each in a separate bank 214a-n. In another embodiment, 20 storage elements (e.g. SSS 0.0-SSS 20.0) 216 form a virtual bank 214a so that each of the eight virtual banks has 20 storage elements (e.g. SSS0.0-SSS 20.8) 216, 218, 220. Data is sent to the solid-state storage 110 over the storage I/O bus 210 to all storage elements of a particular group of storage elements (SSS 0.0-SSS 0.8) 216a, 218a, 220a. The storage control bus 212a is used to select a particular bank (e.g. Bank-0 214a) so that the data received over the storage I/O bus 210 connected to all banks 214 is written just to the selected bank 214a.
In a preferred embodiment, the storage I/O bus 210 is comprised of one or more independent I/O buses (“HOB a-m” comprising 210a.a-m, 210n.a-m) wherein the solid-state storage elements within each row share one of the independent I/O buses accesses each solid-state storage element 216, 218, 220 in parallel so that all banks 214 are accessed simultaneously. For example, one channel of the storage I/O bus 210 may access a first solid-state storage element 216a, 218a, 220a of each bank 214a-n simultaneously. A second channel of the storage I/O bus 210 may access a second solid-state storage element 216b, 218b, 220b of each bank 214a-n simultaneously. Each row of solid-state storage element 216, 218, 220 is accessed simultaneously. In one embodiment, where solid-state storage elements 216, 218, 220 are multi-level (physically stacked), all physical levels of the solid-state storage elements 216, 218, 220 are accessed simultaneously. As used herein, “simultaneously” also includes near simultaneous access where devices are accessed at slightly different intervals to avoid switching noise. Simultaneously is used in this context to be distinguished from a sequential or serial access wherein commands and/or data are sent individually one after the other.
Typically, banks 214a-n are independently selected using the storage control bus 212. In one embodiment, a bank 214 is selected using a chip enable or chip select. Where both chip select and chip enable are available, the storage control bus 212 may select one level of a multi-level solid-state storage element 216, 218, 220. In other embodiments, other commands are used by the storage control bus 212 to individually select one level of a multi-level solid-state storage element 216, 218, 220. Solid-state storage elements 216, 218, 220 may also be selected through a combination of control and of address information transmitted on storage I/O bus 210 and the storage control bus 212.
In one embodiment, each solid-state storage element 216, 218, 220 is partitioned into erase blocks and each erase block is partitioned into pages. A typical page is 2000 bytes (“2 kB”). In one example, a solid-state storage element (e.g. SSS0.0) includes two registers and can program two pages so that a two-register solid-state storage element 216, 218, 220 has a capacity of 4 kB. A bank 214 of 20 solid-state storage elements 216, 218, 220 would then have an 80 kB capacity of pages accessed with the same address going out the channels of the storage I/O bus 210.
This group of pages in a bank 214 of solid-state storage elements 216, 218, 220 of 80 kB may be called a virtual page. Similarly, an erase block of each storage element 216a-m of a bank 214a may be grouped to form a virtual erase block. In a preferred embodiment, an erase block of pages within a solid-state storage element 216, 218, 220 is erased when an erase command is received within a solid-state storage element 216, 218, 220. Whereas the size and number of erase blocks, pages, planes, or other logical and physical divisions within a solid-state storage element 216, 218, 220 are expected to change over time with advancements in technology, it is to be expected that many embodiments consistent with new configurations are possible and are consistent with the general description herein.
Typically, when a packet is written to a particular location within a solid-state storage element 216, 218, 220, wherein the packet is intended to be written to a location within a particular page which is specific to a particular erase block of a particular element of a particular bank, a physical address is sent on the storage I/O bus 210 and followed by the packet. The physical address contains enough information for the solid-state storage element 216, 218, 220 to direct the packet to the designated location within the page. Since all storage elements in a row of storage elements (e.g. SSS 0.0-SSS 0.N 216a, 218a, 220a) are accessed simultaneously by the appropriate bus within the storage I/O bus 210a.a, to reach the proper page and to avoid writing the data packet to similarly addressed pages in the row of storage elements (SSS 0.0-SSS0.N 216a, 218a, 220a), the bank 214a that includes the solid-state storage element SSS 0.0 216a with the correct page where the data packet is to be written is simultaneously selected by the storage control bus 212.
Similarly, a read command traveling on the storage I/O bus 210 requires a simultaneous command on the storage control bus 212 to select a single bank 214a and the appropriate page within that bank 214a. In a preferred embodiment, a read command reads an entire page, and because there are multiple solid-state storage elements 216, 218, 220 in parallel in a bank 214, an entire virtual page is read with a read command. However, the read command may be broken into subcommands, as will be explained below with respect to bank interleave. A virtual page may also be accessed in a write operation.
An erase block erase command may be sent out to erase an erase block over the storage I/O bus 210 with a particular erase block address to erase a particular erase block. Typically, an erase block erase command may be sent over the parallel paths of the storage I/O bus 210 to erase a virtual erase block, each with a particular erase block address to erase a particular erase block. Simultaneously a particular bank (e.g. bank-0 214a) is selected over the storage control bus 212 to prevent erasure of similarly addressed erase blocks in all of the banks (banks 1-N 214b-n). Other commands may also be sent to a particular location using a combination of the storage I/O bus 210 and the storage control bus 212. One of skill in the art will recognize other ways to select a particular storage location using the bi-directional storage I/O bus 210 and the storage control bus 212.
In one embodiment, packets are written sequentially to the solid-state storage 110 at an append point that is advanced through banks 214. For example, packets are streamed to the storage write buffers of a bank 214a of storage elements 216 and when the buffers are full, the packets are programmed to a designated virtual page. Packets then refill the storage write buffers and, when full, the packets are written to the next virtual page. The next virtual page may be in the same bank 214a or another bank (e.g. 214b). This process continues, virtual page after virtual page, typically until a virtual erase block is filled. In another embodiment, the streaming may continue across virtual erase block boundaries with the process continuing, virtual erase block after virtual erase block.
In a read, modify, write operation, data packets associated with the object are located and read in a read operation. Data segments of the modified object that have been modified are not written to the location from which they are read. Instead, the modified data segments are again converted to data packets and then written to the next available location in the virtual page currently being written. The object index entries for the respective data packets are modified to point to the packets that contain the modified data segments. The entry or entries in the object index for data packets associated with the same object that have not been modified will include pointers to original location of the unmodified data packets. Thus, if the original object is maintained, for example to maintain a previous version of the object, the original object will have pointers in the object index to all data packets as originally written. The new object will have pointers in the object index to some of the original data packets and pointers to the modified data packets in the virtual page that is currently being written.
In a copy operation, the object index includes an entry for the original object mapped to a number of packets stored in the solid-state storage 110. When a copy is made, a new object is created and a new entry is created in the object index mapping the new object to the original packets. The new object is also written to the solid-state storage 110 with its location mapped to the new entry in the object index. The new object packets may be used to identify the packets within the original object that are referenced in case changes have been made in the original object that have not been propagated to the copy and the object index is lost or corrupted.
Beneficially, sequentially writing packets facilitates a more even use of the solid-state storage 110 and allows the solid-state storage device controller 202 to monitor storage hot spots and level usage of the various virtual pages in the solid-state storage 110. Sequentially writing packets also facilitates a powerful, efficient garbage collection system, which is described in detail below. One of skill in the art will recognize other benefits of sequential storage of data packets.
Solid-State Storage Device Controller
In various embodiments, the solid-state storage device controller 202 also includes a data bus 204, a local bus 206, a buffer controller 208, buffers 0-N 222a-n, a master controller 224, a direct memory access (“DMA”) controller 226, a memory controller 228, a dynamic memory array 230, a static random memory array 232, a management controller 234, a management bus 236, a bridge 238 to a system bus 240, and miscellaneous logic 242, which are described below. In other embodiments, the system bus 240 is coupled to one or more network interface cards (“NICs”) 244, some of which may include remote DMA (“RDMA”) controllers 246, one or more central processing units (“CPUs”) 248, one or more external memory controllers 250 and associated external memory arrays 252, one or more storage controllers 254, peer controllers 256, and application specific processors 258, which are described below. The components 244-258 connected to the system bus 240 may be located in the computer 112 or may be other devices.
Typically the solid-state storage controller(s) 104 communicate data to the solid-state storage 110 over a storage I/O bus 210. In a typical embodiment where the solid-state storage is arranged in banks 214 and each bank 214 includes multiple storage elements 216, 218, 220 accessed in parallel, the storage I/O bus 210 is an array of busses, one for each row of storage elements 216, 218, 220 spanning the banks 214. As used herein, the term “storage I/O bus” may refer to one storage I/O bus 210 or an array of data independent busses 204. In a preferred embodiment, each storage I/O bus 210 accessing a row of storage elements (e.g. 216a, 218a, 220a) may include a logical-to-physical mapping for storage divisions (e.g. erase blocks) accessed in a row of storage elements 216a, 218a, 220a. This mapping allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem. Remapping is explained further in relation to the remapping module 430 of
Data may also be communicated to the solid-state storage controller(s) 104 from a requesting device 155 through the system bus 240, bridge 238, local bus 206, buffer(s) 222, and finally over a data bus 204. The data bus 204 typically is connected to one or more buffers 222a-n controlled with a buffer controller 208. The buffer controller 208 typically controls transfer of data from the local bus 206 to the buffers 222 and through the data bus 204 to the pipeline input buffer 306 and output buffer 330. The buffer controller 208 typically controls how data arriving from a requesting device 155 can be temporarily stored in a buffer 222 and then transferred onto a data bus 204, or vice versa, to account for different clock domains, to prevent data collisions, etc. The buffer controller 208 typically works in conjunction with the master controller 224 to coordinate data flow. As data arrives, the data will arrive on the system bus 240, be transferred to the local bus 206 through a bridge 238.
Typically the data is transferred from the local bus 206 to one or more data buffers 222 as directed by the master controller 224 and the buffer controller 208. The data then flows out of the buffer(s) 222 to the data bus 204, through a solid-state controller 104, and on to the solid-state storage 110 such as NAND flash or other storage media. In a preferred embodiment, data and associated out-of-band metadata (“object metadata”) arriving with the data is communicated using one or more data channels comprising one or more solid-state storage controllers 104a-104n−1 and associated solid-state storage 110a-110n−1 while at least one channel (solid-state storage controller 104n, solid-state storage 110n) is dedicated to in-band metadata, such as index information and other metadata generated internally to the solid-state storage device 102.
The local bus 206 is typically a bidirectional bus or set of busses that allows for communication of data and commands between devices internal to the solid-state storage device controller 202 and between devices internal to the solid-state storage device 102 and devices 244-258 connected to the system bus 240. The bridge 238 facilitates communication between the local bus 206 and system bus 240. One of skill in the art will recognize other embodiments such as ring structures or switched star configurations and functions of buses 240, 206, 204, 210 and bridges 238.
The system bus 240 is typically a bus of a computer 112 or other device in which the solid-state storage device 102 is installed or connected. In one embodiment, the system bus 240 may be a PCI-e bus, a Serial Advanced Technology Attachment (“serial ATA”) bus, parallel ATA, or the like. In another embodiment, the system bus 240 is an external bus such as small computer system interface (“SCSI”), FireWire, Fiber Channel, USB, PCIe-AS, or the like. The solid-state storage device 102 may be packaged to fit internally to a device or as an externally connected device.
The solid-state storage device controller 202 includes a master controller 224 that controls higher-level functions within the solid-state storage device 102. The master controller 224, in various embodiments, controls data flow by interpreting object requests and other requests, directs creation of indexes to map object identifiers associated with data to physical locations of associated data, coordinating DMA requests, etc. Many of the functions described herein are controlled wholly or in part by the master controller 224.
In one embodiment, the master controller 224 uses embedded controller(s). In another embodiment, the master controller 224 uses local memory such as a dynamic memory array 230 (dynamic random access memory “DRAM”), a static memory array 232 (static random access memory “SRAM”), etc. In one embodiment, the local memory is controlled using the master controller 224. In another embodiment, the master controller 224 accesses the local memory via a memory controller 228. In another embodiment, the master controller 224 runs a Linux server and may support various common server interfaces, such as the World Wide Web, hyper-text markup language (“HTML”), etc. In another embodiment, the master controller 224 uses a nano-processor. The master controller 224 may be constructed using programmable or standard logic, or any combination of controller types listed above. One skilled in the art will recognize many embodiments for the master controller 224.
In one embodiment, where the storage controller 152/solid-state storage device controller 202 manages multiple data storage devices/solid-state storage 110a-n, the master controller 224 divides the work load among internal controllers, such as the solid-state storage controllers 104a-n. For example, the master controller 224 may divide an object to be written to the data storage devices (e.g. solid-state storage 110a-n) so that a portion of the object is stored on each of the attached data storage devices. This feature is a performance enhancement allowing quicker storage and access to an object. In one embodiment, the master controller 224 is implemented using an FPGA. In another embodiment, the firmware within the master controller 224 may be updated through the management bus 236, the system bus 240 over a network connected to a NIC 244 or other device connected to the system bus 240.
In one embodiment, the master controller 224, which manages objects, emulates block storage such that a computer 112 or other device connected to the storage device/solid-state storage device 102 views the storage device/solid-state storage device 102 as a block storage device and sends data to specific physical addresses in the storage device/solid-state storage device 102. The master controller 224 then divides up the blocks and stores the data blocks as it would objects. The master controller 224 then maps the blocks and physical address sent with the block to the actual locations determined by the master controller 224. The mapping is stored in the object index. Typically, for block emulation, a block device application program interface (“API”) is provided in a driver in the computer 112, client 114, or other device wishing to use the storage device/solid-state storage device 102 as a block storage device.
In another embodiment, the master controller 224 coordinates with NIC controllers 244 and embedded RDMA controllers 246 to deliver just-in-time RDMA transfers of data and command sets. NIC controller 244 may be hidden behind a non-transparent port to enable the use of custom drivers. Also, a driver on a client 114 may have access to the computer network 116 through an I/O memory driver using a standard stack API and operating in conjunction with NICs 244.
In one embodiment, the master controller 224 is also a redundant array of independent drive (“RAID”) controller. Where the data storage device/solid-state storage device 102 is networked with one or more other data storage devices/solid-state storage devices 102, the master controller 224 may be a RAID controller for single tier RAID, multi-tier RAID, progressive RAID, etc. The master controller 224 also allows some objects to be stored in a RAID array and other objects to be stored without RAID. In another embodiment, the master controller 224 may be a distributed RAID controller element. In another embodiment, the master controller 224 may comprise many RAID, distributed RAID, and other functions as described elsewhere.
In one embodiment, the master controller 224 coordinates with single or redundant network managers (e.g. switches) to establish routing, to balance bandwidth utilization, failover, etc. In another embodiment, the master controller 224 coordinates with integrated application specific logic (via local bus 206) and associated driver software. In another embodiment, the master controller 224 coordinates with attached application specific processors 258 or logic (via the external system bus 240) and associated driver software. In another embodiment, the master controller 224 coordinates with remote application specific logic (via the computer network 116) and associated driver software. In another embodiment, the master controller 224 coordinates with the local bus 206 or external bus attached hard disk drive (“HDD”) storage controller.
In one embodiment, the master controller 224 communicates with one or more storage controllers 254 where the storage device/solid-state storage device 102 may appear as a storage device connected through a SCSI bus, Internet SCSI (“iSCSI”), fiber channel, etc. Meanwhile the storage device/solid-state storage device 102 may autonomously manage objects and may appear as an object file system or distributed object file system. The master controller 224 may also be accessed by peer controllers 256 and/or application specific processors 258.
In another embodiment, the master controller 224 coordinates with an autonomous integrated management controller to periodically validate FPGA code and/or controller software, validate FPGA code while running (reset) and/or validate controller software during power on (reset), support external reset requests, support reset requests due to watchdog timeouts, and support voltage, current, power, temperature, and other environmental measurements and setting of threshold interrupts. In another embodiment, the master controller 224 manages garbage collection to free erase blocks for reuse. In another embodiment, the master controller 224 manages wear leveling. In another embodiment, the master controller 224 allows the data storage device/solid-state storage device 102 to be partitioned into multiple virtual devices and allows partition-based media encryption. In yet another embodiment, the master controller 224 supports a solid-state storage controller 104 with advanced, multi-bit ECC correction. One of skill in the art will recognize other features and functions of a master controller 224 in a storage controller 152, or more specifically in a solid-state storage device 102.
In one embodiment, the solid-state storage device controller 202 includes a memory controller 228 which controls a dynamic random memory array 230 and/or a static random memory array 232. As stated above, the memory controller 228 may be independent or integrated with the master controller 224. The memory controller 228 typically controls volatile memory of some type, such as DRAM (dynamic random memory array 230) and SRAM (static random memory array 232). In other examples, the memory controller 228 also controls other memory types such as electrically erasable programmable read only memory (“EEPROM”), etc. In other embodiments, the memory controller 228 controls two or more memory types and the memory controller 228 may include more than one controller. Typically, the memory controller 228 controls as much SRAM 232 as is feasible and by DRAM 230 to supplement the SRAM 232.
In one embodiment, the object index is stored in memory 230, 232 and then periodically off-loaded to a channel of the solid-state storage 110n or other non-volatile memory. One of skill in the art will recognize other uses and configurations of the memory controller 228, dynamic memory array 230, and static memory array 232.
In one embodiment, the solid-state storage device controller 202 includes a DMA controller 226 that controls DMA operations between the storage device/solid-state storage device 102 and one or more external memory controllers 250 and associated external memory arrays 252 and CPUs 248. Note that the external memory controllers 250 and external memory arrays 252 are called external because they are external to the storage device/solid-state storage device 102. In addition the DMA controller 226 may also control RDMA operations with requesting devices through a NIC 244 and associated RDMA controller 246. DMA and RDMA are explained in more detail below.
In one embodiment, the solid-state storage device controller 202 includes a management controller 234 connected to a management bus 236. Typically the management controller 234 manages environmental metrics and status of the storage device/solid-state storage device 102. The management controller 234 may monitor device temperature, fan speed, power supply settings, etc. over the management bus 236. The management controller 234 may support the reading and programming of erasable programmable read only memory (“EEPROM”) for storage of FPGA code and controller software. Typically the management bus 236 is connected to the various components within the storage device/solid-state storage device 102. The management controller 234 may communicate alerts, interrupts, etc. over the local bus 206 or may include a separate connection to a system bus 240 or other bus. In one embodiment the management bus 236 is an Inter-Integrated Circuit (“I2C”) bus. One of skill in the art will recognize other related functions and uses of a management controller 234 connected to components of the storage device/solid-state storage device 102 by a management bus 236.
In one embodiment, the solid-state storage device controller 202 includes miscellaneous logic 242 that may be customized for a specific application. Typically where the solid-state device controller 202 or master controller 224 is/are configured using a FPGA or other configurable controller, custom logic may be included based on a particular application, customer requirement, storage requirement, etc.
Data Pipeline
Write Data Pipeline
The write data pipeline 106 includes a packetizer 302 that receives a data or metadata segment to be written to the solid-state storage, either directly or indirectly through another write data pipeline 106 stage, and creates one or more packets sized for the solid-state storage 110. The data or metadata segment is typically part of an object, but may also include an entire object. In another embodiment, the data segment is part of a block of data, but may also include an entire block of data. Typically, an object is received from a computer 112, client 114, or other computer or device and is transmitted to the solid-state storage device 102 in data segments streamed to the solid-state storage device 102 or computer 112. A data segment may also be known by another name, such as data parcel, but as referenced herein includes all or a portion of an object or data block.
Each object is stored as one or more packets. Each object may have one or more container packets. Each packet contains a header. The header may include a header type field. Type fields may include data, object attribute, metadata, data segment delimiters (multi-packet), object structures, object linkages, and the like. The header may also include information regarding the size of the packet, such as the number of bytes of data included in the packet. The length of the packet may be established by the packet type. The header may include information that establishes the relationship of the packet to the object. An example might be the use of an offset in a data packet header to identify the location of the data segment within the object. One of skill in the art will recognize other information that may be included in a header added to data by a packetizer 302 and other information that may be added to a data packet.
Each packet includes a header and possibly data from the data or metadata segment. The header of each packet includes pertinent information to relate the packet to the object to which the packet belongs. For example, the header may include an object identifier and offset that indicates the data segment, object, or data block from which the data packet was formed. The header may also include a logical address used by the storage bus controller 348 to store the packet. The header may also include information regarding the size of the packet, such as the number of bytes included in the packet. The header may also include a sequence number that identifies where the data segment belongs with respect to other packets within the object when reconstructing the data segment or object. The header may include a header type field. Type fields may include data, object attributes, metadata, data segment delimiters (multi-packet), object structures, object linkages, and the like. One of skill in the art will recognize other information that may be included in a header added to data or metadata by a packetizer 302 and other information that may be added to a packet.
The write data pipeline 106 includes an ECC generator 304 that generates one or more error-correcting codes (“ECC”) for the one or more packets received from the packetizer 302. The ECC generator 304 typically uses an error correcting algorithm to generate ECC which is stored with the packet. The ECC stored with the packet is typically used to detect and correct errors introduced into the data through transmission and storage. In one embodiment, packets are streamed into the ECC generator 304 as un-encoded blocks of length N. A syndrome of length S is calculated, appended and output as an encoded block of length N+S. The value of N and S are dependent upon the characteristics of the algorithm which is selected to achieve specific performance, efficiency, and robustness metrics. In the preferred embodiment, there is no fixed relationship between the ECC blocks and the packets; the packet may comprise more than one ECC block; the ECC block may comprise more than one packet; and a first packet may end anywhere within the ECC block and a second packet may begin after the end of the first packet within the same ECC block. In the preferred embodiment, ECC algorithms are not dynamically modified. In a preferred embodiment, the ECC stored with the data packets is robust enough to correct errors in more than two bits.
Beneficially, using a robust ECC algorithm allowing more than single bit correction or even double bit correction allows the life of the solid-state storage 110 to be extended. For example, if flash memory is used as the storage medium in the solid-state storage 110, the flash memory may be written approximately 100,000 times without error per erase cycle. This usage limit may be extended using a robust ECC algorithm. Having the ECC generator 304 and corresponding ECC correction module 322 onboard the solid-state storage device 102, the solid-state storage device 102 can internally correct errors and has a longer useful life than if a less robust ECC algorithm is used, such as single bit correction. However, in other embodiments the ECC generator 304 may use a less robust algorithm and may correct single-bit or double-bit errors. In another embodiment, the solid-state storage device 110 may comprise less reliable storage such as multi-level cell (“MLC”) flash in order to increase capacity, which storage may not be sufficiently reliable without more robust ECC algorithms.
In one embodiment, the write pipeline 106 includes an input buffer 306 that receives a data segment to be written to the solid-state storage 110 and stores the incoming data segments until the next stage of the write data pipeline 106, such as the packetizer 302 (or other stage for a more complex write data pipeline 106) is ready to process the next data segment. The input buffer 306 typically allows for discrepancies between the rate data segments are received and processed by the write data pipeline 106 using an appropriately sized data buffer. The input buffer 306 also allows the data bus 204 to transfer data to the write data pipeline 106 at rates greater than can be sustained by the write data pipeline 106 in order to improve efficiency of operation of the data bus 204. Typically when the write data pipeline 106 does not include an input buffer 306, a buffering function is performed elsewhere, such as in the solid-state storage device 102 but outside the write data pipeline 106, in the computer 112, such as within a network interface card (“NIC”), or at another device, for example when using remote direct memory access (“RDMA”).
In another embodiment, the write data pipeline 106 also includes a write synchronization buffer 308 that buffers packets received from the ECC generator 304 prior to writing the packets to the solid-state storage 110. The write synch buffer 308 is located at a boundary between a local clock domain and a solid-state storage clock domain and provides buffering to account for the clock domain differences. In other embodiments, synchronous solid-state storage 110 may be used and synchronization buffers 308, 328 may be eliminated.
In one embodiment, the write data pipeline 106 also includes a media encryption module 318 that receives the one or more packets from the packetizer 302, either directly or indirectly, and encrypts the one or more packets using an encryption key unique to the solid-state storage device 102 prior to sending the packets to the ECC generator 304. Typically, the entire packet is encrypted, including the headers. In another embodiment, headers are not encrypted. In this document, encryption key is understood to mean a secret encryption key that is managed externally from an embodiment that integrates the solid-state storage 110 and where the embodiment requires encryption protection. The media encryption module 318 and corresponding media decryption module 332 provide a level of security for data stored in the solid-state storage 110. For example, where data is encrypted with the media encryption module 318, if the solid-state storage 110 is connected to a different solid-state storage controller 104, solid-state storage device 102, or computer 112, the contents of the solid-state storage 110 typically could not be read without use of the same encryption key used during the write of the data to the solid-state storage 110 without significant effort.
In a typical embodiment, the solid-state storage device 102 does not store the encryption key in non-volatile storage and allows no external access to the encryption key. The encryption key is provided to the solid-state storage controller 104 during initialization. The solid-state storage device 102 may use and store a non-secret cryptographic nonce that is used in conjunction with an encryption key. A different nonce may be stored with every packet. Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm. The encryption key may be received from a client 114, a computer 112, key manager, or other device that manages the encryption key to be used by the solid-state storage controller 104. In another embodiment, the solid-state storage 110 may have two or more partitions and the solid-state storage controller 104 behaves as though it were two or more solid-state storage controllers 104, each operating on a single partition within the solid-state storage 110. In this embodiment, a unique media encryption key may be used with each partition.
In another embodiment, the write data pipeline 106 also includes an encryption module 314 that encrypts a data or metadata segment received from the input buffer 306, either directly or indirectly, prior sending the data segment to the packetizer 302, the data segment is encrypted using an encryption key received in conjunction with the data segment. The encryption module 314 differs from the media encryption module 318 in that the encryption keys used by the encryption module 314 to encrypt data may not be common to all data stored within the solid-state storage device 102 but may vary on an object basis and received in conjunction with receiving data segments as described below. For example, an encryption key for a data segment to be encrypted by the encryption module 314 may be received with the data segment or may be received as part of a command to write an object to which the data segment belongs. The solid-state storage device 102 may use and store a non-secret cryptographic nonce in each object packet that is used in conjunction with the encryption key. A different nonce may be stored with every packet. Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm. In one embodiment, the nonce used by the media encryption module 318 is the same as that used by the encryption module 314.
The encryption key may be received from a client 114, a computer 112, key manager, or other device that holds the encryption key to be used to encrypt the data segment. In one embodiment, encryption keys are transferred to the solid-state storage controller 104 from one of a solid-state storage device 102, computer 112, client 114, or other external agent which has the ability to execute industry standard methods to securely transfer and protect private and public keys.
In one embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and encrypts a second packet with a second encryption key received in conjunction with the second packet. In another embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and passes a second data packet on to the next stage without encryption. Beneficially, the encryption module 314 included in the write data pipeline 106 of the solid-state storage device 102 allows object-by-object or segment-by-segment data encryption without a single file system or other external system to keep track of the different encryption keys used to store corresponding objects or data segments. Each requesting device 155 or related key manager independently manages encryption keys used to encrypt only the objects or data segments sent by the requesting device 155.
In another embodiment, the write data pipeline 106 includes a compression module 312 that compresses the data or metadata segment prior to sending the data segment to the packetizer 302. The compression module 312 typically compresses a data or metadata segment using a compression routine known to those of skill in the art to reduce the storage size of the segment. For example, if a data segment includes a string of 512 zeros, the compression module 312 may replace the 512 zeros with code or token indicating the 512 zeros where the code is much more compact than the space taken by the 512 zeros.
In one embodiment, the compression module 312 compresses a first segment with a first compression routine and passes along a second segment without compression. In another embodiment, the compression module 312 compresses a first segment with a first compression routine and compresses the second segment with a second compression routine. Having this flexibility within the solid-state storage device 102 is beneficial so that clients 114 or other devices writing data to the solid-state storage device 102 may each specify a compression routine or so that one can specify a compression routine while another specifies no compression. Selection of compression routines may also be selected according to default settings on a per object type or object class basis. For example, a first object of a specific object class and type may be able to override default compression routine settings and a second object of the same object class and object type may use the default compression routine and a third object of the same object class and object type may use no compression.
In one embodiment, the write data pipeline 106 includes a garbage collector bypass 316 that receives data segments from the read data pipeline 108 as part of a data bypass in a garbage collection system. A garbage collection system typically marks packets that are no longer valid, typically because the packet is marked for deletion or has been modified and the modified data is stored in a different location. At some point, the garbage collection system determines that a particular section of storage may be recovered. This determination may be due to a lack of available storage capacity, the percentage of data marked as invalid reaching a threshold, a consolidation of valid data, an error detection rate for that section of storage reaching a threshold, or improving performance based on data distribution, etc. Numerous factors may be considered by a garbage collection algorithm to determine when a section of storage is to be recovered.
Once a section of storage has been marked for recovery, valid packets in the section typically must be relocated. The garbage collector bypass 316 allows packets to be read into the read data pipeline 108 and then transferred directly to the write data pipeline 106 without being routed out of the solid-state storage controller 104. In a preferred embodiment, the garbage collector bypass 316 is part of an autonomous garbage collector system that operates within the solid-state storage device 102. This allows the solid-state storage device 102 to manage data so that data is systematically spread throughout the solid-state storage 110 to improve performance, data reliability and to avoid overuse and underuse of any one location or area of the solid-state storage 110 and to lengthen the useful life of the solid-state storage 110.
The garbage collector bypass 316 coordinates insertion of segments into the write data pipeline 106 with other segments being written by clients 114 or other devices. In the depicted embodiment, the garbage collector bypass 316 is before the packetizer 302 in the write data pipeline 106 and after the depacketizer 324 in the read data pipeline 108, but may also be located elsewhere in the read and write data pipelines 106, 108. The garbage collector bypass 316 may be used during a flush of the write pipeline 106 to fill the remainder of the virtual page in order to improve the efficiency of storage within the solid-state storage 110 and thereby reduce the frequency of garbage collection.
In one embodiment, the write data pipeline 106 includes a write buffer 320 that buffers data for efficient write operations. Typically, the write buffer 320 includes enough capacity for packets to fill at least one virtual page in the solid-state storage 110. This allows a write operation to send an entire page of data to the solid-state storage 110 without interruption. By sizing the write buffer 320 of the write data pipeline 106 and buffers within the read data pipeline 108 to be the same capacity or larger than a storage write buffer within the solid-state storage 110, writing and reading data is more efficient since a single write command may be crafted to send a full virtual page of data to the solid-state storage 110 instead of multiple commands.
While the write buffer 320 is being filled, the solid-state storage 110 may be used for other read operations. This is advantageous because other solid-state devices with a smaller write buffer or no write buffer may tie up the solid-state storage when data is written to a storage write buffer and data flowing into the storage write buffer stalls. Read operations will be blocked until the entire storage write buffer is filled and programmed. Another approach for systems without a write buffer or a small write buffer is to flush the storage write buffer that is not full in order to enable reads. Again this is inefficient because multiple write/program cycles are required to fill a page.
For the depicted embodiment with a write buffer 320 sized larger than a virtual page, a single write command, which includes numerous subcommands, can then be followed by a single program command to transfer the page of data from the storage write buffer in each solid-state storage element 216, 218, 220 to the designated page within each solid-state storage element 216, 218, 220. This technique has the benefits of eliminating partial page programming, which is known to reduce data reliability and durability and freeing up the destination bank for reads and other commands while the buffer fills.
In one embodiment, the write buffer 320 is a ping-pong buffer where one side of the buffer is filled and then designated for transfer at an appropriate time while the other side of the ping-pong buffer is being filled. In another embodiment, the write buffer 320 includes a first-in first-out (“FIFO”) register with a capacity of more than a virtual page of data segments. One of skill in the art will recognize other write buffer 320 configurations that allow a virtual page of data to be stored prior to writing the data to the solid-state storage 110.
In another embodiment, the write buffer 320 is sized smaller than a virtual page so that less than a page of information could be written to a storage write buffer in the solid-state storage 110. In the embodiment, to prevent a stall in the write data pipeline 106 from holding up read operations, data is queued using the garbage collection system that needs to be moved from one location to another as part of the garbage collection process. In case of a data stall in the write data pipeline 106, the data can be fed through the garbage collector bypass 316 to the write buffer 320 and then on to the storage write buffer in the solid-state storage 110 to fill the pages of a virtual page prior to programming the data. In this way a data stall in the write data pipeline 106 would not stall reading from the solid-state storage device 102.
In another embodiment, the write data pipeline 106 includes a write program module 310 with one or more user-definable functions within the write data pipeline 106. The write program module 310 allows a user to customize the write data pipeline 106. A user may customize the write data pipeline 106 based on a particular data requirement or application. Where the solid-state storage controller 104 is an FPGA, the user may program the write data pipeline 106 with custom commands and functions relatively easily. A user may also use the write program module 310 to include custom functions with an ASIC, however, customizing an ASIC may be more difficult than with an FPGA. The write program module 310 may include buffers and bypass mechanisms to allow a first data segment to execute in the write program module 310 while a second data segment may continue through the write data pipeline 106. In another embodiment, the write program module 310 may include a processor core that can be programmed through software.
Note that the write program module 310 is shown between the input buffer 306 and the compression module 312, however, the write program module 310 could be anywhere in the write data pipeline 106 and may be distributed among the various stages 302-320. In addition, there may be multiple write program modules 310 distributed among the various states 302-320 that are programmed and operate independently. In addition, the order of the stages 302-320 may be altered. One of skill in the art will recognize workable alterations to the order of the stages 302-320 based on particular user requirements.
Read Data Pipeline
The read data pipeline 108 includes an ECC correction module 322 that determines if a data error exists in the ECC blocks of a requested packet received from the solid-state storage 110 by using the ECC stored with each ECC block of the requested packet. The ECC correction module 322 then corrects any errors in the requested packet if any error exists and the errors are correctable using the ECC. For example, if the ECC can detect an error in six bits but can only correct three bit errors, the ECC correction module 322 corrects ECC blocks of the requested packet with up to three bits in error. The ECC correction module 322 corrects the bits in error by changing the bits in error to the correct one or zero state so that the requested data packet is identical to when it was written to the solid-state storage 110 and the ECC was generated for the packet.
If the ECC correction module 322 determines that the requested packets contains more bits in error than the ECC can correct, the ECC correction module 322 cannot correct the errors in the corrupted ECC blocks of the requested packet and sends an interrupt. In one embodiment, the ECC correction module 322 sends an interrupt with a message indicating that the requested packet is in error. The message may include information that the ECC correction module 322 cannot correct the errors or the inability of the ECC correction module 322 to correct the errors may be implied. In another embodiment, the ECC correction module 322 sends the corrupted ECC blocks of the requested packet with the interrupt and/or the message.
In the preferred embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet that cannot be corrected by the ECC correction module 322 is read by the master controller 224, corrected, and returned to the ECC correction module 322 for further processing by the read data pipeline 108. In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet is sent to the device requesting the data. The requesting device 155 may correct the ECC block or replace the data using another copy, such as a backup or mirror copy, and then may use the replacement data of the requested data packet or return it to the read data pipeline 108. The requesting device 155 may use header information in the requested packet in error to identify data required to replace the corrupted requested packet or to replace the object to which the packet belongs. In another preferred embodiment, the solid-state storage controller 104 stores data using some type of RAID and is able to recover the corrupted data. In another embodiment, the ECC correction module 322 sends an interrupt and/or message and the receiving device fails the read operation associated with the requested data packet. One of skill in the art will recognize other options and actions to be taken as a result of the ECC correction module 322 determining that one or more ECC blocks of the requested packet are corrupted and that the ECC correction module 322 cannot correct the errors.
The read data pipeline 108 includes a depacketizer 324 that receives ECC blocks of the requested packet from the ECC correction module 322, directly or indirectly, and checks and removes one or more packet headers. The depacketizer 324 may validate the packet headers by checking packet identifiers, data length, data location, etc. within the headers. In one embodiment, the header includes a hash code that can be used to validate that the packet delivered to the read data pipeline 108 is the requested packet. The depacketizer 324 also removes the headers from the requested packet added by the packetizer 302. The depacketizer 324 may be directed to not operate on certain packets but pass these forward without modification. An example might be a container label that is requested during the course of a rebuild process where the header information is required by the object index reconstruction module 272. Further examples include the transfer of packets of various types destined for use within the solid-state storage device 102. In another embodiment, the depacketizer 324 operation may be packet type dependent.
The read data pipeline 108 includes an alignment module 326 that receives data from the depacketizer 324 and removes unwanted data. In one embodiment, a read command sent to the solid-state storage 110 retrieves a packet of data. A device requesting the data may not require all data within the retrieved packet and the alignment module 326 removes the unwanted data. If all data within a retrieved page is requested data, the alignment module 326 does not remove any data.
The alignment module 326 re-formats the data as data segments of an object in a form compatible with a device requesting the data segment prior to forwarding the data segment to the next stage. Typically, as data is processed by the read data pipeline 108, the size of data segments or packets changes at various stages. The alignment module 326 uses received data to format the data into data segments suitable to be sent to the requesting device 155 and joined to form a response. For example, data from a portion of a first data packet may be combined with data from a portion of a second data packet. If a data segment is larger than a data requested by the requesting device 155, the alignment module 326 may discard the unwanted data.
In one embodiment, the read data pipeline 108 includes a read synchronization buffer 328 that buffers one or more requested packets read from the solid-state storage 110 prior to processing by the read data pipeline 108. The read synchronization buffer 328 is at the boundary between the solid-state storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences.
In another embodiment, the read data pipeline 108 includes an output buffer 330 that receives requested packets from the alignment module 326 and stores the packets prior to transmission to the requesting device 155. The output buffer 330 accounts for differences between when data segments are received from stages of the read data pipeline 108 and when the data segments are transmitted to other parts of the solid-state storage controller 104 or to the requesting device 155. The output buffer 330 also allows the data bus 204 to receive data from the read data pipeline 108 at rates greater than can be sustained by the read data pipeline 108 in order to improve efficiency of operation of the data bus 204.
In one embodiment, the read data pipeline 108 includes a media decryption module 332 that receives one or more encrypted requested packets from the ECC correction module 322 and decrypts the one or more requested packets using the encryption key unique to the solid-state storage device 102 prior to sending the one or more requested packets to the depacketizer 324. Typically the encryption key used to decrypt data by the media decryption module 332 is identical to the encryption key used by the media encryption module 318. In another embodiment, the solid-state storage 110 may have two or more partitions and the solid-state storage controller 104 behaves as though it were two or more solid-state storage controllers 104 each operating on a single partition within the solid-state storage 110. In this embodiment, a unique media encryption key may be used with each partition.
In another embodiment, the read data pipeline 108 includes a decryption module 334 that decrypts a data segment formatted by the depacketizer 324 prior to sending the data segment to the output buffer 330. The data segment decrypted using an encryption key received in conjunction with the read request that initiates retrieval of the requested packet received by the read synchronization buffer 328. The decryption module 334 may decrypt a first packet with an encryption key received in conjunction with the read request for the first packet and then may decrypt a second packet with a different encryption key or may pass the second packet on to the next stage of the read data pipeline 108 without decryption. Typically, the decryption module 334 uses a different encryption key to decrypt a data segment than the media decryption module 332 uses to decrypt requested packets. When the packet was stored with a non-secret cryptographic nonce, the nonce is used in conjunction with an encryption key to decrypt the data packet. The encryption key may be received from a client 114, a computer 112, key manager, or other device that manages the encryption key to be used by the solid-state storage controller 104.
In another embodiment, the read data pipeline 108 includes a decompression module 336 that decompresses a data segment formatted by the depacketizer 324. In the preferred embodiment, the decompression module 336 uses compression information stored in one or both of the packet header and the container label to select a complementary routine to that used to compress the data by the compression module 312. In another embodiment, the decompression routine used by the decompression module 336 is dictated by the device requesting the data segment being decompressed. In another embodiment, the decompression module 336 selects a decompression routine according to default settings on a per object type or object class basis. A first packet of a first object may be able to override a default decompression routine and a second packet of a second object of the same object class and object type may use the default decompression routine and a third packet of a third object of the same object class and object type may use no decompression.
In another embodiment, the read data pipeline 108 includes a read program module 338 that includes one or more user-definable functions within the read data pipeline 108. The read program module 338 has similar characteristics to the write program module 310 and allows a user to provide custom functions to the read data pipeline 108. The read program module 338 may be located as shown in
The solid-state storage controller 104 includes control and status registers 340 and corresponding control queues 342. The control and status registers 340 and control queues 342 facilitate control and sequencing commands and subcommands associated with data processed in the write and read data pipelines 106, 108. For example, a data segment in the packetizer 302 may have one or more corresponding control commands or instructions in a control queue 342 associated with the ECC generator 304. As the data segment is packetized, some of the instructions or commands may be executed within the packetizer 302. Other commands or instructions may be passed to the next control queue 342 through the control and status registers 340 as the newly formed data packet created from the data segment is passed to the next stage.
Commands or instructions may be simultaneously loaded into the control queues 342 for a packet being forwarded to the write data pipeline 106 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage. Similarly, commands or instructions may be simultaneously loaded into the control queues 342 for a packet being requested from the read data pipeline 108 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage. One of skill in the art will recognize other features and functions of control and status registers 340 and control queues 342.
The solid-state storage controller 104 and or solid-state storage device 102 may also include a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350, which are described in relation to
Bank Interleave
The bank interleave controller 344 directs one or more commands to two or more queues in the bank interleave controller 344 and coordinates among the banks 214 of the solid-state storage 110 execution of the commands stored in the queues, such that a command of a first type executes on one bank 214a while a command of a second type executes on a second bank 214b. The one or more commands are separated by command type into the queues. Each bank 214 of the solid-state storage 110 has a corresponding set of queues within the bank interleave controller 344 and each set of queues includes a queue for each command type.
The bank interleave controller 344 coordinates among the banks 214 of the solid-state storage 110 execution of the commands stored in the queues. For example, a command of a first type executes on one bank 214a while a command of a second type executes on a second bank 214b. Typically the command types and queue types include read and write commands and queues 410, 412, but may also include other commands and queues that are storage media specific. For example, in the embodiment depicted in
For other types of solid-state storage 110, other types of commands and corresponding queues may be included without straying from the scope of the invention. The flexible nature of an FPGA solid-state storage controller 104 allows flexibility in storage media. If flash memory were changed to another solid-state storage type, the bank interleave controller 344, storage bus controller 348, and MUX 350 could be altered to accommodate the media type without significantly affecting the data pipelines 106, 108 and other solid-state storage controller 104 functions.
In the embodiment depicted in
The agents 402, 404, 406, 408, in one embodiment, direct commands of the appropriate type destined for a particular bank 214a to the correct queue for the bank 214a. For example, the read agent 402 may receive a read command for bank-1 214b and directs the read command to the bank-1 read queue 410b. The write agent 404 may receive a write command to write data to a location in bank-0 214a of the solid-state storage 110 and will then send the write command to the bank-0 write queue 412a. Similarly, the erase agent 406 may receive an erase command to erase an erase block in bank-1214b and will then pass the erase command to the bank-1 erase queue 414b. The management agent 408 typically receives management commands, status requests, and the like, such as a reset command or a request to read a configuration register of a bank 214, such as bank-0 214a. The management agent 408 sends the management command to the bank-0 management queue 416a.
The agents 402, 404, 406, 408 typically also monitor status of the queues 410, 412, 414, 416 and send status, interrupt, or other messages when the queues 410, 412, 414, 416 are full, nearly full, non-functional, etc. In one embodiment, the agents 402, 404, 406, 408 receive commands and generate corresponding sub-commands. In one embodiment, the agents 402, 404, 406, 408 receive commands through the control & status registers 340 and generate corresponding sub-commands which are forwarded to the queues 410, 412, 414, 416. One of skill in the art will recognize other functions of the agents 402, 404, 406, 408.
The queues 410, 412, 414, 416 typically receive commands and store the commands until required to be sent to the solid-state storage banks 214. In a typical embodiment, the queues 410, 412, 414, 416 are first-in, first-out (“FIFO”) registers or a similar component that operates as a FIFO. In another embodiment, the queues 410, 412, 414, 416 store commands in an order that matches data, order of importance, or other criteria.
The bank controllers 418 typically receive commands from the queues 410, 412, 414, 416 and generate appropriate subcommands. For example, the bank-0 write queue 412a may receive a command to write a page of data packets to bank-0 214a. The bank-0 controller 418a may receive the write command at an appropriate time and may generate one or more write subcommands for each data packet stored in the write buffer 320 to be written to the page in bank-0 214a. For example, bank-0 controller 418a may generate commands to validate the status of bank 0 214a and the solid-state storage array 216, select the appropriate location for writing one or more data packets, clear the input buffers within the solid-state storage memory array 216, transfer the one or more data packets to the input buffers, program the input buffers into the selected location, verify that the data was correctly programmed, and if program failures occur do one or more of interrupting the master controller 224, retrying the write to the same physical location, and retrying the write to a different physical location. Additionally, in conjunction with example write command, the storage bus controller 348 will cause the one or more commands to be multiplied to each of the storage I/O buses 210a-n with the logical address of the command mapped to a first physical addresses for storage I/O bus 210a, and mapped to a second physical address for storage I/O bus 210b, and so forth as further described below.
Typically, bus arbiter 420 selects from among the bank controllers 418 and pulls subcommands from output queues within the bank controllers 418 and forwards these to the Storage Bus Controller 348 in a sequence that optimizes the performance of the banks 214. In another embodiment, the bus arbiter 420 may respond to a high level interrupt and modify the normal selection criteria. In another embodiment, the master controller 224 can control the bus arbiter 420 through the control and status registers 340. One of skill in the art will recognize other means by which the bus arbiter 420 may control and interleave the sequence of commands from the bank controllers 418 to the solid-state storage 110.
The bus arbiter 420 typically coordinates selection of appropriate commands, and corresponding data when required for the command type, from the bank controllers 418 and sends the commands and data to the storage bus controller 348. The bus arbiter 420 typically also sends commands to the storage control bus 212 to select the appropriate bank 214. For the case of flash memory or other solid-state storage 110 with an asynchronous, bi-directional serial storage I/O bus 210, only one command (control information) or set of data can be transmitted at a time. For example, when write commands or data are being transmitted to the solid-state storage 110 on the storage I/O bus 210, read commands, data being read, erase commands, management commands, or other status commands cannot be transmitted on the storage I/O bus 210. For example, when data is being read from the storage I/O bus 210, data cannot be written to the solid-state storage 110.
For example, during a write operation on bank-0 the bus arbiter 420 selects the bank-0 controller 418a which may have a write command or a series of write sub-commands on the top of its queue which cause the storage bus controller 348 to execute the following sequence. The bus arbiter 420 forwards the write command to the storage bus controller 348, which sets up a write command by selecting bank-0 214a through the storage control bus 212, sending a command to clear the input buffers of the solid-state storage elements 110 associated with the bank-0 214a, and sending a command to validate the status of the solid-state storage elements 216, 218, 220 associated with the bank-0 214a. The storage bus controller 348 then transmits a write subcommand on the storage I/O bus 210, which contains the physical addresses including the address of the logical erase block for each individual physical erase solid-stage storage element 216a-m as mapped from the logical erase block address. The storage bus controller 348 then muxes the write buffer 320 through the write sync buffer 308 to the storage I/O bus 210 through the MUX 350 and streams write data to the appropriate page. When the page is full, then storage bus controller 348 causes the solid-state storage elements 216a-m associated with the bank-0 214a to program the input buffer to the memory cells within the solid-state storage elements 216a-m. Finally, the storage bus controller 348 validates the status to ensure that page was correctly programmed.
A read operation is similar to the write example above. During a read operation, typically the bus arbiter 420, or other component of the bank interleave controller 344, receives data and corresponding status information and sends the data to the read data pipeline 108 while sending the status information on to the control and status registers 340. Typically, a read data command forwarded from bus arbiter 420 to the storage bus controller 348 will cause the MUX 350 to gate the read data on storage I/O bus 210 to the read data pipeline 108 and send status information to the appropriate control and status registers 340 through the status MUX 422.
The bus arbiter 420 coordinates the various command types and data access modes so that only an appropriate command type or corresponding data is on the bus at any given time. If the bus arbiter 420 has selected a write command, and write subcommands and corresponding data are being written to the solid-state storage 110, the bus arbiter 420 will not allow other command types on the storage I/O bus 210. Beneficially, the bus arbiter 420 uses timing information, such as predicted command execution times, along with status information received concerning bank 214 status to coordinate execution of the various commands on the bus with the goal of minimizing or eliminating idle time of the busses.
The master controller 224 through the bus arbiter 420 typically uses expected completion times of the commands stored in the queues 410, 412, 414, 416, along with status information, so that when the subcommands associated with a command are executing on one bank 214a, other subcommands of other commands are executing on other banks 214b-n. When one command is fully executed on a bank 214a, the bus arbiter 420 directs another command to the bank 214a. The bus arbiter 420 may also coordinate commands stored in the queues 410, 412, 414, 416 with other commands that are not stored in the queues 410, 412, 414, 416.
For example, an erase command may be sent out to erase a group of erase blocks within the solid-state storage 110. An erase command may take 10 to 1000 times more time to execute than a write or a read command or 10 to 100 times more time to execute than a program command. For N banks 214, the bank interleave controller 344 may split the erase command into N commands, each to erase a virtual erase block of a bank 214a. While bank-0 214a is executing an erase command, the bus arbiter 420 may select other commands for execution on the other banks 214b-n. The bus arbiter 420 may also work with other components, such as the storage bus controller 348, the master controller 224, etc., to coordinate command execution among the buses. Coordinating execution of commands using the bus arbiter 420, bank controllers 418, queues 410, 412, 414, 416, and agents 402, 404, 406, 408 of the bank interleave controller 344 can dramatically increase performance over other solid-state storage systems without a bank interleave function.
In one embodiment, the solid-state controller 104 includes one bank interleave controller 344 that serves all of the storage elements 216, 218, 220 of the solid-state storage 110. In another embodiment, the solid-state controller 104 includes a bank interleave controller 344 for each row of storage elements 216a-m, 218a-m, 220a-m. For example, one bank interleave controller 344 serves one row of storage elements SSS 0.0-SSS 0.N 216a, 218a, 220a, a second bank interleave controller 344 serves a second row of storage elements SSS 1.0-SSS 1.N 216b, 218b, 220b, etc.
In another alternate embodiment (not shown), commands are stored in a single queue where the commands may be pulled from the queue in an order other than how they are stored so that the bank interleave controller 344 can execute a command on one bank 214a while other commands are executing on the remaining banks 214b-n. One of skill in the art will easily recognize other queue configurations and types to enable execution of a command on one bank 214a while other commands are executing on other banks 214b-n.
Storage Specific Components
The solid-state storage controller 104 includes a synchronization buffer 346 that buffers commands and status messages sent and received from the solid-state storage 110. The synchronization buffer 346 is located at the boundary between the solid-state storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences. The synchronization buffer 346, write synchronization buffer 308, and read synchronization buffer 328 may be independent or may act together to buffer data, commands, status messages, etc. In the preferred embodiment, the synchronization buffer 346 is located where there are the fewest number of signals crossing the clock domains. One skilled in the art will recognize that synchronization between clock domains may be arbitrarily moved to other locations within the solid-state storage device 102 in order to optimize some aspect of design implementation.
The solid-state storage controller 104 includes a storage bus controller 348 that interprets and translates commands for data sent to and read from the solid-state storage 110 and status messages received from the solid-state storage 110 based on the type of solid-state storage 110. For example, the storage bus controller 348 may have different timing requirements for different types of storage, storage with different performance characteristics, storage from different manufacturers, etc. The storage bus controller 348 also sends control commands to the storage control bus 212.
In the preferred embodiment, the solid-state storage controller 104 includes a MUX 350 that comprises an array of multiplexers 350a-n where each multiplexer is dedicated to a row in the solid-state storage array 110. For example, multiplexer 350a is associated with solid-state storage elements 216a, 218a, 220a. MUX 350 routes the data from the write data pipeline 106 and commands from the storage bus controller 348 to the solid-state storage 110 via the storage I/O bus 210 and routes data and status messages from the solid-state storage 110 via the storage I/O bus 210 to the read data pipeline 108 and the control and status registers 340 through the storage bus controller 348, synchronization buffer 346, and bank interleave controller 344.
In the preferred embodiment, the solid-state storage controller 104 includes a MUX 350 for each row of solid-state storage elements (e.g. SSS 0.1 216a, SSS 0.2 218a, SSS 0.N 220a). A MUX 350 combines data from the write data pipeline 106 and commands sent to the solid-state storage 110 via the storage I/O bus 210 and separates data to be processed by the read data pipeline 108 from commands. Packets stored in the write buffer 320 are directed on busses out of the write buffer 320 through a write synchronization buffer 308 for each row of solid-state storage elements (SSS x.0 to SSS x.N 216, 218, 220) to the MUX 350 for each row of solid-state storage elements (SSS x.0 to SSS x.N 216, 218, 220). The commands and read data are received by the MUXes 350 from the storage I/O bus 210. The MUXes 350 also direct status messages to the storage bus controller 348.
The storage bus controller 348 includes a mapping module 424. The mapping module 424 maps a logical address of an erase block to one or more physical addresses of an erase block. For example, a solid-state storage 110 with an array of twenty storage elements (e.g. SSS 0.0 to SSS M.0 216) per block 214a may have a logical address for a particular erase block mapped to twenty physical addresses of the erase block, one physical address per storage element. Because the storage elements are accessed in parallel, erase blocks at the same position in each storage element in a row of storage elements 216a, 218a, 220a will share a physical address. To select one erase block (e.g. in storage element SSS 0.0 216a) instead of all erase blocks in the row (e.g. in storage elements SSS 0.0, 0.1, . . . 0.N 216a, 218a, 220a), one bank (in this case bank-0 214a) is selected.
This logical-to-physical mapping for erase blocks is beneficial because if one erase block becomes damaged or inaccessible, the mapping can be changed to map to another erase block. This mitigates the loss of losing an entire virtual erase block when one element's erase block is faulty. The remapping module 430 changes a mapping of a logical address of an erase block to one or more physical addresses of a virtual erase block (spread over the array of storage elements). For example, virtual erase block 1 may be mapped to erase block 1 of storage element SSS 0.0 216a, to erase block 1 of storage element SSS 1.0 216b, . . . , and to storage element M.0 216m, virtual erase block 2 may be mapped to erase block 2 of storage element SSS 0.1 218a, to erase block 2 of storage element SSS 1.1 218b, . . . , and to storage element M.1 218m, etc.
If erase block 1 of a storage element SSS0.0 216a is damaged, experiencing errors due to wear, etc., or cannot be used for some reason, the remapping module 430 could change the logical-to-physical mapping for the logical address that pointed to erase block 1 of virtual erase block 1. If a spare erase block (call it erase block 221) of storage element SSS 0.0 216a is available and currently not mapped, the remapping module 430 could change the mapping of virtual erase block 1 to point to erase block 221 of storage element SSS 0.0 216a, while continuing to point to erase block 1 of storage element SSS 1.0 216b, erase block 1 of storage element SSS 2.0 (not shown) . . . , and to storage element M.0 216m. The mapping module 424 or remapping module 430 could map erase blocks in a prescribed order (virtual erase block 1 to erase block 1 of the storage elements, virtual erase block 2 to erase block 2 of the storage elements, etc.) or may map erase blocks of the storage elements 216, 218, 220 in another order based on some other criteria.
In one embodiment, the erase blocks could be grouped by access time. Grouping by access time, meaning time to execute a command, such as programming (writing) data into pages of specific erase blocks, can level command completion so that a command executed across the erase blocks of a virtual erase block is not limited by the slowest erase block. In other embodiments, the erase blocks may be grouped by wear level, health, etc. One of skill in the art will recognize other factors to consider when mapping or remapping erase blocks.
In one embodiment, the storage bus controller 348 includes a status capture module 426 that receives status messages from the solid-state storage 110 and sends the status messages to the status MUX 422. In another embodiment, when the solid-state storage 110 is flash memory, the storage bus controller 348 includes a NAND bus controller 428. The NAND bus controller 428 directs commands from the read and write data pipelines 106, 108 to the correct location in the solid-state storage 110, coordinates timing of command execution based on characteristics of the flash memory, etc. If the solid-state storage 110 is another solid-state storage type, the NAND bus controller 428 would be replaced by a bus controller specific to the storage type. One of skill in the art will recognize other functions of a NAND bus controller 428.
Flow Charts
Typically, a first packet includes an object identifier that identifies the object for which the packet was created. A second packet may include a header with information used by the solid-state storage device 102 to associate the second packet to the object identified in the first packet and offset information locating the second packet within the object, and data. The solid-state storage device controller 202 manages the bank 214 and physical area to which the packets are streamed.
The ECC generator 304 receives a packet from the packetizer 302 and generates 508 ECC for the data packets. Typically, there is no fixed relationship between packets and ECC blocks. An ECC block may comprise one or more packets. A packet may comprise one or more ECC blocks. A packet may start and end anywhere within an ECC block. A packet may start anywhere in a first ECC block and end anywhere in a subsequent ECC block.
The write synchronization buffer 308 buffers 510 the packets as distributed within the corresponding ECC blocks prior to writing ECC blocks to the solid-state storage 110 and then the solid-state storage controller 104 writes 512 the data at an appropriate time considering clock domain differences, and the method 500 ends 514. The write synch buffer 308 is located at the boundary between a local clock domain and a solid-state storage 110 clock domain. Note that the method 500 describes receiving one or more data segments and writing one or more data packets for convenience, but typically a stream of data segments is received and a group. Typically a number of ECC blocks comprising a complete virtual page of solid-state storage 110 are written to the solid-state storage 110. Typically the packetizer 302 receives data segments of one size and generates packets of another size. This necessarily requires data or metadata segments or parts of data or metadata segments to be combined to form data packets to capture all of the data of the segments into packets.
The ECC generator 304 receives a packet from the packetizer 302 and generates 608 one or more ECC blocks for the packets. The write synchronization buffer 308 buffers 610 the packets as distributed within the corresponding ECC blocks prior to writing ECC blocks to the solid-state storage 110 and then the solid-state storage controller 104 writes 612 the data at an appropriate time considering clock domain differences. When data is requested from the solid-state storage 110, ECC blocks comprising one or more data packets are read into the read synchronization buffer 328 and buffered 614. The ECC blocks of the packet are received over the storage I/O bus 210. Since the storage I/O bus 210 is bi-directional, when data is read, write operations, command operations, etc. are halted.
The ECC correction module 322 receives the ECC blocks of the requested packets held in the read synchronization buffer 328 and corrects 616 errors within each ECC block as necessary. If the ECC correction module 322 determines that one or more errors exist in an ECC block and the errors are correctable using the ECC syndrome, the ECC correction module 322 corrects 616 the error in the ECC block. If the ECC correction module 322 determines that a detected error is not correctable using the ECC, the ECC correction module 322 sends an interrupt.
The depacketizer 324 receives 618 the requested packet after the ECC correction module 322 corrects any errors and depacketizes 618 the packets by checking and removing the packet header of each packet. The alignment module 326 receives packets after depacketizing, removes unwanted data, and re-formats 620 the data packets as data or metadata segments of an object in a form compatible with the device requesting the segment or object. The output buffer 330 receives requested packets after depacketizing and buffers 622 the packets prior to transmission to the requesting device 155, and the method 600 ends 624.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
This application is a continuation of and U.S. patent application Ser. No. 15/402,936 entitled “Apparatus, System, and Method for Managing Commands of Solid-State Storage Using Bank Interleave” and filed on Jan. 10, 2017 for David Flynn, et al., which is a continuation of and U.S. patent application Ser. No. 11/952,095 entitled “Apparatus, System, and Method for Managing Commands of Solid-State Storage Using Bank Interleave” and filed on Dec. 6, 2007 for David Flynn, et al., now U.S. Pat. No. 9,575,902, which claims priority to U.S. Provisional Patent Application No. 60/873,111 entitled “Elemental Blade System” and filed on Dec. 6, 2006 for David Flynn, et al., and U.S. Provisional Patent Application No. 60/974,470 entitled “Apparatus, System, and Method for Object-Oriented Solid-State Storage” and filed on Sep. 22, 2007 for David Flynn, et al., all of which are incorporated herein by reference in their entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3478251 | Perotto et al. | Nov 1969 | A |
| 4092732 | Ouchi | May 1978 | A |
| 4290105 | Cichelli et al. | Sep 1981 | A |
| 4571674 | Hartung | Feb 1986 | A |
| 4584665 | Vrielink | Apr 1986 | A |
| 4761785 | Clark et al. | Aug 1988 | A |
| 4858070 | Buron et al. | Aug 1989 | A |
| 4980861 | Herdt et al. | Dec 1990 | A |
| 5043871 | Nishigaki et al. | Aug 1991 | A |
| 5111463 | Zook | May 1992 | A |
| 5124987 | Milligan et al. | Jun 1992 | A |
| 5151905 | Yokono et al. | Sep 1992 | A |
| 5193184 | Belsan et al. | Mar 1993 | A |
| 5226154 | Kondoh | Jul 1993 | A |
| 5261068 | Gaskins et al. | Nov 1993 | A |
| 5263003 | Cowles et al. | Nov 1993 | A |
| 5274799 | Brant et al. | Dec 1993 | A |
| 5291496 | Andaleon et al. | Mar 1994 | A |
| 5307497 | Feigenbaum et al. | Apr 1994 | A |
| 5313475 | Cromer et al. | May 1994 | A |
| 5323489 | Bird | Jun 1994 | A |
| 5325509 | Lautzenheiser | Jun 1994 | A |
| 5325523 | Beglin et al. | Jun 1994 | A |
| 5337275 | Garner | Aug 1994 | A |
| 5357475 | Hasbun et al. | Oct 1994 | A |
| 5379304 | Dell et al. | Jan 1995 | A |
| 5381528 | Brunelle | Jan 1995 | A |
| 5382950 | Gronemeyer | Jan 1995 | A |
| 5388083 | Assar et al. | Feb 1995 | A |
| 5388108 | DeMoss et al. | Feb 1995 | A |
| 5392427 | Barrett et al. | Feb 1995 | A |
| 5394531 | Smith | Feb 1995 | A |
| 5404485 | Ban | Apr 1995 | A |
| 5414840 | Rengarajan et al. | May 1995 | A |
| 5422856 | Sasaki et al. | Jun 1995 | A |
| 5434994 | Shaheen et al. | Jul 1995 | A |
| 5438671 | Miles | Aug 1995 | A |
| 5457658 | Niijima et al. | Oct 1995 | A |
| 5465355 | Cook et al. | Nov 1995 | A |
| 5469555 | Ghosh et al. | Nov 1995 | A |
| 5479638 | Assar et al. | Dec 1995 | A |
| 5485595 | Assar et al. | Jan 1996 | A |
| 5490248 | Dan et al. | Feb 1996 | A |
| 5499354 | Aschoff et al. | Mar 1996 | A |
| 5499367 | Bamford et al. | Mar 1996 | A |
| 5504882 | Chai et al. | Apr 1996 | A |
| 5535328 | Harari et al. | Jul 1996 | A |
| 5535391 | Hejlsberg et al. | Jul 1996 | A |
| 5535399 | Blitz et al. | Jul 1996 | A |
| 5541886 | Hasbun | Jul 1996 | A |
| 5544356 | Robinson et al. | Aug 1996 | A |
| 5548757 | Matsuyama et al. | Aug 1996 | A |
| 5551003 | Mattson et al. | Aug 1996 | A |
| 5553261 | Hasbun et al. | Sep 1996 | A |
| 5559988 | Durante et al. | Sep 1996 | A |
| 5561784 | Chen et al. | Oct 1996 | A |
| 5566315 | Milillo et al. | Oct 1996 | A |
| 5574882 | Menon et al. | Nov 1996 | A |
| 5579474 | Kakuta et al. | Nov 1996 | A |
| 5586291 | Lasker et al. | Dec 1996 | A |
| 5592641 | Fandrich et al. | Jan 1997 | A |
| 5594883 | Pricer | Jan 1997 | A |
| 5596708 | Weber | Jan 1997 | A |
| 5596736 | Kerns | Jan 1997 | A |
| 5598370 | Niijima et al. | Jan 1997 | A |
| 5603001 | Sukegawa et al. | Feb 1997 | A |
| 5638289 | Yamada et al. | Jun 1997 | A |
| 5651133 | Burkes et al. | Jul 1997 | A |
| 5664096 | Ichinomiya et al. | Sep 1997 | A |
| 5664187 | Burkes et al. | Sep 1997 | A |
| 5680579 | Young et al. | Oct 1997 | A |
| 5682497 | Robinson | Oct 1997 | A |
| 5682499 | Bakke et al. | Oct 1997 | A |
| 5701434 | Nakagawa | Dec 1997 | A |
| 5720025 | Wilkes et al. | Feb 1998 | A |
| 5721874 | Carnevale et al. | Feb 1998 | A |
| 5734861 | Cohn et al. | Mar 1998 | A |
| 5742787 | Talreja | Apr 1998 | A |
| 5745671 | Hodges | Apr 1998 | A |
| 5745673 | Di Zenzo et al. | Apr 1998 | A |
| 5745792 | Jost | Apr 1998 | A |
| 5754563 | White | May 1998 | A |
| 5754567 | Norman | May 1998 | A |
| 5757567 | Hetzler et al. | May 1998 | A |
| 5758118 | Choy et al. | May 1998 | A |
| 5761402 | Kaneda et al. | Jun 1998 | A |
| 5765207 | Curran | Jun 1998 | A |
| 5768152 | Battaline et al. | Jun 1998 | A |
| 5787486 | Chin | Jul 1998 | A |
| 5797022 | Shimotono et al. | Aug 1998 | A |
| 5798968 | Lee et al. | Aug 1998 | A |
| 5799140 | Niijima et al. | Aug 1998 | A |
| 5799200 | Brant et al. | Aug 1998 | A |
| 5802602 | Rahman et al. | Sep 1998 | A |
| 5805501 | Shiau et al. | Sep 1998 | A |
| 5809515 | Kaki et al. | Sep 1998 | A |
| 5809527 | Cooper et al. | Sep 1998 | A |
| 5809543 | Byers et al. | Sep 1998 | A |
| 5812457 | Arase | Sep 1998 | A |
| 5822759 | Treynor | Oct 1998 | A |
| 5831989 | Fujisaki | Nov 1998 | A |
| 5832515 | Ledain et al. | Nov 1998 | A |
| 5835935 | Estakh et al. | Nov 1998 | A |
| 5835964 | Draves et al. | Nov 1998 | A |
| 5845313 | Estakhri et al. | Dec 1998 | A |
| 5845329 | Onishi et al. | Dec 1998 | A |
| 5854796 | Sato | Dec 1998 | A |
| 5860083 | Sukegawa | Jan 1999 | A |
| 5867430 | Chen et al. | Feb 1999 | A |
| 5873118 | Letwin | Feb 1999 | A |
| 5890192 | Lee et al. | Mar 1999 | A |
| 5893086 | Schmuck et al. | Apr 1999 | A |
| 5893138 | Judd et al. | Apr 1999 | A |
| 5907856 | Estakhri et al. | May 1999 | A |
| 5920869 | Wakayama et al. | Jul 1999 | A |
| 5922080 | Olarig | Jul 1999 | A |
| 5924113 | Estakhri et al. | Jul 1999 | A |
| 5930815 | Estakhri et al. | Jul 1999 | A |
| 5933847 | Ogawa | Aug 1999 | A |
| 5953737 | Estakhri et al. | Sep 1999 | A |
| 5957158 | Volz et al. | Sep 1999 | A |
| 5958067 | Kaneda et al. | Sep 1999 | A |
| 5960462 | Solomon et al. | Sep 1999 | A |
| 5961660 | Capps, Jr. et al. | Oct 1999 | A |
| 5969986 | Wong et al. | Oct 1999 | A |
| 5996046 | Yagisawa et al. | Nov 1999 | A |
| 5996054 | Ledain et al. | Nov 1999 | A |
| 6000006 | Bruce et al. | Dec 1999 | A |
| 6000019 | Dykstal et al. | Dec 1999 | A |
| 6003123 | Carter et al. | Dec 1999 | A |
| 6014724 | Jenett | Jan 2000 | A |
| 6014747 | Fackenthall et al. | Jan 2000 | A |
| 6034882 | Johnson et al. | Mar 2000 | A |
| 6034897 | Estakhri et al. | Mar 2000 | A |
| 6038619 | Berning et al. | Mar 2000 | A |
| 6044438 | Olnowich | Mar 2000 | A |
| 6047334 | Langendorf et al. | Apr 2000 | A |
| 6049890 | Kakuta et al. | Apr 2000 | A |
| 6061511 | Marantz et al. | May 2000 | A |
| 6069827 | Sinclair | May 2000 | A |
| 6073232 | Kroeker et al. | Jun 2000 | A |
| 6078520 | Tobita et al. | Jun 2000 | A |
| 6092158 | Harriman et al. | Jul 2000 | A |
| 6092215 | Hodges et al. | Jul 2000 | A |
| 6101601 | Matthews et al. | Aug 2000 | A |
| 6105076 | Beardsley et al. | Aug 2000 | A |
| 6112319 | Paulson | Aug 2000 | A |
| 6115793 | Gruber et al. | Sep 2000 | A |
| 6125072 | Wu | Sep 2000 | A |
| 6128695 | Estakhri et al. | Oct 2000 | A |
| 6138125 | DeMoss | Oct 2000 | A |
| 6141249 | Estakhri et al. | Oct 2000 | A |
| 6145051 | Estakhri et al. | Nov 2000 | A |
| 6148377 | Carter et al. | Nov 2000 | A |
| 6157963 | Courtright, II et al. | Dec 2000 | A |
| 6170039 | Kishida | Jan 2001 | B1 |
| 6170042 | Gaertner et al. | Jan 2001 | B1 |
| 6170047 | Dye | Jan 2001 | B1 |
| 6172906 | Estakh et al. | Jan 2001 | B1 |
| 6173381 | Dye | Jan 2001 | B1 |
| 6185654 | Van Doren | Feb 2001 | B1 |
| 6188619 | Jung | Feb 2001 | B1 |
| 6189078 | Bauman et al. | Feb 2001 | B1 |
| 6205521 | Schumann | Mar 2001 | B1 |
| 6209000 | Klein et al. | Mar 2001 | B1 |
| 6209003 | Mattis et al. | Mar 2001 | B1 |
| 6209088 | Reneris | Mar 2001 | B1 |
| 6219751 | Hodges | Apr 2001 | B1 |
| 6223308 | Estakhri et al. | Apr 2001 | B1 |
| 6230234 | Estakhri et al. | May 2001 | B1 |
| 6236593 | Hong et al. | May 2001 | B1 |
| 6237059 | Dean et al. | May 2001 | B1 |
| 6240040 | Akaogi et al. | May 2001 | B1 |
| 6256642 | Krueger et al. | Jul 2001 | B1 |
| 6256749 | Kakuta et al. | Jul 2001 | B1 |
| 6262918 | Estakhri et al. | Jul 2001 | B1 |
| 6269382 | Cabrera et al. | Jul 2001 | B1 |
| 6278633 | Wong et al. | Aug 2001 | B1 |
| 6279041 | Baber et al. | Aug 2001 | B1 |
| 6279069 | Robinson et al. | Aug 2001 | B1 |
| 6289413 | Rogers et al. | Sep 2001 | B1 |
| 6295571 | Scardamalia et al. | Sep 2001 | B1 |
| 6295577 | Anderson et al. | Sep 2001 | B1 |
| 6295581 | DeRoo | Sep 2001 | B1 |
| 6298401 | Anderson | Oct 2001 | B1 |
| 6311290 | Hasbun et al. | Oct 2001 | B1 |
| 6311305 | Sollish et al. | Oct 2001 | B1 |
| 6321263 | Luzzi et al. | Nov 2001 | B1 |
| 6321345 | Mann et al. | Nov 2001 | B1 |
| 6330688 | Brown | Dec 2001 | B1 |
| 6334173 | Won et al. | Dec 2001 | B1 |
| 6336174 | Li et al. | Jan 2002 | B1 |
| 6341289 | Burroughs et al. | Jan 2002 | B1 |
| 6347341 | Glassen et al. | Feb 2002 | B1 |
| 6353878 | Dunham | Mar 2002 | B1 |
| 6356986 | Solomon et al. | Mar 2002 | B1 |
| 6370631 | Dye | Apr 2002 | B1 |
| 6374266 | Shnelvar | Apr 2002 | B1 |
| 6374336 | Peters et al. | Apr 2002 | B1 |
| 6385688 | Mills et al. | May 2002 | B1 |
| 6385710 | Goldman et al. | May 2002 | B1 |
| 6393513 | Estakhri et al. | May 2002 | B2 |
| 6401175 | Tremblay et al. | Jun 2002 | B1 |
| 6404647 | Minne' | Jun 2002 | B1 |
| 6404676 | Kihara et al. | Jun 2002 | B2 |
| 6405201 | Nazari | Jun 2002 | B1 |
| 6407930 | Hsu | Jun 2002 | B1 |
| 6412030 | Adusumilli | Jun 2002 | B1 |
| 6412080 | Fleming et al. | Jun 2002 | B1 |
| 6418478 | Ignatius et al. | Jul 2002 | B1 |
| 6418509 | Yanai et al. | Jul 2002 | B1 |
| 6420215 | Knall et al. | Jul 2002 | B1 |
| 6424872 | Glanzer et al. | Jul 2002 | B1 |
| 6446188 | Henderson et al. | Sep 2002 | B1 |
| 6449688 | Peters et al. | Sep 2002 | B1 |
| 6467011 | Scardamalia et al. | Oct 2002 | B2 |
| 6467022 | Buckland et al. | Oct 2002 | B1 |
| 6470238 | Nizar et al. | Oct 2002 | B1 |
| 6477617 | Golding | Nov 2002 | B1 |
| 6480933 | Cargem et al. | Nov 2002 | B1 |
| 6487636 | Dolphin et al. | Nov 2002 | B1 |
| 6496366 | Coglitore et al. | Dec 2002 | B1 |
| 6507911 | Langford | Jan 2003 | B1 |
| 6513112 | Craig et al. | Jan 2003 | B1 |
| 6515909 | Wooldridge | Feb 2003 | B1 |
| 6515928 | Sato et al. | Feb 2003 | B2 |
| 6516380 | Kenchammana-Hoskote et al. | Feb 2003 | B2 |
| 6519185 | Harari et al. | Feb 2003 | B2 |
| 6523102 | Dye et al. | Feb 2003 | B1 |
| 6525953 | Johnson | Feb 2003 | B1 |
| 6526482 | Nonoyama et al. | Feb 2003 | B1 |
| 6532527 | Selkirk et al. | Mar 2003 | B2 |
| 6535869 | Housel, III | Mar 2003 | B1 |
| 6535949 | Parker | Mar 2003 | B1 |
| 6535997 | Janson et al. | Mar 2003 | B1 |
| 6549987 | Rappoport et al. | Apr 2003 | B1 |
| 6552955 | Miki | Apr 2003 | B1 |
| 6556440 | Jensen et al. | Apr 2003 | B2 |
| 6557084 | Freerksen et al. | Apr 2003 | B2 |
| 6564285 | Mills et al. | May 2003 | B1 |
| 6567307 | Estakh | May 2003 | B1 |
| 6567889 | DeKoning et al. | May 2003 | B1 |
| 6571312 | Sugai et al. | May 2003 | B1 |
| D475705 | Coglitore et al. | Jun 2003 | S |
| 6578113 | Krishnamurthy et al. | Jun 2003 | B2 |
| 6587915 | Kim | Jul 2003 | B1 |
| 6587937 | Jensen et al. | Jul 2003 | B1 |
| 6594712 | Pettey et al. | Jul 2003 | B1 |
| 6601151 | Harris | Jul 2003 | B1 |
| 6601211 | Norman | Jul 2003 | B1 |
| 6604168 | Ogawa | Aug 2003 | B2 |
| 6608793 | Park et al. | Aug 2003 | B2 |
| 6611836 | Davis et al. | Aug 2003 | B2 |
| 6615355 | Mattison | Sep 2003 | B2 |
| 6618451 | Gonikberg | Sep 2003 | B1 |
| 6622200 | Hasbun et al. | Sep 2003 | B1 |
| 6625685 | Cho et al. | Sep 2003 | B1 |
| 6629112 | Shank et al. | Sep 2003 | B1 |
| 6633950 | Brown et al. | Oct 2003 | B1 |
| 6633956 | Mitani | Oct 2003 | B1 |
| 6643181 | Sofer et al. | Nov 2003 | B2 |
| 6643748 | Wieland | Nov 2003 | B1 |
| 6655758 | Pasotti et al. | Dec 2003 | B2 |
| 6658438 | Moore et al. | Dec 2003 | B1 |
| 6671757 | Multer et al. | Dec 2003 | B1 |
| 6675318 | Lee | Jan 2004 | B1 |
| 6675349 | Chen | Jan 2004 | B1 |
| 6683810 | Sakamoto | Jan 2004 | B2 |
| 6684274 | Chong, Jr. | Jan 2004 | B1 |
| 6684301 | Martin | Jan 2004 | B1 |
| 6694281 | Arnaout et al. | Feb 2004 | B2 |
| 6694453 | Shukla et al. | Feb 2004 | B1 |
| 6697076 | Trivedi et al. | Feb 2004 | B1 |
| 6697797 | Hoggatt et al. | Feb 2004 | B1 |
| 6697878 | Imai | Feb 2004 | B1 |
| 6701452 | Kinjo et al. | Mar 2004 | B1 |
| 6710901 | Pastor | Mar 2004 | B2 |
| 6715027 | Kim et al. | Mar 2004 | B2 |
| 6715046 | Shoham et al. | Mar 2004 | B1 |
| 6724640 | Cooper | Apr 2004 | B1 |
| 6725321 | Sinclair et al. | Apr 2004 | B1 |
| 6725342 | Coulson | Apr 2004 | B1 |
| 6728851 | Estakh et al. | Apr 2004 | B1 |
| 6728866 | Kahle et al. | Apr 2004 | B1 |
| 6735546 | Scheuerlein | May 2004 | B2 |
| 6737675 | Patel et al. | May 2004 | B2 |
| 6742078 | Chien et al. | May 2004 | B1 |
| 6742081 | Talagala et al. | May 2004 | B2 |
| 6745284 | Lee et al. | Jun 2004 | B1 |
| 6745292 | Stevens | Jun 2004 | B1 |
| 6748487 | Takamoto et al. | Jun 2004 | B1 |
| 6748504 | Sawdon et al. | Jun 2004 | B2 |
| 6751155 | Gorobets | Jun 2004 | B2 |
| 6751769 | Chen et al. | Jun 2004 | B2 |
| 6754773 | Ulrich et al. | Jun 2004 | B2 |
| 6754774 | Gruner et al. | Jun 2004 | B2 |
| 6754800 | Wong et al. | Jun 2004 | B2 |
| 6757800 | Estakhri et al. | Jun 2004 | B1 |
| 6760805 | Lasser | Jul 2004 | B2 |
| 6760806 | Jeon | Jul 2004 | B2 |
| 6763424 | Conley | Jul 2004 | B2 |
| 6763440 | Traversat et al. | Jul 2004 | B1 |
| 6766432 | Saltz | Jul 2004 | B2 |
| 6775185 | Fujisawa et al. | Aug 2004 | B2 |
| 6779045 | Kendall et al. | Aug 2004 | B2 |
| 6779080 | Basham et al. | Aug 2004 | B2 |
| 6779088 | Benveniste et al. | Aug 2004 | B1 |
| 6779094 | Selkirk et al. | Aug 2004 | B2 |
| 6779145 | Edwards et al. | Aug 2004 | B1 |
| 6785078 | Basham et al. | Aug 2004 | B2 |
| 6785768 | Peters et al. | Aug 2004 | B2 |
| 6785776 | Arimilli et al. | Aug 2004 | B2 |
| 6785785 | Piccirillo et al. | Aug 2004 | B2 |
| 6795890 | Sugai et al. | Sep 2004 | B1 |
| 6801979 | Estakh | Oct 2004 | B1 |
| 6804755 | Selkirk et al. | Oct 2004 | B2 |
| 6807097 | Takano et al. | Oct 2004 | B2 |
| 6816917 | Dicorpo et al. | Nov 2004 | B2 |
| 6823398 | Lee et al. | Nov 2004 | B1 |
| 6824393 | Debord et al. | Nov 2004 | B2 |
| 6839819 | Martin | Jan 2005 | B2 |
| 6839826 | Cernea | Jan 2005 | B2 |
| 6845053 | Chevallier | Jan 2005 | B2 |
| 6845428 | Kedem | Jan 2005 | B1 |
| 6849480 | Low et al. | Feb 2005 | B1 |
| 6849905 | Ilkbahar et al. | Feb 2005 | B2 |
| 6850408 | Coglitore et al. | Feb 2005 | B1 |
| 6850969 | Ladan-Mozes et al. | Feb 2005 | B2 |
| 6859824 | Yamamoto et al. | Feb 2005 | B1 |
| 6862692 | Ulrich et al. | Mar 2005 | B2 |
| 6865657 | Traversat et al. | Mar 2005 | B1 |
| 6871257 | Conley et al. | Mar 2005 | B2 |
| 6871295 | Ulrich et al. | Mar 2005 | B2 |
| 6877076 | Cho et al. | Apr 2005 | B1 |
| 6880049 | Gruner et al. | Apr 2005 | B2 |
| 6881994 | Lee et al. | Apr 2005 | B2 |
| 6883044 | Roohparvar | Apr 2005 | B1 |
| 6883068 | Tsirigotis et al. | Apr 2005 | B2 |
| 6883069 | Yoshida | Apr 2005 | B2 |
| 6883079 | Priborsky | Apr 2005 | B1 |
| 6887058 | Fujiwara | May 2005 | B2 |
| 6892298 | West | May 2005 | B2 |
| 6901499 | Aasheim et al. | May 2005 | B2 |
| 6906961 | Eggleston et al. | Jun 2005 | B2 |
| 6910170 | Choi et al. | Jun 2005 | B2 |
| 6912537 | Selkirk et al. | Jun 2005 | B2 |
| 6912598 | Bedarida et al. | Jun 2005 | B1 |
| 6912618 | Estakhri et al. | Jun 2005 | B2 |
| 6914853 | Coulson | Jul 2005 | B2 |
| 6920522 | Roohparvar | Jul 2005 | B2 |
| 6922754 | Liu et al. | Jul 2005 | B2 |
| 6928505 | Klingman | Aug 2005 | B1 |
| 6931509 | Lloyd-Jones | Aug 2005 | B2 |
| 6932617 | Debord et al. | Aug 2005 | B2 |
| 6938133 | Johnson et al. | Aug 2005 | B2 |
| 6938252 | Baylor et al. | Aug 2005 | B2 |
| 6950952 | Felsman | Sep 2005 | B2 |
| 6950966 | Chiquoine et al. | Sep 2005 | B2 |
| 6957158 | Hancock et al. | Oct 2005 | B1 |
| 6959369 | Ashton et al. | Oct 2005 | B1 |
| 6968421 | Conley | Nov 2005 | B2 |
| 6973531 | Chang et al. | Dec 2005 | B1 |
| 6973551 | Walton | Dec 2005 | B1 |
| 6977599 | Widmer | Dec 2005 | B2 |
| 6977847 | Lasser et al. | Dec 2005 | B2 |
| 6978342 | Estakhri et al. | Dec 2005 | B1 |
| 6981070 | Luk et al. | Dec 2005 | B1 |
| 6988151 | Tsuruta | Jan 2006 | B2 |
| 6990547 | Ulrich et al. | Jan 2006 | B2 |
| 6990553 | Nakayama et al. | Jan 2006 | B2 |
| 6996676 | Megiddo et al. | Feb 2006 | B2 |
| 7000063 | Friedman et al. | Feb 2006 | B2 |
| 7005350 | Walker et al. | Feb 2006 | B2 |
| 7010652 | Piccirillo et al. | Mar 2006 | B2 |
| 7010662 | Aasheim et al. | Mar 2006 | B2 |
| 7010663 | George et al. | Mar 2006 | B2 |
| 7013364 | Honda et al. | Mar 2006 | B2 |
| 7013376 | Hooper, III | Mar 2006 | B2 |
| 7013379 | Testardi | Mar 2006 | B1 |
| 7024695 | Kumar et al. | Apr 2006 | B1 |
| 7035111 | Lin et al. | Apr 2006 | B1 |
| 7035974 | Shang | Apr 2006 | B2 |
| 7042664 | Gill et al. | May 2006 | B2 |
| 7043599 | Ware et al. | May 2006 | B1 |
| 7045717 | Kolvick et al. | May 2006 | B2 |
| 7047366 | Ezra | May 2006 | B1 |
| 7050337 | Iwase et al. | May 2006 | B2 |
| 7057936 | Yaegashi et al. | Jun 2006 | B2 |
| 7057942 | Suda et al. | Jun 2006 | B2 |
| 7058769 | Danilak | Jun 2006 | B1 |
| 7064994 | Wu | Jun 2006 | B1 |
| 7065618 | Ghemawat et al. | Jun 2006 | B1 |
| 7069307 | Lee et al. | Jun 2006 | B1 |
| 7069349 | Hawkins et al. | Jun 2006 | B2 |
| 7069380 | Ogawa et al. | Jun 2006 | B2 |
| 7076599 | Aasheim et al. | Jul 2006 | B2 |
| 7076688 | Yamamoto | Jul 2006 | B2 |
| 7076723 | Saliba | Jul 2006 | B2 |
| 7080193 | Roohparvar | Jul 2006 | B2 |
| 7081377 | Cleeves | Jul 2006 | B2 |
| 7082495 | DeWhitt et al. | Jul 2006 | B2 |
| 7082512 | Aasheim et al. | Jul 2006 | B2 |
| 7085879 | Aasheim et al. | Aug 2006 | B2 |
| 7085953 | Hsu et al. | Aug 2006 | B1 |
| 7085983 | Ohta | Aug 2006 | B2 |
| 7089391 | Geiger et al. | Aug 2006 | B2 |
| 7093101 | Aasheim et al. | Aug 2006 | B2 |
| 7096321 | Modha | Aug 2006 | B2 |
| 7107419 | Ghemawat et al. | Sep 2006 | B1 |
| 7107430 | Grossman et al. | Sep 2006 | B2 |
| 7107480 | Moshayedi et al. | Sep 2006 | B1 |
| 7111115 | Peters et al. | Sep 2006 | B2 |
| 7111140 | Estakhri et al. | Sep 2006 | B2 |
| 7120051 | Gorobets et al. | Oct 2006 | B2 |
| 7130956 | Rao | Oct 2006 | B2 |
| 7130957 | Rao | Oct 2006 | B2 |
| 7130960 | Kano | Oct 2006 | B1 |
| 7136964 | Yamamoto | Nov 2006 | B2 |
| 7139864 | Bennett et al. | Nov 2006 | B2 |
| 7143228 | Iida et al. | Nov 2006 | B2 |
| 7149947 | Maclellan et al. | Dec 2006 | B1 |
| 7155559 | Estakhri et al. | Dec 2006 | B1 |
| 7162560 | Taylor et al. | Jan 2007 | B2 |
| 7162571 | Kilian et al. | Jan 2007 | B2 |
| 7165144 | Choubal et al. | Jan 2007 | B2 |
| 7167944 | Estakh | Jan 2007 | B1 |
| 7167953 | Megiddo et al. | Jan 2007 | B2 |
| 7171536 | Chang et al. | Jan 2007 | B2 |
| 7173852 | Gorobets et al. | Feb 2007 | B2 |
| 7177197 | Cernea | Feb 2007 | B2 |
| 7178081 | Lee et al. | Feb 2007 | B2 |
| 7181569 | Greco et al. | Feb 2007 | B2 |
| 7181572 | Walmsley | Feb 2007 | B2 |
| 7185162 | Snyder | Feb 2007 | B1 |
| 7185265 | Kakuta et al. | Feb 2007 | B2 |
| 7194577 | Johnson et al. | Mar 2007 | B2 |
| 7194740 | Frank et al. | Mar 2007 | B1 |
| 7197567 | Fitzgerald | Mar 2007 | B1 |
| 7197657 | Tobias | Mar 2007 | B1 |
| 7200758 | Zimmer | Apr 2007 | B2 |
| 7203815 | Haswell | Apr 2007 | B2 |
| 7215580 | Gorobets | May 2007 | B2 |
| 7219197 | Hatakeyama | May 2007 | B2 |
| 7219238 | Saito et al. | May 2007 | B2 |
| 7225247 | Kennedy | May 2007 | B2 |
| 7227777 | Roohparvar | Jun 2007 | B2 |
| 7231401 | Inohara et al. | Jun 2007 | B1 |
| 7234082 | Lai et al. | Jun 2007 | B2 |
| 7237141 | Fredin | Jun 2007 | B2 |
| 7240152 | Nakayama et al. | Jul 2007 | B2 |
| 7243203 | Scheuerlein | Jul 2007 | B2 |
| 7246179 | Camara et al. | Jul 2007 | B2 |
| 7248691 | Pandit et al. | Jul 2007 | B1 |
| 7254672 | Murray et al. | Aug 2007 | B1 |
| 7254686 | Islam et al. | Aug 2007 | B2 |
| 7256641 | Namekawa et al. | Aug 2007 | B2 |
| 7257129 | Lee et al. | Aug 2007 | B2 |
| 7257690 | Baird | Aug 2007 | B1 |
| 7260820 | Waldspurger et al. | Aug 2007 | B1 |
| 7263591 | Estakh et al. | Aug 2007 | B2 |
| 7269534 | Mugunda et al. | Sep 2007 | B2 |
| 7272755 | Smith | Sep 2007 | B2 |
| 7275098 | Becher et al. | Sep 2007 | B1 |
| 7275135 | Coulson | Sep 2007 | B2 |
| 7280373 | Aizawa | Oct 2007 | B2 |
| 7280536 | Testardi | Oct 2007 | B2 |
| 7281076 | Yates et al. | Oct 2007 | B2 |
| 7284089 | Gall et al. | Oct 2007 | B2 |
| 7287109 | Barth et al. | Oct 2007 | B2 |
| 7290116 | Grohoski et al. | Oct 2007 | B1 |
| 7293165 | Tobias | Nov 2007 | B1 |
| 7293183 | Lee et al. | Nov 2007 | B2 |
| 7293196 | Hicken et al. | Nov 2007 | B2 |
| 7299339 | Ramesh | Nov 2007 | B2 |
| 7299354 | Khanna et al. | Nov 2007 | B2 |
| 7301805 | Gorobets et al. | Nov 2007 | B2 |
| 7305520 | Voigt et al. | Dec 2007 | B2 |
| 7305668 | Kennedy et al. | Dec 2007 | B2 |
| 7310711 | New et al. | Dec 2007 | B2 |
| 7318173 | Falik et al. | Jan 2008 | B1 |
| 7324614 | Lee et al. | Jan 2008 | B2 |
| 7328307 | Hoogterp | Feb 2008 | B2 |
| 7337201 | Yellin et al. | Feb 2008 | B1 |
| 7340558 | Lee et al. | Mar 2008 | B2 |
| 7340566 | Voth et al. | Mar 2008 | B2 |
| 7340581 | Gorobets et al. | Mar 2008 | B2 |
| 7340645 | Martin et al. | Mar 2008 | B1 |
| 7340665 | Tsang | Mar 2008 | B2 |
| 7343465 | Shibayama et al. | Mar 2008 | B2 |
| 7353324 | Tanaka | Apr 2008 | B2 |
| 7356651 | Liu et al. | Apr 2008 | B2 |
| 7356730 | Ulrich et al. | Apr 2008 | B2 |
| 7360015 | Matthews et al. | Apr 2008 | B2 |
| 7360037 | Higaki et al. | Apr 2008 | B2 |
| 7366808 | Kano et al. | Apr 2008 | B2 |
| 7366825 | Williams et al. | Apr 2008 | B2 |
| 7366868 | Reuter et al. | Apr 2008 | B2 |
| 7370163 | Yang et al. | May 2008 | B2 |
| 7373514 | Krueger et al. | May 2008 | B2 |
| 7376034 | Torabi et al. | May 2008 | B2 |
| 7380081 | Ji et al. | May 2008 | B2 |
| 7389465 | Radke et al. | Jun 2008 | B2 |
| 7392365 | Selkirk et al. | Jun 2008 | B2 |
| 7395384 | Sinclair et al. | Jul 2008 | B2 |
| 7398348 | Moore et al. | Jul 2008 | B2 |
| 7400537 | Hemink et al. | Jul 2008 | B2 |
| 7403424 | Hemink et al. | Jul 2008 | B2 |
| 7415575 | Tong et al. | Aug 2008 | B1 |
| 7418490 | Zhang et al. | Aug 2008 | B1 |
| 7424593 | Estakhri et al. | Sep 2008 | B2 |
| 7428691 | Ouchi | Sep 2008 | B2 |
| 7430465 | Liebl et al. | Sep 2008 | B2 |
| 7434097 | Guha et al. | Oct 2008 | B2 |
| 7437510 | Rosenbluth et al. | Oct 2008 | B2 |
| 7441067 | Gorobets et al. | Oct 2008 | B2 |
| 7441081 | Humlicek | Oct 2008 | B2 |
| 7441090 | Estakhri et al. | Oct 2008 | B2 |
| 7444460 | Nakanishi et al. | Oct 2008 | B2 |
| 7447847 | Louie et al. | Nov 2008 | B2 |
| 7450420 | Sinclair et al. | Nov 2008 | B2 |
| 7451128 | Song et al. | Nov 2008 | B2 |
| 7451344 | Roth | Nov 2008 | B1 |
| 7451346 | Katsuragi et al. | Nov 2008 | B2 |
| 7454555 | Ware et al. | Nov 2008 | B2 |
| 7457166 | Hemink et al. | Nov 2008 | B2 |
| 7457897 | Lee et al. | Nov 2008 | B1 |
| 7460432 | Warner | Dec 2008 | B2 |
| 7463521 | Li | Dec 2008 | B2 |
| 7463532 | Tran et al. | Dec 2008 | B2 |
| 7464221 | Nakamura et al. | Dec 2008 | B2 |
| 7464240 | Caulkins et al. | Dec 2008 | B2 |
| 7480766 | Gorobets | Jan 2009 | B2 |
| 7487235 | Andrews et al. | Feb 2009 | B2 |
| 7487320 | Bansal et al. | Feb 2009 | B2 |
| 7487343 | Insley et al. | Feb 2009 | B1 |
| 7495954 | Ito | Feb 2009 | B2 |
| 7499317 | Ito | Mar 2009 | B2 |
| 7499320 | Li | Mar 2009 | B2 |
| 7499338 | Ito | Mar 2009 | B2 |
| 7500000 | Groves et al. | Mar 2009 | B2 |
| 7502255 | Li | Mar 2009 | B2 |
| 7502369 | Teoh | Mar 2009 | B2 |
| 7502884 | Shah et al. | Mar 2009 | B1 |
| 7505321 | Scheuerlein et al. | Mar 2009 | B2 |
| 7509454 | Kano | Mar 2009 | B2 |
| 7516267 | Coulson et al. | Apr 2009 | B2 |
| 7522457 | Hemink et al. | Apr 2009 | B2 |
| 7523249 | Estakhri et al. | Apr 2009 | B1 |
| 7523546 | Vatanparast et al. | Apr 2009 | B2 |
| 7526614 | Van Riel | Apr 2009 | B2 |
| 7529905 | Sinclair | May 2009 | B2 |
| 7532537 | Solomon et al. | May 2009 | B2 |
| 7535766 | Ito | May 2009 | B2 |
| 7536491 | Kano et al. | May 2009 | B2 |
| 7548464 | Kim | Jun 2009 | B2 |
| 7549013 | Estakh et al. | Jun 2009 | B2 |
| 7552271 | Sinclair et al. | Jun 2009 | B2 |
| 7565569 | Zohar et al. | Jul 2009 | B2 |
| 7574554 | Tanaka et al. | Aug 2009 | B2 |
| 7580287 | Aritome | Aug 2009 | B2 |
| 7590796 | Rajan et al. | Sep 2009 | B2 |
| 7594471 | Koekemoer et al. | Sep 2009 | B2 |
| 7599967 | Girkar et al. | Oct 2009 | B2 |
| 7603532 | Rajan et al. | Oct 2009 | B2 |
| 7610348 | Kisley et al. | Oct 2009 | B2 |
| 7619912 | Bhakta et al. | Nov 2009 | B2 |
| 7619941 | Torabi et al. | Nov 2009 | B2 |
| 7620769 | Lee et al. | Nov 2009 | B2 |
| 7620773 | Nicholson et al. | Nov 2009 | B2 |
| 7624239 | Bennett et al. | Nov 2009 | B2 |
| 7630255 | Yang | Dec 2009 | B2 |
| 7631138 | Gonzalez et al. | Dec 2009 | B2 |
| 7631162 | Gorobets | Dec 2009 | B2 |
| 7640390 | Iwamura et al. | Dec 2009 | B2 |
| 7644206 | Lawson et al. | Jan 2010 | B2 |
| 7644239 | Ergan et al. | Jan 2010 | B2 |
| 7652922 | Kim et al. | Jan 2010 | B2 |
| 7660911 | McDaniel | Feb 2010 | B2 |
| 7660941 | Lee et al. | Feb 2010 | B2 |
| 7664239 | Groff et al. | Feb 2010 | B2 |
| 7664906 | Chung et al. | Feb 2010 | B2 |
| 7669019 | Fujibayashi et al. | Feb 2010 | B2 |
| 7673111 | Chen et al. | Mar 2010 | B2 |
| 7676625 | Cassiday et al. | Mar 2010 | B2 |
| 7676628 | Compton et al. | Mar 2010 | B1 |
| 7676728 | Resnick et al. | Mar 2010 | B2 |
| 7689599 | Shah et al. | Mar 2010 | B1 |
| 7689803 | Karr et al. | Mar 2010 | B2 |
| 7702873 | Griess et al. | Apr 2010 | B2 |
| 7707232 | Dussud et al. | Apr 2010 | B2 |
| 7707337 | Lee et al. | Apr 2010 | B2 |
| 7720864 | Muth et al. | May 2010 | B1 |
| 7721059 | Mylly et al. | May 2010 | B2 |
| 7725628 | Phan et al. | May 2010 | B1 |
| 7725661 | Liu et al. | May 2010 | B2 |
| 7734643 | Waterhouse et al. | Jun 2010 | B1 |
| 7743210 | Jernigan, IV et al. | Jun 2010 | B1 |
| 7752360 | Galles | Jul 2010 | B2 |
| 7752389 | Fan | Jul 2010 | B1 |
| 7761625 | Karamcheti et al. | Jul 2010 | B2 |
| 7773521 | Zhang et al. | Aug 2010 | B2 |
| 7774392 | Lin | Aug 2010 | B2 |
| 7774542 | Zhang et al. | Aug 2010 | B2 |
| 7777652 | Lee et al. | Aug 2010 | B2 |
| 7778092 | Klein | Aug 2010 | B2 |
| 7778961 | Chang et al. | Aug 2010 | B2 |
| 7783956 | Ko et al. | Aug 2010 | B2 |
| 7797479 | Trika et al. | Sep 2010 | B2 |
| 7818525 | Frost et al. | Oct 2010 | B1 |
| 7822887 | Torabi et al. | Oct 2010 | B2 |
| 7827442 | Sharma et al. | Nov 2010 | B2 |
| 7831783 | Pandit et al. | Nov 2010 | B2 |
| 7836226 | Flynn et al. | Nov 2010 | B2 |
| 7840839 | Scales et al. | Nov 2010 | B2 |
| 7853772 | Chang et al. | Dec 2010 | B2 |
| 7856528 | Frost et al. | Dec 2010 | B1 |
| 7865761 | Chilton | Jan 2011 | B1 |
| 7873693 | Mehrotra et al. | Jan 2011 | B1 |
| 7873782 | Terry et al. | Jan 2011 | B2 |
| 7873803 | Cheng | Jan 2011 | B2 |
| 7877539 | Sinclair et al. | Jan 2011 | B2 |
| 7881150 | Solomon et al. | Feb 2011 | B2 |
| 7882305 | Moritoki | Feb 2011 | B2 |
| 7885413 | Vasic et al. | Feb 2011 | B2 |
| 7898867 | Hazama et al. | Mar 2011 | B2 |
| 7903468 | Litsyn et al. | Mar 2011 | B2 |
| 7904647 | El-Batal et al. | Mar 2011 | B2 |
| 7908501 | Kim et al. | Mar 2011 | B2 |
| 7913051 | Todd et al. | Mar 2011 | B1 |
| 7917803 | Stefanus et al. | Mar 2011 | B2 |
| 7925879 | Yasaki et al. | Apr 2011 | B2 |
| 7925936 | Sommer | Apr 2011 | B1 |
| 7930326 | Doucette et al. | Apr 2011 | B2 |
| 7930589 | Lavastre et al. | Apr 2011 | B2 |
| 7934072 | Hobbet et al. | Apr 2011 | B2 |
| 7941591 | Aviles | May 2011 | B2 |
| 7944762 | Gorobets | May 2011 | B2 |
| 7958280 | Salessi et al. | Jun 2011 | B2 |
| 7970770 | Edwards | Jun 2011 | B2 |
| 7970806 | Park et al. | Jun 2011 | B2 |
| 7970919 | Duran | Jun 2011 | B1 |
| 7973531 | Findeklee et al. | Jul 2011 | B2 |
| 7978541 | Sutardja | Jul 2011 | B2 |
| 7984230 | Nasu et al. | Jul 2011 | B2 |
| 7991940 | Frydman et al. | Aug 2011 | B2 |
| 8001334 | Lee | Aug 2011 | B2 |
| 8001434 | Lee et al. | Aug 2011 | B1 |
| 8010738 | Chilton et al. | Aug 2011 | B1 |
| 8019938 | Flynn et al. | Sep 2011 | B2 |
| 8019940 | Flynn et al. | Sep 2011 | B2 |
| 8028120 | Mo et al. | Sep 2011 | B2 |
| 8046500 | Flynn et al. | Oct 2011 | B2 |
| 8046526 | Yeh | Oct 2011 | B2 |
| 8046551 | Sahin | Oct 2011 | B1 |
| 8055820 | Sebire | Nov 2011 | B2 |
| 8055922 | Brittain et al. | Nov 2011 | B2 |
| 8055979 | Wu et al. | Nov 2011 | B2 |
| 8074041 | Clark et al. | Dec 2011 | B2 |
| 8078794 | Lee et al. | Dec 2011 | B2 |
| 8081536 | Solomon et al. | Dec 2011 | B1 |
| 8090886 | Phan et al. | Jan 2012 | B2 |
| 8112574 | Lee et al. | Feb 2012 | B2 |
| 8127103 | Kano et al. | Feb 2012 | B2 |
| 8130551 | Oowada et al. | Mar 2012 | B2 |
| 8135900 | Kunimatsu et al. | Mar 2012 | B2 |
| 8135904 | Lasser et al. | Mar 2012 | B2 |
| 8151082 | Flynn et al. | Apr 2012 | B2 |
| 8156281 | Grosner et al. | Apr 2012 | B1 |
| 8161353 | Flynn et al. | Apr 2012 | B2 |
| 8171204 | Chow et al. | May 2012 | B2 |
| 8175099 | Hodges et al. | May 2012 | B2 |
| 8189407 | Strasser et al. | May 2012 | B2 |
| 8205015 | Flynn et al. | Jun 2012 | B2 |
| 8205060 | Hahn et al. | Jun 2012 | B2 |
| 8214583 | Sinclair et al. | Jul 2012 | B2 |
| 8214591 | Flynn et al. | Jul 2012 | B2 |
| 8234450 | Glover et al. | Jul 2012 | B2 |
| 8250295 | Amidi et al. | Aug 2012 | B2 |
| 8261005 | Flynn et al. | Sep 2012 | B2 |
| 8289801 | Smith et al. | Oct 2012 | B2 |
| 8296628 | Madan | Oct 2012 | B2 |
| 8301810 | Pang et al. | Oct 2012 | B2 |
| 8301833 | Chen et al. | Oct 2012 | B1 |
| 8315092 | Strasser et al. | Nov 2012 | B2 |
| 8359501 | Lee et al. | Jan 2013 | B1 |
| 8364888 | Melik-Martirosian et al. | Jan 2013 | B2 |
| 8402069 | Rajaram et al. | Mar 2013 | B2 |
| 8402226 | Faibish et al. | Mar 2013 | B1 |
| 8417901 | Lin | Apr 2013 | B2 |
| 8423701 | Perroni et al. | Apr 2013 | B2 |
| 8423710 | Gole | Apr 2013 | B1 |
| 8429242 | Todd | Apr 2013 | B1 |
| 8429436 | Fillingim et al. | Apr 2013 | B2 |
| 8446892 | Ji et al. | May 2013 | B2 |
| 8463846 | Girbal | Jun 2013 | B2 |
| 8489817 | Flynn et al. | Jul 2013 | B2 |
| 8489820 | Ellard | Jul 2013 | B1 |
| 8495292 | Flynn et al. | Jul 2013 | B2 |
| 8516185 | Lee et al. | Aug 2013 | B2 |
| 8516187 | Chen et al. | Aug 2013 | B2 |
| 8533391 | Song et al. | Sep 2013 | B2 |
| 8533406 | Flynn et al. | Sep 2013 | B2 |
| 8549230 | Chatterjee et al. | Oct 2013 | B1 |
| 8572310 | Oh et al. | Oct 2013 | B2 |
| 8595573 | Shalvi et al. | Nov 2013 | B2 |
| 8607028 | Kale et al. | Dec 2013 | B2 |
| 8694722 | Gorobets et al. | Apr 2014 | B2 |
| 8745011 | Kishi | Jun 2014 | B2 |
| 8762658 | Flynn et al. | Jun 2014 | B2 |
| 8838875 | Park | Sep 2014 | B2 |
| 8904091 | Guda et al. | Dec 2014 | B1 |
| 9015209 | Hahn et al. | Apr 2015 | B2 |
| 9116823 | Fillingim et al. | Aug 2015 | B2 |
| 9152556 | Olbrich et al. | Oct 2015 | B2 |
| 9170754 | Flynn et al. | Oct 2015 | B2 |
| 9207876 | Shu et al. | Dec 2015 | B2 |
| 9286198 | Bennett | Mar 2016 | B2 |
| 9495241 | Flynn et al. | Nov 2016 | B2 |
| 9575902 | Flynn et al. | Feb 2017 | B2 |
| 9632727 | Flynn et al. | Apr 2017 | B2 |
| 10013354 | Flynn et al. | Jul 2018 | B2 |
| 10133662 | Peterson et al. | Nov 2018 | B2 |
| 10216569 | Flynn et al. | Feb 2019 | B2 |
| 10296220 | Batwara et al. | May 2019 | B2 |
| 10331351 | Asnaashari et al. | Jun 2019 | B2 |
| 10387327 | Flynn et al. | Aug 2019 | B2 |
| 10387328 | Flynn et al. | Aug 2019 | B2 |
| 20010007533 | Kobayashi et al. | Jul 2001 | A1 |
| 20010008007 | Halligan et al. | Jul 2001 | A1 |
| 20010013087 | Ronstrom | Aug 2001 | A1 |
| 20010021924 | Ohno | Sep 2001 | A1 |
| 20010025360 | Kakuta et al. | Sep 2001 | A1 |
| 20010052093 | Oshima et al. | Dec 2001 | A1 |
| 20020002661 | Blumenau et al. | Jan 2002 | A1 |
| 20020035665 | Basham et al. | Mar 2002 | A1 |
| 20020048191 | Ikehashi et al. | Apr 2002 | A1 |
| 20020049883 | Schneider et al. | Apr 2002 | A1 |
| 20020051468 | Ofek et al. | May 2002 | A1 |
| 20020053009 | Selkirk et al. | May 2002 | A1 |
| 20020057798 | Zhang | May 2002 | A1 |
| 20020066047 | Olarig et al. | May 2002 | A1 |
| 20020069317 | Chow et al. | Jun 2002 | A1 |
| 20020069318 | Chow et al. | Jun 2002 | A1 |
| 20020078124 | Baylor et al. | Jun 2002 | A1 |
| 20020095403 | Chan et al. | Jul 2002 | A1 |
| 20020103819 | Duvillier et al. | Aug 2002 | A1 |
| 20020108016 | Haines et al. | Aug 2002 | A1 |
| 20020111996 | Jones et al. | Aug 2002 | A1 |
| 20020133743 | Oldfield et al. | Sep 2002 | A1 |
| 20020138686 | Yang et al. | Sep 2002 | A1 |
| 20020150154 | Warke | Oct 2002 | A1 |
| 20020154645 | Hu et al. | Oct 2002 | A1 |
| 20020156984 | Padovano | Oct 2002 | A1 |
| 20020161855 | Manczak et al. | Oct 2002 | A1 |
| 20020161972 | Talagala et al. | Oct 2002 | A1 |
| 20020174326 | Kling et al. | Nov 2002 | A1 |
| 20020181134 | Bunker et al. | Dec 2002 | A1 |
| 20020182899 | Debord et al. | Dec 2002 | A1 |
| 20020184481 | Bish et al. | Dec 2002 | A1 |
| 20020194451 | Mukaida et al. | Dec 2002 | A1 |
| 20020199056 | Ayukawa et al. | Dec 2002 | A1 |
| 20030002503 | Brewer et al. | Jan 2003 | A1 |
| 20030014598 | Brown | Jan 2003 | A1 |
| 20030023784 | Matsunami et al. | Jan 2003 | A1 |
| 20030023911 | Davis et al. | Jan 2003 | A1 |
| 20030028704 | Mukaida et al. | Feb 2003 | A1 |
| 20030028726 | Gaertner et al. | Feb 2003 | A1 |
| 20030033361 | Garnett et al. | Feb 2003 | A1 |
| 20030041211 | Merkey et al. | Feb 2003 | A1 |
| 20030046380 | Steger et al. | Mar 2003 | A1 |
| 20030056142 | Hashemi | Mar 2003 | A1 |
| 20030061296 | Craddock et al. | Mar 2003 | A1 |
| 20030065866 | Spencer | Apr 2003 | A1 |
| 20030070034 | Friedman et al. | Apr 2003 | A1 |
| 20030093741 | Argon et al. | May 2003 | A1 |
| 20030101025 | Shah et al. | May 2003 | A1 |
| 20030115405 | Funyu et al. | Jun 2003 | A1 |
| 20030126420 | Murayama et al. | Jul 2003 | A1 |
| 20030126475 | Bodas | Jul 2003 | A1 |
| 20030130969 | Hawkins et al. | Jul 2003 | A1 |
| 20030131182 | Kumar et al. | Jul 2003 | A1 |
| 20030135808 | Kakuta et al. | Jul 2003 | A1 |
| 20030140051 | Fujiwara et al. | Jul 2003 | A1 |
| 20030142764 | Keevill et al. | Jul 2003 | A1 |
| 20030145230 | Chiu et al. | Jul 2003 | A1 |
| 20030149753 | Lamb | Aug 2003 | A1 |
| 20030163630 | Aasheim et al. | Aug 2003 | A1 |
| 20030163633 | Aasheim et al. | Aug 2003 | A1 |
| 20030163663 | Aasheim et al. | Aug 2003 | A1 |
| 20030165076 | Gorobets et al. | Sep 2003 | A1 |
| 20030198084 | Fujisawa et al. | Oct 2003 | A1 |
| 20030204788 | Smith | Oct 2003 | A1 |
| 20030210601 | Lin et al. | Nov 2003 | A1 |
| 20030221060 | Umberger et al. | Nov 2003 | A1 |
| 20040003002 | Adelmann | Jan 2004 | A1 |
| 20040003167 | Kimura et al. | Jan 2004 | A1 |
| 20040010612 | Pandya | Jan 2004 | A1 |
| 20040010742 | Williamson et al. | Jan 2004 | A1 |
| 20040025064 | Felsman | Feb 2004 | A1 |
| 20040034750 | Horn | Feb 2004 | A1 |
| 20040044705 | Stager et al. | Mar 2004 | A1 |
| 20040044840 | Wong | Mar 2004 | A1 |
| 20040054867 | Stravers et al. | Mar 2004 | A1 |
| 20040059870 | Ash et al. | Mar 2004 | A1 |
| 20040064558 | Miyake | Apr 2004 | A1 |
| 20040064600 | Lee | Apr 2004 | A1 |
| 20040064647 | DeWhitt et al. | Apr 2004 | A1 |
| 20040070955 | Dobbs et al. | Apr 2004 | A1 |
| 20040073806 | Zimmer | Apr 2004 | A1 |
| 20040073829 | Olarig | Apr 2004 | A1 |
| 20040078456 | Kennedy et al. | Apr 2004 | A1 |
| 20040088514 | Bullen et al. | May 2004 | A1 |
| 20040093463 | Shang | May 2004 | A1 |
| 20040098544 | Gaither et al. | May 2004 | A1 |
| 20040098575 | Datta et al. | May 2004 | A1 |
| 20040103238 | Avraham et al. | May 2004 | A1 |
| 20040103245 | Fukusawa et al. | May 2004 | A1 |
| 20040117586 | Estakhri et al. | Jun 2004 | A1 |
| 20040122559 | Young et al. | Jun 2004 | A1 |
| 20040122888 | Carmichael | Jun 2004 | A1 |
| 20040128470 | Hetzler et al. | Jul 2004 | A1 |
| 20040133771 | King et al. | Jul 2004 | A1 |
| 20040139282 | Yoshioka et al. | Jul 2004 | A1 |
| 20040148360 | Mehra et al. | Jul 2004 | A1 |
| 20040150964 | Uzuka et al. | Aug 2004 | A1 |
| 20040158589 | Liang et al. | Aug 2004 | A1 |
| 20040177054 | Stern et al. | Sep 2004 | A1 |
| 20040177216 | Asari et al. | Sep 2004 | A1 |
| 20040186946 | Lee | Sep 2004 | A1 |
| 20040205177 | Levy et al. | Oct 2004 | A1 |
| 20040207440 | Robertson et al. | Oct 2004 | A1 |
| 20040221132 | Torkelsson et al. | Nov 2004 | A1 |
| 20040225719 | Kisley et al. | Nov 2004 | A1 |
| 20040225946 | Hashimoto et al. | Nov 2004 | A1 |
| 20040228063 | Hawkins et al. | Nov 2004 | A1 |
| 20040230710 | Goodman | Nov 2004 | A1 |
| 20040230866 | Yates et al. | Nov 2004 | A1 |
| 20040233910 | Chen et al. | Nov 2004 | A1 |
| 20040236761 | Both | Nov 2004 | A1 |
| 20040236798 | Srinivasan et al. | Nov 2004 | A1 |
| 20040247022 | Raghavan et al. | Dec 2004 | A1 |
| 20040250019 | Fujie et al. | Dec 2004 | A1 |
| 20040255122 | Ingerman et al. | Dec 2004 | A1 |
| 20040260947 | Brady et al. | Dec 2004 | A1 |
| 20040264847 | Koh et al. | Dec 2004 | A1 |
| 20040267482 | Robertson et al. | Dec 2004 | A1 |
| 20040267483 | Percer et al. | Dec 2004 | A1 |
| 20040267486 | Percer et al. | Dec 2004 | A1 |
| 20040268013 | Pagan | Dec 2004 | A1 |
| 20040268064 | Rudelic | Dec 2004 | A1 |
| 20040268359 | Hanes | Dec 2004 | A1 |
| 20050002263 | Iwase et al. | Jan 2005 | A1 |
| 20050005191 | Judd | Jan 2005 | A1 |
| 20050010715 | Davies et al. | Jan 2005 | A1 |
| 20050015539 | Horii et al. | Jan 2005 | A1 |
| 20050015685 | Yamamoto | Jan 2005 | A1 |
| 20050018527 | Gorobets | Jan 2005 | A1 |
| 20050021260 | Robertson et al. | Jan 2005 | A1 |
| 20050027851 | McKeown et al. | Feb 2005 | A1 |
| 20050027900 | Pettey | Feb 2005 | A1 |
| 20050027951 | Piccirillo et al. | Feb 2005 | A1 |
| 20050042893 | Debord et al. | Feb 2005 | A1 |
| 20050055495 | Vihmalo et al. | Mar 2005 | A1 |
| 20050055497 | Estakhri et al. | Mar 2005 | A1 |
| 20050071461 | Mihm et al. | Mar 2005 | A1 |
| 20050071677 | Khanna et al. | Mar 2005 | A1 |
| 20050076107 | Goud et al. | Apr 2005 | A1 |
| 20050080887 | Lee et al. | Apr 2005 | A1 |
| 20050080994 | Cohen et al. | Apr 2005 | A1 |
| 20050091215 | Chandra et al. | Apr 2005 | A1 |
| 20050091452 | Chen et al. | Apr 2005 | A1 |
| 20050097243 | Yamashita et al. | May 2005 | A1 |
| 20050097278 | Hsu et al. | May 2005 | A1 |
| 20050102437 | Pettey et al. | May 2005 | A1 |
| 20050108292 | Burton et al. | May 2005 | A1 |
| 20050114591 | Coronado et al. | May 2005 | A1 |
| 20050120177 | Black | Jun 2005 | A1 |
| 20050132148 | Arimilli et al. | Jun 2005 | A1 |
| 20050132259 | Emmot et al. | Jun 2005 | A1 |
| 20050138092 | Abuaiadh et al. | Jun 2005 | A1 |
| 20050141312 | Sinclair et al. | Jun 2005 | A1 |
| 20050141313 | Gorobets et al. | Jun 2005 | A1 |
| 20050144358 | Conley et al. | Jun 2005 | A1 |
| 20050144361 | Gonzalez et al. | Jun 2005 | A1 |
| 20050144418 | Kita | Jun 2005 | A1 |
| 20050149472 | Schreter | Jul 2005 | A1 |
| 20050149618 | Cheng | Jul 2005 | A1 |
| 20050149645 | Tsuruta | Jul 2005 | A1 |
| 20050149819 | Hwang | Jul 2005 | A1 |
| 20050154786 | Shackelford | Jul 2005 | A1 |
| 20050168962 | Takeuchi et al. | Aug 2005 | A1 |
| 20050172099 | Lowe | Aug 2005 | A1 |
| 20050177672 | Rao | Aug 2005 | A1 |
| 20050177687 | Rao | Aug 2005 | A1 |
| 20050193166 | Johnson et al. | Sep 2005 | A1 |
| 20050201306 | Engel | Sep 2005 | A1 |
| 20050204187 | Lee et al. | Sep 2005 | A1 |
| 20050210323 | Batchelor et al. | Sep 2005 | A1 |
| 20050216653 | Aasheim et al. | Sep 2005 | A1 |
| 20050223154 | Uemura | Oct 2005 | A1 |
| 20050228963 | Rothman et al. | Oct 2005 | A1 |
| 20050229090 | Shen et al. | Oct 2005 | A1 |
| 20050235082 | Sato | Oct 2005 | A1 |
| 20050235088 | Kang | Oct 2005 | A1 |
| 20050235103 | Saliba et al. | Oct 2005 | A1 |
| 20050235132 | Karr et al. | Oct 2005 | A1 |
| 20050238035 | Riley | Oct 2005 | A1 |
| 20050240713 | Wu et al. | Oct 2005 | A1 |
| 20050246487 | Ergan et al. | Nov 2005 | A1 |
| 20050246510 | Retnamma et al. | Nov 2005 | A1 |
| 20050246558 | Ku | Nov 2005 | A1 |
| 20050257017 | Yagi | Nov 2005 | A1 |
| 20050257213 | Chu et al. | Nov 2005 | A1 |
| 20050262150 | Krishnaswamy | Nov 2005 | A1 |
| 20050267882 | Aupperlee et al. | Dec 2005 | A1 |
| 20050268037 | Hama et al. | Dec 2005 | A1 |
| 20050270927 | Hayashi | Dec 2005 | A1 |
| 20050271079 | Teoh | Dec 2005 | A1 |
| 20050273476 | Wertheimer et al. | Dec 2005 | A1 |
| 20050276092 | Hansen et al. | Dec 2005 | A1 |
| 20050283489 | Shiozawa et al. | Dec 2005 | A1 |
| 20060004955 | Ware et al. | Jan 2006 | A1 |
| 20060015529 | Yagawa | Jan 2006 | A1 |
| 20060017963 | Sakuda et al. | Jan 2006 | A1 |
| 20060020616 | Hardy et al. | Jan 2006 | A1 |
| 20060020744 | Sinclair et al. | Jan 2006 | A1 |
| 20060020745 | Conley et al. | Jan 2006 | A1 |
| 20060020747 | Estakhri et al. | Jan 2006 | A1 |
| 20060026221 | Chen et al. | Feb 2006 | A1 |
| 20060026263 | Raghavan et al. | Feb 2006 | A1 |
| 20060026339 | Rostampour | Feb 2006 | A1 |
| 20060026341 | Lasser | Feb 2006 | A1 |
| 20060026347 | Hung | Feb 2006 | A1 |
| 20060026385 | Dinechin et al. | Feb 2006 | A1 |
| 20060036904 | Yang | Feb 2006 | A1 |
| 20060047920 | Moore et al. | Mar 2006 | A1 |
| 20060047926 | Zheng | Mar 2006 | A1 |
| 20060059326 | Aasheim et al. | Mar 2006 | A1 |
| 20060059358 | Galal et al. | Mar 2006 | A1 |
| 20060064556 | Aasheim et al. | Mar 2006 | A1 |
| 20060069868 | Nonaka et al. | Mar 2006 | A1 |
| 20060069870 | Nicholson et al. | Mar 2006 | A1 |
| 20060069885 | Matsui et al. | Mar 2006 | A1 |
| 20060074877 | Kuersch et al. | Apr 2006 | A1 |
| 20060075057 | Gildea et al. | Apr 2006 | A1 |
| 20060075146 | Schoinas et al. | Apr 2006 | A1 |
| 20060085471 | Rajan et al. | Apr 2006 | A1 |
| 20060085626 | Roberson et al. | Apr 2006 | A1 |
| 20060085670 | Carver et al. | Apr 2006 | A1 |
| 20060085674 | Ananthamurthy | Apr 2006 | A1 |
| 20060090048 | Okumoto et al. | Apr 2006 | A1 |
| 20060090948 | Allen | May 2006 | A1 |
| 20060095659 | New et al. | May 2006 | A1 |
| 20060095661 | Fleiner et al. | May 2006 | A1 |
| 20060106514 | Liebl et al. | May 2006 | A1 |
| 20060106968 | Wooi Teoh | May 2006 | A1 |
| 20060106990 | Benhase et al. | May 2006 | A1 |
| 20060107097 | Zohar et al. | May 2006 | A1 |
| 20060107127 | Park et al. | May 2006 | A1 |
| 20060112297 | Davidson | May 2006 | A1 |
| 20060114917 | Raisch | Jun 2006 | A1 |
| 20060117056 | Havewala et al. | Jun 2006 | A1 |
| 20060117153 | Tran et al. | Jun 2006 | A1 |
| 20060117155 | Ware et al. | Jun 2006 | A1 |
| 20060120235 | Jensen | Jun 2006 | A1 |
| 20060129556 | Reuter | Jun 2006 | A1 |
| 20060129778 | Clark et al. | Jun 2006 | A1 |
| 20060136464 | Rossmann | Jun 2006 | A1 |
| 20060136507 | Bangalore | Jun 2006 | A1 |
| 20060136657 | Rudelic et al. | Jun 2006 | A1 |
| 20060136685 | Griv et al. | Jun 2006 | A1 |
| 20060136687 | Conley et al. | Jun 2006 | A1 |
| 20060136749 | Satou et al. | Jun 2006 | A1 |
| 20060136779 | Lee et al. | Jun 2006 | A1 |
| 20060139069 | Frank et al. | Jun 2006 | A1 |
| 20060139330 | Kutch et al. | Jun 2006 | A1 |
| 20060143209 | Zimmer et al. | Jun 2006 | A1 |
| 20060143396 | Cabot | Jun 2006 | A1 |
| 20060149893 | Barfuss et al. | Jul 2006 | A1 |
| 20060149902 | Yun et al. | Jul 2006 | A1 |
| 20060149916 | Nase | Jul 2006 | A1 |
| 20060149954 | Hageman et al. | Jul 2006 | A1 |
| 20060152981 | Ryu | Jul 2006 | A1 |
| 20060153026 | Blacquiere et al. | Jul 2006 | A1 |
| 20060155921 | Gorobets et al. | Jul 2006 | A1 |
| 20060159456 | Gumaste et al. | Jul 2006 | A1 |
| 20060161725 | Lee et al. | Jul 2006 | A1 |
| 20060164111 | Lopez et al. | Jul 2006 | A1 |
| 20060168154 | Zhang et al. | Jul 2006 | A1 |
| 20060179263 | Song et al. | Aug 2006 | A1 |
| 20060184349 | Goud et al. | Aug 2006 | A1 |
| 20060184722 | Sinclair | Aug 2006 | A1 |
| 20060184736 | Benhase et al. | Aug 2006 | A1 |
| 20060190552 | Henze et al. | Aug 2006 | A1 |
| 20060206286 | Mugunda et al. | Sep 2006 | A1 |
| 20060206603 | Rajan et al. | Sep 2006 | A1 |
| 20060206664 | Umemura | Sep 2006 | A1 |
| 20060212644 | Acton et al. | Sep 2006 | A1 |
| 20060224849 | Rezaul Islam et al. | Oct 2006 | A1 |
| 20060230295 | Schumacher et al. | Oct 2006 | A1 |
| 20060236061 | Koclanes | Oct 2006 | A1 |
| 20060242330 | Torudbakken et al. | Oct 2006 | A1 |
| 20060248387 | Nicholson et al. | Nov 2006 | A1 |
| 20060253767 | Winarski et al. | Nov 2006 | A1 |
| 20060265624 | Moshayedi et al. | Nov 2006 | A1 |
| 20060265635 | Tokita et al. | Nov 2006 | A1 |
| 20060265636 | Hummler | Nov 2006 | A1 |
| 20060271725 | Wong | Nov 2006 | A1 |
| 20060271740 | Mark et al. | Nov 2006 | A1 |
| 20060280048 | Jung et al. | Dec 2006 | A1 |
| 20060288156 | Fish et al. | Dec 2006 | A1 |
| 20060293045 | LaDue | Dec 2006 | A1 |
| 20060294300 | Lubbers | Dec 2006 | A1 |
| 20060294336 | Gibble et al. | Dec 2006 | A1 |
| 20070005928 | Trika et al. | Jan 2007 | A1 |
| 20070006048 | Zimmer et al. | Jan 2007 | A1 |
| 20070011563 | Tsang | Jan 2007 | A1 |
| 20070016699 | Minami | Jan 2007 | A1 |
| 20070016730 | Cousin et al. | Jan 2007 | A1 |
| 20070016754 | Testardi | Jan 2007 | A1 |
| 20070016827 | Lopez et al. | Jan 2007 | A1 |
| 20070027948 | Engebretsen | Feb 2007 | A1 |
| 20070028035 | Nishihara | Feb 2007 | A1 |
| 20070028051 | Williamson et al. | Feb 2007 | A1 |
| 20070028053 | Shet et al. | Feb 2007 | A1 |
| 20070030734 | Sinclair et al. | Feb 2007 | A1 |
| 20070033318 | Gilday et al. | Feb 2007 | A1 |
| 20070033324 | Sinclair | Feb 2007 | A1 |
| 20070033325 | Sinclair | Feb 2007 | A1 |
| 20070033326 | Sinclair | Feb 2007 | A1 |
| 20070033327 | Sinclair | Feb 2007 | A1 |
| 20070033330 | Sinclair et al. | Feb 2007 | A1 |
| 20070033362 | Sinclair | Feb 2007 | A1 |
| 20070033371 | Dunshea et al. | Feb 2007 | A1 |
| 20070033376 | Sinclair et al. | Feb 2007 | A1 |
| 20070043900 | Yun | Feb 2007 | A1 |
| 20070043915 | Moir et al. | Feb 2007 | A1 |
| 20070050548 | Bali et al. | Mar 2007 | A1 |
| 20070050571 | Nakamura et al. | Mar 2007 | A1 |
| 20070055853 | Hatasaki et al. | Mar 2007 | A1 |
| 20070058610 | Brandstatter | Mar 2007 | A1 |
| 20070061508 | Zweighaft | Mar 2007 | A1 |
| 20070061515 | Kano | Mar 2007 | A1 |
| 20070061597 | Holtzman et al. | Mar 2007 | A1 |
| 20070067326 | Morris et al. | Mar 2007 | A1 |
| 20070069318 | Takeuchi et al. | Mar 2007 | A1 |
| 20070073975 | Lee et al. | Mar 2007 | A1 |
| 20070074092 | Dammann et al. | Mar 2007 | A1 |
| 20070083530 | Lakshminath et al. | Apr 2007 | A1 |
| 20070086260 | Sinclair | Apr 2007 | A1 |
| 20070088666 | Saito | Apr 2007 | A1 |
| 20070088974 | Chandwani et al. | Apr 2007 | A1 |
| 20070106870 | Bonwick et al. | May 2007 | A1 |
| 20070113150 | Resnick et al. | May 2007 | A1 |
| 20070118676 | Kano et al. | May 2007 | A1 |
| 20070118713 | Guterman et al. | May 2007 | A1 |
| 20070124474 | Margulis | May 2007 | A1 |
| 20070124533 | Estakh et al. | May 2007 | A1 |
| 20070124540 | Van Riel | May 2007 | A1 |
| 20070136555 | Sinclair | Jun 2007 | A1 |
| 20070141895 | Karstens | Jun 2007 | A1 |
| 20070143532 | Gorobets et al. | Jun 2007 | A1 |
| 20070143560 | Gorobets | Jun 2007 | A1 |
| 20070143561 | Gorobets | Jun 2007 | A1 |
| 20070143566 | Gorobets | Jun 2007 | A1 |
| 20070143567 | Gorobets | Jun 2007 | A1 |
| 20070143571 | Sinclair et al. | Jun 2007 | A1 |
| 20070143606 | Bandholz et al. | Jun 2007 | A1 |
| 20070147356 | Malas et al. | Jun 2007 | A1 |
| 20070147366 | Babbar et al. | Jun 2007 | A1 |
| 20070150689 | Pandit et al. | Jun 2007 | A1 |
| 20070156998 | Gorobets | Jul 2007 | A1 |
| 20070162830 | Stek et al. | Jul 2007 | A1 |
| 20070168564 | Conley et al. | Jul 2007 | A1 |
| 20070168625 | Cornwell et al. | Jul 2007 | A1 |
| 20070168641 | Hummel et al. | Jul 2007 | A1 |
| 20070168698 | Coulson et al. | Jul 2007 | A1 |
| 20070169030 | Tarditi, Jr. et al. | Jul 2007 | A1 |
| 20070169088 | Lambert et al. | Jul 2007 | A1 |
| 20070169106 | Douglas et al. | Jul 2007 | A1 |
| 20070171714 | Wu et al. | Jul 2007 | A1 |
| 20070174437 | Kraus | Jul 2007 | A1 |
| 20070174574 | Kano | Jul 2007 | A1 |
| 20070174686 | Douglas et al. | Jul 2007 | A1 |
| 20070174705 | Shih | Jul 2007 | A1 |
| 20070185902 | Messinger et al. | Aug 2007 | A1 |
| 20070186086 | Lambert et al. | Aug 2007 | A1 |
| 20070198770 | Horii et al. | Aug 2007 | A1 |
| 20070198852 | Choi et al. | Aug 2007 | A1 |
| 20070204100 | Shin et al. | Aug 2007 | A1 |
| 20070204128 | Lee et al. | Aug 2007 | A1 |
| 20070204197 | Yokokawa | Aug 2007 | A1 |
| 20070204199 | Chung et al. | Aug 2007 | A1 |
| 20070204270 | Shin | Aug 2007 | A1 |
| 20070204332 | Pan | Aug 2007 | A1 |
| 20070206630 | Bird | Sep 2007 | A1 |
| 20070208790 | Reuter et al. | Sep 2007 | A1 |
| 20070220227 | Long | Sep 2007 | A1 |
| 20070220369 | Fayad et al. | Sep 2007 | A1 |
| 20070220396 | Jackson | Sep 2007 | A1 |
| 20070230253 | Kim | Oct 2007 | A1 |
| 20070233455 | Zimmer et al. | Oct 2007 | A1 |
| 20070233937 | Coulson et al. | Oct 2007 | A1 |
| 20070233938 | Cho et al. | Oct 2007 | A1 |
| 20070234021 | Ruberg et al. | Oct 2007 | A1 |
| 20070239728 | Smits | Oct 2007 | A1 |
| 20070239926 | Gyl et al. | Oct 2007 | A1 |
| 20070245068 | Yero | Oct 2007 | A1 |
| 20070245076 | Chang et al. | Oct 2007 | A1 |
| 20070245094 | Lee et al. | Oct 2007 | A1 |
| 20070245217 | Valle | Oct 2007 | A1 |
| 20070250660 | Gill et al. | Oct 2007 | A1 |
| 20070255430 | Sharma et al. | Nov 2007 | A1 |
| 20070255891 | Chow et al. | Nov 2007 | A1 |
| 20070260608 | Hertzberg et al. | Nov 2007 | A1 |
| 20070260811 | Merry, Jr. et al. | Nov 2007 | A1 |
| 20070260813 | Lin | Nov 2007 | A1 |
| 20070260821 | Zeffer et al. | Nov 2007 | A1 |
| 20070261030 | Wadhwa | Nov 2007 | A1 |
| 20070263514 | Iwata et al. | Nov 2007 | A1 |
| 20070266037 | Terry et al. | Nov 2007 | A1 |
| 20070266196 | Torii | Nov 2007 | A1 |
| 20070266219 | Hsieh et al. | Nov 2007 | A1 |
| 20070266276 | Gatzemeier et al. | Nov 2007 | A1 |
| 20070268754 | Lee et al. | Nov 2007 | A1 |
| 20070271468 | McKenney et al. | Nov 2007 | A1 |
| 20070271572 | Gupta et al. | Nov 2007 | A1 |
| 20070274150 | Gorobets | Nov 2007 | A1 |
| 20070276897 | Tameshige et al. | Nov 2007 | A1 |
| 20070276994 | Caulkins et al. | Nov 2007 | A1 |
| 20070283357 | Jeter et al. | Dec 2007 | A1 |
| 20070294474 | Panabaker et al. | Dec 2007 | A1 |
| 20070300008 | Rogers et al. | Dec 2007 | A1 |
| 20070300009 | Rogers et al. | Dec 2007 | A1 |
| 20080005220 | Tsunakawa et al. | Jan 2008 | A1 |
| 20080005222 | Lambert et al. | Jan 2008 | A1 |
| 20080005446 | Frantz et al. | Jan 2008 | A1 |
| 20080005465 | Matthews | Jan 2008 | A1 |
| 20080005468 | Faibish et al. | Jan 2008 | A1 |
| 20080005748 | Mathew et al. | Jan 2008 | A1 |
| 20080010395 | Mylly et al. | Jan 2008 | A1 |
| 20080010580 | Anderson et al. | Jan 2008 | A1 |
| 20080016294 | Hillier, III et al. | Jan 2008 | A1 |
| 20080016301 | Chen | Jan 2008 | A1 |
| 20080022187 | Bains | Jan 2008 | A1 |
| 20080025126 | Jewell et al. | Jan 2008 | A1 |
| 20080028058 | Shaw et al. | Jan 2008 | A1 |
| 20080031030 | Rajan et al. | Feb 2008 | A1 |
| 20080034153 | Lee et al. | Feb 2008 | A1 |
| 20080034259 | Ko et al. | Feb 2008 | A1 |
| 20080040522 | Matthews | Feb 2008 | A1 |
| 20080043769 | Hirai | Feb 2008 | A1 |
| 20080046443 | Fachan et al. | Feb 2008 | A1 |
| 20080046737 | Mihm et al. | Feb 2008 | A1 |
| 20080052377 | Light | Feb 2008 | A1 |
| 20080052477 | Lee et al. | Feb 2008 | A1 |
| 20080052483 | Rangarajan et al. | Feb 2008 | A1 |
| 20080052576 | Brandyberry et al. | Feb 2008 | A1 |
| 20080059752 | Serizawa | Mar 2008 | A1 |
| 20080059820 | Vaden et al. | Mar 2008 | A1 |
| 20080065815 | Nasu et al. | Mar 2008 | A1 |
| 20080077767 | Khosravi et al. | Mar 2008 | A1 |
| 20080080243 | Edahiro et al. | Apr 2008 | A1 |
| 20080082724 | Dunlop et al. | Apr 2008 | A1 |
| 20080082736 | Chow et al. | Apr 2008 | A1 |
| 20080082774 | Tomlin et al. | Apr 2008 | A1 |
| 20080086580 | Zhang et al. | Apr 2008 | A1 |
| 20080091876 | Fujibayashi et al. | Apr 2008 | A1 |
| 20080098083 | Shergill et al. | Apr 2008 | A1 |
| 20080098159 | Song et al. | Apr 2008 | A1 |
| 20080104344 | Shimozono et al. | May 2008 | A1 |
| 20080109090 | Esmaili et al. | May 2008 | A1 |
| 20080109647 | Gavens et al. | May 2008 | A1 |
| 20080114962 | Holt | May 2008 | A1 |
| 20080117686 | Yamada | May 2008 | A1 |
| 20080120303 | Selkirk et al. | May 2008 | A1 |
| 20080120469 | Kornegay et al. | May 2008 | A1 |
| 20080120518 | Ritz et al. | May 2008 | A1 |
| 20080123211 | Chng et al. | May 2008 | A1 |
| 20080126507 | Wilkinson | May 2008 | A1 |
| 20080126682 | Zhao et al. | May 2008 | A1 |
| 20080126686 | Sokolov et al. | May 2008 | A1 |
| 20080126700 | El-Bat et al. | May 2008 | A1 |
| 20080126704 | Ulrich et al. | May 2008 | A1 |
| 20080126852 | Brandyberry et al. | May 2008 | A1 |
| 20080133963 | Katano et al. | Jun 2008 | A1 |
| 20080137284 | Flynn et al. | Jun 2008 | A1 |
| 20080137658 | Wang | Jun 2008 | A1 |
| 20080140737 | Garst et al. | Jun 2008 | A1 |
| 20080140819 | Bailey et al. | Jun 2008 | A1 |
| 20080140918 | Sutardja | Jun 2008 | A1 |
| 20080140919 | Torabi et al. | Jun 2008 | A1 |
| 20080141043 | Flynn et al. | Jun 2008 | A1 |
| 20080144826 | Chang | Jun 2008 | A1 |
| 20080155051 | Moshayedi | Jun 2008 | A1 |
| 20080160899 | Henry et al. | Jul 2008 | A1 |
| 20080162590 | Kundu et al. | Jul 2008 | A1 |
| 20080162787 | Tomlin et al. | Jul 2008 | A1 |
| 20080163007 | Shaeffer et al. | Jul 2008 | A1 |
| 20080163220 | Wang et al. | Jul 2008 | A1 |
| 20080183882 | Flynn et al. | Jul 2008 | A1 |
| 20080183965 | Shiga et al. | Jul 2008 | A1 |
| 20080183968 | Huang | Jul 2008 | A1 |
| 20080195798 | Lee et al. | Aug 2008 | A1 |
| 20080195801 | Cheon et al. | Aug 2008 | A1 |
| 20080201535 | Hara | Aug 2008 | A1 |
| 20080205286 | Li et al. | Aug 2008 | A1 |
| 20080209090 | Kano et al. | Aug 2008 | A1 |
| 20080222309 | Shanbhogue | Sep 2008 | A1 |
| 20080228862 | Mackey | Sep 2008 | A1 |
| 20080228992 | Dumitru et al. | Sep 2008 | A1 |
| 20080229045 | Qi | Sep 2008 | A1 |
| 20080229046 | Raciborski | Sep 2008 | A1 |
| 20080229079 | Flynn et al. | Sep 2008 | A1 |
| 20080229381 | Sikka et al. | Sep 2008 | A1 |
| 20080235443 | Chow et al. | Sep 2008 | A1 |
| 20080235528 | Kim et al. | Sep 2008 | A1 |
| 20080243966 | Croisettier et al. | Oct 2008 | A1 |
| 20080244181 | Walz et al. | Oct 2008 | A1 |
| 20080256316 | Evanchik et al. | Oct 2008 | A1 |
| 20080263259 | Sadovsky et al. | Oct 2008 | A1 |
| 20080263305 | Shu et al. | Oct 2008 | A1 |
| 20080263569 | Shu et al. | Oct 2008 | A1 |
| 20080266973 | Sekar et al. | Oct 2008 | A1 |
| 20080270714 | Van Den Bosch | Oct 2008 | A1 |
| 20080276040 | Moritoki | Nov 2008 | A1 |
| 20080282031 | Tanoue | Nov 2008 | A1 |
| 20080288819 | Heller, Jr. | Nov 2008 | A1 |
| 20080294847 | Maruyama et al. | Nov 2008 | A1 |
| 20080301475 | Felter et al. | Dec 2008 | A1 |
| 20080303692 | Hirai | Dec 2008 | A1 |
| 20080307192 | Sinclair et al. | Dec 2008 | A1 |
| 20080313364 | Flynn et al. | Dec 2008 | A1 |
| 20080320209 | Lee et al. | Dec 2008 | A1 |
| 20080320253 | Tomlin et al. | Dec 2008 | A1 |
| 20080320323 | Brittain et al. | Dec 2008 | A1 |
| 20090013056 | Weinstock et al. | Jan 2009 | A1 |
| 20090031072 | Sartore | Jan 2009 | A1 |
| 20090031098 | Sartore | Jan 2009 | A1 |
| 20090037651 | Gorobets | Feb 2009 | A1 |
| 20090037778 | Resnick | Feb 2009 | A1 |
| 20090043952 | Estakhri et al. | Feb 2009 | A1 |
| 20090044078 | Vogan et al. | Feb 2009 | A1 |
| 20090070526 | Tetrick et al. | Mar 2009 | A1 |
| 20090070541 | Yochai | Mar 2009 | A1 |
| 20090083478 | Kunimatsu et al. | Mar 2009 | A1 |
| 20090083485 | Cheng | Mar 2009 | A1 |
| 20090089485 | Yeh | Apr 2009 | A1 |
| 20090089518 | Hobbet et al. | Apr 2009 | A1 |
| 20090091979 | Shalvi | Apr 2009 | A1 |
| 20090091996 | Chen et al. | Apr 2009 | A1 |
| 20090094676 | Burugula et al. | Apr 2009 | A1 |
| 20090100194 | Bhadri et al. | Apr 2009 | A1 |
| 20090106479 | Okin et al. | Apr 2009 | A1 |
| 20090113235 | Selinger | Apr 2009 | A1 |
| 20090125650 | Sebire | May 2009 | A1 |
| 20090125671 | Flynn et al. | May 2009 | A1 |
| 20090125700 | Kisel | May 2009 | A1 |
| 20090132760 | Flynn et al. | May 2009 | A1 |
| 20090141606 | Liu et al. | Jun 2009 | A1 |
| 20090144496 | Kawaguchi | Jun 2009 | A1 |
| 20090144818 | Kumar et al. | Jun 2009 | A1 |
| 20090150599 | Bennett | Jun 2009 | A1 |
| 20090150605 | Flynn et al. | Jun 2009 | A1 |
| 20090150621 | Lee | Jun 2009 | A1 |
| 20090150639 | Ohata | Jun 2009 | A1 |
| 20090150641 | Flynn et al. | Jun 2009 | A1 |
| 20090157956 | Kano | Jun 2009 | A1 |
| 20090157989 | Karam et al. | Jun 2009 | A1 |
| 20090172250 | Allen et al. | Jul 2009 | A1 |
| 20090172253 | Rothman et al. | Jul 2009 | A1 |
| 20090193183 | Kudo et al. | Jul 2009 | A1 |
| 20090204649 | Wong et al. | Aug 2009 | A1 |
| 20090204750 | Estakhri et al. | Aug 2009 | A1 |
| 20090207649 | Tang et al. | Aug 2009 | A1 |
| 20090210636 | Karamcheti et al. | Aug 2009 | A1 |
| 20090216944 | Gill et al. | Aug 2009 | A1 |
| 20090222596 | Flynn et al. | Sep 2009 | A1 |
| 20090228637 | Moon et al. | Sep 2009 | A1 |
| 20090235017 | Estakhri et al. | Sep 2009 | A1 |
| 20090239468 | He et al. | Sep 2009 | A1 |
| 20090240873 | Yu et al. | Sep 2009 | A1 |
| 20090248763 | Rajan et al. | Oct 2009 | A1 |
| 20090248922 | Hinohara et al. | Oct 2009 | A1 |
| 20090276588 | Murase | Nov 2009 | A1 |
| 20090276654 | Butterworth et al. | Nov 2009 | A1 |
| 20090287850 | Furukawa et al. | Nov 2009 | A1 |
| 20090287887 | Matsuki et al. | Nov 2009 | A1 |
| 20090292861 | Kanevsky et al. | Nov 2009 | A1 |
| 20090300277 | Jeddeloh | Dec 2009 | A1 |
| 20090307424 | Galloway et al. | Dec 2009 | A1 |
| 20090313453 | Stefanus et al. | Dec 2009 | A1 |
| 20090327602 | Moore et al. | Dec 2009 | A1 |
| 20090327804 | Moshayedi | Dec 2009 | A1 |
| 20100005228 | Fukutomi et al. | Jan 2010 | A1 |
| 20100005255 | Kaushik et al. | Jan 2010 | A1 |
| 20100011147 | Hummel et al. | Jan 2010 | A1 |
| 20100011150 | Klein | Jan 2010 | A1 |
| 20100017441 | Todd | Jan 2010 | A1 |
| 20100017556 | Chin et al. | Jan 2010 | A1 |
| 20100017568 | Wadhawan et al. | Jan 2010 | A1 |
| 20100023674 | Aviles | Jan 2010 | A1 |
| 20100023676 | Moon et al. | Jan 2010 | A1 |
| 20100023682 | Lee et al. | Jan 2010 | A1 |
| 20100030946 | Kano et al. | Feb 2010 | A1 |
| 20100031000 | Flynn et al. | Feb 2010 | A1 |
| 20100049913 | Marcu et al. | Feb 2010 | A1 |
| 20100070698 | Ungureanu et al. | Mar 2010 | A1 |
| 20100076936 | Rajan | Mar 2010 | A1 |
| 20100077133 | Jeon | Mar 2010 | A1 |
| 20100077194 | Zhao et al. | Mar 2010 | A1 |
| 20100082529 | Mace et al. | Apr 2010 | A1 |
| 20100082890 | Heo et al. | Apr 2010 | A1 |
| 20100082922 | George et al. | Apr 2010 | A1 |
| 20100091535 | Sommer et al. | Apr 2010 | A1 |
| 20100095059 | Kisley et al. | Apr 2010 | A1 |
| 20100100670 | Jeddeloh | Apr 2010 | A1 |
| 20100102999 | Lee et al. | Apr 2010 | A1 |
| 20100106917 | Ruberg et al. | Apr 2010 | A1 |
| 20100110748 | Best | May 2010 | A1 |
| 20100122017 | Toyama | May 2010 | A1 |
| 20100124123 | Lee | May 2010 | A1 |
| 20100131826 | Shalvi et al. | May 2010 | A1 |
| 20100146187 | Grimsrud et al. | Jun 2010 | A1 |
| 20100153617 | Miroshnichenko et al. | Jun 2010 | A1 |
| 20100153651 | Kushwah | Jun 2010 | A1 |
| 20100153660 | Lasser | Jun 2010 | A1 |
| 20100153680 | Baum et al. | Jun 2010 | A1 |
| 20100169542 | Sinclair | Jul 2010 | A1 |
| 20100174870 | Banerjee | Jul 2010 | A1 |
| 20100180161 | Kern et al. | Jul 2010 | A1 |
| 20100199020 | Lin et al. | Aug 2010 | A1 |
| 20100205231 | Cousins | Aug 2010 | A1 |
| 20100205335 | Phan et al. | Aug 2010 | A1 |
| 20100205368 | Gregg et al. | Aug 2010 | A1 |
| 20100211737 | Flynn et al. | Aug 2010 | A1 |
| 20100217916 | Gao et al. | Aug 2010 | A1 |
| 20100217948 | Mason et al. | Aug 2010 | A1 |
| 20100228936 | Wright et al. | Sep 2010 | A1 |
| 20100229005 | Herman et al. | Sep 2010 | A1 |
| 20100235597 | Arakawa | Sep 2010 | A1 |
| 20100250831 | O'Brien et al. | Sep 2010 | A1 |
| 20100251068 | Lin et al. | Sep 2010 | A1 |
| 20100257304 | Rajan et al. | Oct 2010 | A1 |
| 20100262738 | Swing et al. | Oct 2010 | A1 |
| 20100262740 | Borchers et al. | Oct 2010 | A1 |
| 20100262757 | Sprinkle et al. | Oct 2010 | A1 |
| 20100262758 | Swing et al. | Oct 2010 | A1 |
| 20100262759 | Borchers et al. | Oct 2010 | A1 |
| 20100262760 | Swing et al. | Oct 2010 | A1 |
| 20100262761 | Borchers et al. | Oct 2010 | A1 |
| 20100262762 | Borchers et al. | Oct 2010 | A1 |
| 20100262766 | Sprinkle et al. | Oct 2010 | A1 |
| 20100262767 | Borchers et al. | Oct 2010 | A1 |
| 20100262773 | Borchers et al. | Oct 2010 | A1 |
| 20100262894 | Swing et al. | Oct 2010 | A1 |
| 20100262979 | Borchers et al. | Oct 2010 | A1 |
| 20100268869 | Roh et al. | Oct 2010 | A1 |
| 20100268974 | Floyd et al. | Oct 2010 | A1 |
| 20100269542 | Nishiura et al. | Oct 2010 | A1 |
| 20100281207 | Miller et al. | Nov 2010 | A1 |
| 20100287347 | Cameron et al. | Nov 2010 | A1 |
| 20100293348 | Ye et al. | Nov 2010 | A1 |
| 20100318744 | Benhase et al. | Dec 2010 | A1 |
| 20100332871 | Allalouf et al. | Dec 2010 | A1 |
| 20100332897 | Wilson | Dec 2010 | A1 |
| 20110004722 | Jeddeloh | Jan 2011 | A1 |
| 20110016260 | Lomelino et al. | Jan 2011 | A1 |
| 20110022819 | Post et al. | Jan 2011 | A1 |
| 20110029728 | Popovski et al. | Feb 2011 | A1 |
| 20110035562 | Gaither | Feb 2011 | A1 |
| 20110047437 | Flynn | Feb 2011 | A1 |
| 20110055458 | Kuehne | Mar 2011 | A1 |
| 20110060861 | Warren | Mar 2011 | A1 |
| 20110066792 | Shaeffer et al. | Mar 2011 | A1 |
| 20110072207 | Jin et al. | Mar 2011 | A1 |
| 20110078415 | Johnson et al. | Mar 2011 | A1 |
| 20110093687 | Chen et al. | Apr 2011 | A1 |
| 20110099323 | Syu | Apr 2011 | A1 |
| 20110119441 | Peake et al. | May 2011 | A1 |
| 20110119446 | Blumrich et al. | May 2011 | A1 |
| 20110126045 | Bennett | May 2011 | A1 |
| 20110131231 | Haas et al. | Jun 2011 | A1 |
| 20110182119 | Strasser et al. | Jul 2011 | A1 |
| 20110191534 | Ash et al. | Aug 2011 | A1 |
| 20110208911 | Taguchi et al. | Aug 2011 | A1 |
| 20110208915 | Bannon et al. | Aug 2011 | A1 |
| 20110209028 | Post et al. | Aug 2011 | A1 |
| 20110214011 | Grube et al. | Sep 2011 | A1 |
| 20110219169 | Zhang et al. | Sep 2011 | A1 |
| 20110225347 | Goss et al. | Sep 2011 | A1 |
| 20110225364 | Edwards | Sep 2011 | A1 |
| 20110240749 | Naddor | Oct 2011 | A1 |
| 20110258391 | Atkisson et al. | Oct 2011 | A1 |
| 20110258512 | Flynn et al. | Oct 2011 | A1 |
| 20110295969 | Bernstein et al. | Dec 2011 | A1 |
| 20110296133 | Flynn et al. | Dec 2011 | A1 |
| 20110314071 | Johnson et al. | Dec 2011 | A1 |
| 20110320733 | Sanford et al. | Dec 2011 | A1 |
| 20120011340 | Flynn et al. | Jan 2012 | A1 |
| 20120030408 | Flynn et al. | Feb 2012 | A1 |
| 20120036309 | Dillow et al. | Feb 2012 | A1 |
| 20120041992 | Sutardja | Feb 2012 | A1 |
| 20120042224 | Wu et al. | Feb 2012 | A1 |
| 20120059978 | Rosenband et al. | Mar 2012 | A1 |
| 20120084489 | Gorobets et al. | Apr 2012 | A1 |
| 20120096217 | Son et al. | Apr 2012 | A1 |
| 20120102298 | Sengupta et al. | Apr 2012 | A1 |
| 20120110108 | Li et al. | May 2012 | A1 |
| 20120117304 | Worthington et al. | May 2012 | A1 |
| 20120124315 | Wang | May 2012 | A1 |
| 20120151118 | Flynn et al. | Jun 2012 | A1 |
| 20120191667 | Kopylovitz et al. | Jul 2012 | A1 |
| 20120203980 | Flynn et al. | Aug 2012 | A1 |
| 20120239860 | Atkisson et al. | Sep 2012 | A1 |
| 20120239868 | Ryan et al. | Sep 2012 | A1 |
| 20120254515 | Melik-Martirosian et al. | Oct 2012 | A1 |
| 20120297140 | Wu et al. | Nov 2012 | A1 |
| 20120320209 | Vico et al. | Dec 2012 | A1 |
| 20120331206 | Flynn et al. | Dec 2012 | A1 |
| 20130166820 | Batwara et al. | Jun 2013 | A1 |
| 20130166829 | Dumitru et al. | Jun 2013 | A1 |
| 20130166855 | Batwara et al. | Jun 2013 | A1 |
| 20130173997 | Suzumura et al. | Jul 2013 | A1 |
| 20130191705 | Watanabe et al. | Jul 2013 | A1 |
| 20140215175 | Kasorla et al. | Jul 2014 | A1 |
| 20140365707 | Talagala et al. | Dec 2014 | A1 |
| 20140372679 | Flynn et al. | Dec 2014 | A1 |
| 20150248922 | Hyun et al. | Sep 2015 | A1 |
| 20150268864 | Bernat et al. | Sep 2015 | A1 |
| 20160018991 | Flynn et al. | Jan 2016 | A1 |
| Number | Date | Country |
|---|---|---|
| 1340760 | Mar 2002 | CN |
| 1619509 | May 2005 | CN |
| 1632765 | Jun 2005 | CN |
| 1771495 | May 2006 | CN |
| 101266829 | Sep 2008 | CN |
| 0747822 | Dec 1996 | EP |
| 0747822 | Apr 1997 | EP |
| 1100001 | May 2001 | EP |
| 0747822 | Oct 2001 | EP |
| 1280047 | Jan 2003 | EP |
| 1418502 | May 2004 | EP |
| 1594064 | Nov 2005 | EP |
| 1607868 | Dec 2005 | EP |
| 1814039 | Aug 2007 | EP |
| 1871040 | Dec 2007 | EP |
| 1814039 | Mar 2009 | EP |
| 123416 | Sep 2001 | GB |
| 2431750 | May 2007 | GB |
| H04242848 | Aug 1992 | JP |
| H08153014 | Jun 1996 | JP |
| H096706 | Jan 1997 | JP |
| H09198336 | Jul 1997 | JP |
| H10301719 | Nov 1998 | JP |
| H10320270 | Dec 1998 | JP |
| 2000259525 | Sep 2000 | JP |
| 2001296974 | Oct 2001 | JP |
| 2004086295 | Mar 2004 | JP |
| 4242848 | Mar 2009 | JP |
| 2009122850 | Jun 2009 | JP |
| 20000026300 | May 2000 | KR |
| 20010034476 | Apr 2001 | KR |
| 20050024278 | Mar 2005 | KR |
| 20060107728 | Oct 2006 | KR |
| 20100022811 | Mar 2010 | KR |
| 200825696 | Jun 2008 | TW |
| WO-9419746 | Sep 1994 | WO |
| WO-9518407 | Jul 1995 | WO |
| WO-9612225 | Apr 1996 | WO |
| WO-9828684 | Jul 1998 | WO |
| WO-9828685 | Jul 1998 | WO |
| WO-9829684 | Jul 1998 | WO |
| WO-0131512 | May 2001 | WO |
| WO-0201365 | Jan 2002 | WO |
| WO-0205611 | Jan 2002 | WO |
| WO-02067529 | Aug 2002 | WO |
| WO-2004077219 | Sep 2004 | WO |
| WO-2004099989 | Nov 2004 | WO |
| WO-2005010773 | Feb 2005 | WO |
| WO-2005103878 | Nov 2005 | WO |
| WO-2006050455 | May 2006 | WO |
| WO-2006062511 | Jun 2006 | WO |
| WO-2006065626 | Jun 2006 | WO |
| WO-2006113334 | Oct 2006 | WO |
| WO-2007132457 | Nov 2007 | WO |
| WO-2008070173 | Jun 2008 | WO |
| WO-2008070796 | Jun 2008 | WO |
| WO-2008070799 | Jun 2008 | WO |
| WO-2008073421 | Jun 2008 | WO |
| WO-2008130799 | Oct 2008 | WO |
| WO-2008070796 | Dec 2009 | WO |
| WO-2010036757 | Apr 2010 | WO |
| WO-2010053756 | May 2010 | WO |
| WO-2011106394 | Sep 2011 | WO |
| WO-2011106394 | Nov 2011 | WO |
| WO-2012050934 | Apr 2012 | WO |
| WO-2012082792 | Jun 2012 | WO |
| Entry |
|---|
| Application No. PCT/US2007/025188, International Preliminary Report on Patentability, dated Feb. 3, 2009. |
| U.S. Appl. No. 11/952,123, Notice of Allowance, dated May 5, 2011. |
| Application No. PCT/US2007/025049, International Preliminary Reporton Patentability, dated Mar. 11, 2009, 12 pages. |
| Application No. 200980121161.3, Office Action, dated Nov. 30, 2012. |
| Notice of Allowance, U.S. Appl. No. 12/098,435, dated Feb. 17, 2010. |
| Notice of Allowance, U.S. Appl. No. 12/098,435, dated Jul. 8, 2010. |
| Final Office Action, U.S. Appl. No. 13/456,119, dated Nov. 4, 2014. |
| Notice of Allowance, U.S. Appl. No. 13/456,119, dated Feb. 20, 2015. |
| Notice of Allowance, U.S. Appl. No. 13/456,119, dated Jun. 10, 2015. |
| Office Action, EP Application No. 09730535.3; dated Dec. 3, 2010. |
| First Office Action, CN Application No. 200780050974.9; dated Aug. 11, 2011. |
| U.S. Appl. No. 12/098,427, Office Action received from USPTO, dated Aug. 5, 2011. |
| Office Action, U.S. Appl. No. 12/098,431, dated Aug. 10, 2011. |
| U.S. Appl. No. 13/442,638, Notice of Allowance, dated Nov. 13, 2012. |
| U.S. Appl. No. 13/442,638, Office Action dated Jul. 2, 2012. |
| U.S. Appl. No. 12/467,914, Office Action, dated Oct. 14, 2011. |
| PCT/US2010/048320, International Search Report and Written Opinion, dated Apr. 28, 2011. |
| Application No. 07865334.2, Office Action, dated Nov. 23, 2012. |
| Office Action, U.S. Appl. No. 13/174,449, dated Sep. 6, 2011. |
| Office Action, CN Application No. 200780050969.8, dated Nov. 11, 2010. |
| Office Action, EP Application No. 07865335.9, dated Nov. 18, 2010. |
| U.S. Appl. No. 11/952,106, Final Office Action, dated Aug. 30, 2012. |
| U.S. Appl. No. 11/952,106, Notice of Allowance, dated Mar. 21, 2013. |
| U.S. Appl. No. 11/952,106, Office Action, dated Dec. 20, 2011. |
| U.S. Appl. No. 11/952,106, Office Action, dated Jan. 25, 2011. |
| U.S. Appl. No. 11/952,106, Office Action, dated Sep. 7, 2011. |
| Application No. PCT/US2012/023373, International Search Report and Written Opinion, dated Jul. 30, 2012, 8 pages. |
| Application No. 200780050989.5, China Second Office Action, dated Dec. 19, 2011. |
| Notice of Allowance, U.S. Appl. No. 12/900,336, dated Jun. 16, 2011. |
| Office Action, U.S. Appl. No. 12/900,336, dated Jan. 13, 2011. |
| Office Action, U.S. Appl. No. 11/952,112, dated Mar. 5, 2010. |
| Office Action, EP Application No. 07865345.8, dated Nov. 17, 2010. |
| U.S. Appl. No. 13/784,705, Office Action, dated May 22, 2015. |
| Office Action, U.S. Appl. No. 11/952,095, dated Apr. 22, 2015. |
| U.S. Appl. No. 13/296,834, Final OfficeAction, dated Jun. 18, 2015. |
| “Actel fusion FPGAs supporting Intelligent Peripheral Management Interface (IPMI) Applications,” Application Note, Oct. 1, 2006, Actel Corporation, pp. 1-17. |
| Adaptec, “Understanding Read and Write Caching,” http://ask.adaptec.com/app/answers/detail/a.sub.--id/2046/.about./und- erstanding-read-and-write-caching, 2 pgs. Published Mar. 12, 2001. |
| “Adaptive Replacement Cache”, Wikipedia, last modified Apr. 2010, pp. 3, http://en.wikipedia.org/wiki/Adaptive.sub.--replacement-cache. |
| “Agiga Tech Introduction”, Agigaram, San Diego, California, US, Mar. 7, 2013. |
| AgigaRAM Company, Technology Review, Feb. 2008, p. 1, reviewed Feb. 17, 2010. |
| Agigatech, “Bulletproof Memory for RAID Servers, Parts 1-3,” http://agigatech.com/blog/bulletproof-memory-for-raid-servers-part-1/, Nov. 12, 2009, visited Jan. 5, 2011. |
| Agrawal et al. “ECC and Signal Processing Technology for Solid State Drives and Multi-bit per cell NAND Flash Memories” Forward Insights, Report No. FI-NFL-FSP-0110, (Jan. 2010), 174 pages. |
| Ajanovic, Jasmin, “PCI Express* (PCIe*) 3.0 Accelerator Features”, Intel Corporation, pp. 10, Mar. 7, 2013. |
| “Am29DL322D/323D/324D Data Sheet”, Spansion, Oct. 7, 2004, pp. 57, XP-002476181, Publication No. 21534, Revision #, Amendment #7. |
| Application No. 10816110.0, Extended European Search Report, dated Jun. 3, 2013, 9 pages. |
| Application No. PCT/US2007/025048, International Preliminary Reporton Patentability, dated Jun. 18, 2009, 8 pages. |
| Application No. 10816043.3, Extended European Search Report, dated Jun. 21, 2013, 6 pages. |
| Application No. 07865334.2, Examination Report, dated Jan. 30, 2012. |
| Application No. 07865334.2, Office Action, dated Nov. 17, 2010. |
| Application No. 07865334.2, Summons, Aug. 17, 2012. |
| Application No. 07865345.8, Examination Report, dated Jan. 30, 2012. |
| Application No. 07867661.6, Office Action, dated Oct. 6, 2011. |
| Application No. 09731243.3, Examination Report, dated May 25, 2012. |
| Application No. 10816108.4, Office Action, dated Sep. 30, 2015. |
| Application No. 10816108.4, PCT/U.S. Pat. No. 2010048321, Search Report, dated Feb. 4, 2014. |
| Application No. 10816108.4, Search Report, dated Apr. 2, 2014. |
| Application No. 11848174.6, Examination Report, dated Jun. 30, 2015. |
| Application No. 11848174.6, Search Report, dated Apr. 2, 2014. |
| Application No. 12176826.1, Search Report, dated Dec. 10, 2012. |
| U.S. Appl. No. 12/877,971, Office Action, dated Apr. 18, 2013. |
| U.S. Appl. No. 13/088,211, Notice of Allowance, dated May 29, 2015. |
| Application No. 200780050969.8, Office Action, dated Jul. 6, 2011. |
| Application No. 200780050969.8, Office Action, dated Nov. 7. 2011. |
| Application No. 200780050972.X, Office Action, dated Sep. 26, 2011. |
| Application No. 200780050972.X, Second Office Action, dated Jul. 5, 2012. |
| Application No. 200780050974.9, Office Action, dated Jul. 27, 2011. |
| Application No. 200780050974.9, Office Action, dated May 23, 2012. |
| Application No. 200780050989.5, Office Action, dated Jul. 20, 2012. |
| Application No. 200780051010.6, First Office Action, dated Nov. 17, 2011. |
| Application No. 200780051010.6, Second Office Action, dated Aug. 1, 2012. |
| Application No. 200780051027.1, Office Action, dated Apr. 23, 2013. |
| Application No. 200780051027.1, Office Action, dated Feb. 16, 2012. |
| Application No. 200780051034, Office Action, dated Nov. 11, 2010. |
| Application No. 200780051034.1, Final Office Action, dated Apr. 28, 2012. |
| Application No. 200780051034.1, Office Action, dated Jul. 6, 2011. |
| Application No. 200780051034.1, Office Action, dated Nov. 8, 2011. |
| Application No. 200980121047.0, Final Office Action, dated Aug. 3, 2012. |
| Application No. 201080050702.0, Office Action, dated Feb. 20, 2014. |
| Application No. 201080050702.0, Second Office Action, dated Sep. 19, 2014. |
| Application No. 2011800598626, Office Action, dated Apr. 1, 2015. |
| Application No. EP11813216, Search Report, dated Nov. 20, 2013. |
| Application No. PCT/US2007/025048, International Search Report and Written Opinion, dated May 27, 2008, 12 pages. |
| Application No. PCT/US2007/025049, International Search Report and Written Opinion, dated May 14, 2008, 13 pages. |
| Application No. PCT/US2007/086683, International Preliminary Reporton Patentability, dated Nov. 5, 2009, 10 pages. |
| Application No. PCT/US2007/086683, International Search Report and Written Opinion, dated Oct. 26, 2009, 14 pages. |
| Application No. PCT/US2007/086686, International Preliminary Reporton Patentability, dated Dec. 16, 2008,12 pages. |
| Application No. PCT/US2007/086686, International Search Report and Written Opinion, dated Apr. 28, 2008, 14 pages. |
| Application No. PCT/US2007/086687, International Preliminary Reporton Patentability, dated Mar. 18, 2009, 15 pages. |
| Application No. PCT/US2007/086688, International Preliminary Reporton Patentability, dated Mar. 16, 2009, 13 pages. |
| Application No. PCT/US2007/086688, International Search Report and Written Opinion, dated Apr. 28, 2008, 13 pages. |
| Application No. PCT/US2007/086691, International Search Report and Written Opinion, dated May 8, 2008, 13 pages. |
| Application No. PCT/US2007/086701, International Preliminary Reporton Patentability, dated Mar. 16, 2009, 15 pages. |
| Application No. PCT/US2007/086701, International Search Report and Written Opinion, dated Jun. 5, 2008, 13 pages. |
| Application No. PCT/US2007/086702, International Preliminary Reporton Patentability, dated Nov. 19, 2009, pp. 10. |
| Application No. PCT/US2007/086702, International Search Report and Written Opinion, dated Nov. 4, 2009. |
| Application No. PCT/US2007/086703, International Search Report and Written Opinion, dated Nov. 9, 2009. |
| Application No. PCT/US2009/039570, International Preliminary Reporton Patentability, dated Oct. 21, 2010, 8 pages. |
| Application No. PCT/US2009/039570, International Search Report and Written Opinion, dated Aug. 7, 2009, 14 pages. |
| Application No. PCT/US2009/039572, International Preliminary Reporton Patentability, dated Oct. 14, 2010, 14 pages. |
| Application No. PCT/US2009/039572, International Search Report and Written Opinion, dated Jul. 30, 2009, 18 pages. |
| Application No. PCT/US2009/039626, International Preliminary Reporton Patentability , dated Oct. 21, 2010, 10 pages. |
| Application No. PCT/US2009/039626, International Search Report and Written Opinion, dated Aug. 27, 2009, 15 pages. |
| Application No. PCT/US2009/039673, International Preliminary Report on Patentability, dated Oct. 21, 2010, 10 pages. |
| Application No. PCT/US2009/039673, International Search Report and Written Opinion, dated Jul. 6, 2009. |
| Application No. PCT/US2010/048321, International Search Report and Written Opinion, dated Apr. 28, 2011, 10 pages. |
| Application No. PCT/US2010/048325, International Preliminary Reporton Patentability, dated Mar. 13, 2012, 4 pages. |
| Application No. PCT/US2011/025885, International Preliminary Reporton Patentability, dated Sep. 7, 2012, 8 pages. |
| Application No. PCT/US2011/045801, International Search Report and Written Opinion dated Apr. 6, 2012. |
| Application No. PCT/US2011/046005, International Search Report and Written Opinion, dated Apr. 6, 2012, 8 pages. |
| Application No. PCT/US2011/047659, International Preliminary Reporton Patentability, dated Feb. 21, 2013, 5 pages. |
| Application No. PCT/US2011/047659, International Search Report and Written Opinion, dated Apr. 9, 2012, 8 pages. |
| Application No. PCT/US2011/053792, International Preliminary Reporton Patentability, dated Apr. 2, 2013. |
| Application No. PCT/US2011/053792, International Search Report, dated May 4, 2012. |
| Application No. PCT/US2011/053792, Written Opinion, dated May 4, 2012. |
| Application No. PCT/US2011/053795, International Search Report and Written Opinion, dated May 4, 2012. |
| Application No. PCT/US2011/065927, International Preliminary Reporton Patentability, dated Jun. 18, 2013, 4 pages. |
| Application No. PCT/US2012/021094, International Search Report, dated Sep. 24, 2012, 12 pages. |
| Application No. PCT/US2012/024927, International Preliminary Report on Patentability and Written Opinion, dated Aug. 13, 2013. |
| Application No. PCT/US2012/024927, International Search Report, dated Oct. 12, 2012. |
| Application No. PCT/US2012/024927, Written Opinion, dated Oct. 12, 2012. |
| Application No. PCT/US2012/026790, International Preliminary Report on Patentability, dated Sep. 6, 2013, 8 pages. |
| Application No. PCT/US2012/026790, International Search Report and Written Opinion,dated Dec. 27, 2012, 11 pages. |
| Application No. PCT/US2014/048129, International Search Report and Written Opinion, dated Nov. 7, 2014. |
| Ari Gottwals, Henze, “Performance Boosting and Workload Isolation in Storage Area Networks with SanCache”, Hewlett Packard Laboratories, Proceedings of the 23rd IEEE/14th NASA Goddard Conference on Mass Storage Systems and Technologies (MSST 2006) May 2006, pp. 263-227. |
| Arie Tai, NAND vs. NOR flash technology, Feb. 1, 2002, M-Systems, pp. 1-4, retrived fromhttp://www2.electronicproducts.com/NAND vs_NOR_flash_technology-article-FEBMSY1-feb2002-html.aspx on Nov. 10, 2010. |
| Arpaci-Dusseau, Andrea C., “Removing the Costs of Indirection in Flash-based SSDs with Nameless Writes”, HotStorage, Jun. 2010, p. 5. |
| ASPMC.sub.--660 Rugged IDE Flash Disk PMC Module, Asine Group, http://www.asinegroup.com/products/aspmc660.html, copyright 2002, 3 pages. [Retrieved Nov. 18, 2009]. |
| Atsuo Kawaguchi, Shingo Nishioka, Hiroshi Motoda, A Flash-Memory Based File System, Advanced Research Laboratory, Hitachi, Ltd., Japan, 1995. |
| AW Object Request Broker, AutomatWeb's technology, Jun. 7, 2007, available at http://www.struktuur.ee/188000 (last visited on Mar. 11, 2010). |
| Bad Block Management in NAND Flash Memories, AN1819 Application Note, May 19, 2004, downloaded from www.datasheetarchive.com on Jul. 2, 2009. |
| Bandulet, Christian, “Object-Based Storage Devices”, Sun Developer Network, Jul. 2007, pp. 7, http://developers.xun/com/solaris/articles/osd.html. |
| Bandulet, Christian, “The Evolution of File Systems”, Sun Microsystems, 2009, p. 24, SNIA Education. |
| Barral et al., U.S. Appl. No. 60/625,495, “Dynamically Expandable and Contractible Fault-Tolerant Storage System Permitting Variously Sized Storage Devices and Method,” filed Nov. 5, 2004. |
| Barral et al., U.S. Appl. No. 60/718,768, “Dynamically Adaptable Fault-Tolerant Storage System,” filed Sep. 20, 2005. |
| Batwara, et al., Non-Final Office Action dated May 21, 2015 for U.S. Appl. No. 13/725,728. |
| Batwara, et al., Notice of Allowance dated Oct. 19, 2015 for U.S. Appl. No. 13/725,728. |
| Benjauthrit, B.; Coady, L.; Trcka, M.;, “An overview of error control codes for data storage,” Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, vol. No., pp. 120-126, Jun. 24-26, 1996. |
| Bhaniramka et al., “OpenGI Multipipe Sdk: A Toolkit for Scalable Parallel Rendering”, 2005. |
| Bitmicro Introduces E-Disk PMC Flash Disk Module at Military & Aerospace Electronics East, May 18, 2004, BiTMICRO, http://www.bitmicro.sub.--com/press.sub.-news.sub.--releases.sub.--20040--518.sub.--prt.php. |
| Bonnet, “Flash Device Support for Database Management,” published Jan. 9, 2011. |
| Brandon Jr.,Daniel et al., Sparse Matrices in CS Education, Christian Brothers University, 650 East Parkway South, Memphis, Tennessee 38104, 2009, pp. 93-98, May 2009. |
| Cardarilli, et al., “Design of fault-tolerant solid state mass memory”, Defect and Fault Tolerance in VLSI Systems, 1999, DFT 1999, International Symposium, vol. No. pp. 302-310, Nov. 1999. |
| Casey “San Cache: SSDin the SAN” storageinc, Mar. 2000. |
| Casey, “Disk I/O Performance Scaling: the File Caching Solution”, Solid Data Systems, Inc., Paper #528, Mar. 2001, pp. 1-8. |
| Casey, Michael, “SAN Cash: SSD in the SAN,” Computer Technology Review's Storage Inc., Quarter 1, Mar. 200, 4 pages. |
| Casey, Michael, “Solid State File-Caching for Performance and Scalability”, Solidata, downloaded Jan. 5, 2011, pp. 5, http://www.storagesearch.com/3dram.html. |
| Casey, “Solid State File-Caching for Performance and Scalability,” Solid Data Quarter 1 2000, http://www/storagesearch. com/3dram.html, visited May 20, 2011. |
| Casey, Solid State File-Caching for Performance and Scalability, SolidData, Mar. 2001, http://www.storagesearch.com/3dramhtml. |
| Chao, Chia, et al. Mime: a high performance parallel storage device with strong recovery guarantees. Technical Report HPL-CSP-92-9, Hewlett-Packard Laboratories, 1992. |
| Chen, “Hystor: Making SSDs the Survival of the Fittest in High Performance Storage Systems”, Proceedings of 25th ACM International Conference on Supercomputing (ICS 2011), Tucson, Arizona, May 31-Jun. 4, 2011. |
| Chinese OfficeAction for U.S. Appl. No. 11/952,095.1 CN filing of this U.S. Appl. No. 11/952,095, dated Feb. 1, 2011. |
| Cipo, “Office Action for CN Application No. 200780050973.4”, dated Jan. 26, 2011. |
| Coburn, Joel, “From ARIES to MARS: Reengineering Transaction Management for Next-Generation. Solid-State Drives” UCSD CSE Technical Report, downloaded Jul. 11, 2013, p. 17, San Diego, California, US. |
| Coburn, Joel, “NV-Heaps: Making Persistent Objects Fast and Safe with Next-Generation, Non-Volatile Memories”, University of California San Diego, 2011, pp. 13, ACM 978-1-4503-0266. Jan. 11, 2003, Newport Beach, California, US. |
| Condit, Jeremy, “Better I/O Through Byte-Addressable, Persistent Memory”, Microsoft Research, UCLA, Oct. 11-14, 2009, pp. 14, ACM 978-1-60558-752—Mar. 9, 2010, Big Sky, Montana, US. |
| Damian Yerrick, Block Device, http://www.pineight.com/ds/block/, “visited” Mar. 1, 2010. |
| Dan, et al., “Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory,” M-Systems: Flash Disk Pioneers—White Paper, 91-SR-014-02-8L, Rev 1.1, Sep. 2003, pp. 2-13. |
| “Data Management Software (DMS) for AMD Simultaneous Read/Write Flash Memory Devices”, Spansion, Jul. 2003, pp. 10, Technology Background, Publication No. 22274, Revision A, Amendment 0. |
| Datadirect Networks, White Paper: S2A9550 Overview, DataDirect Networks, www.datadirectnet.com, 2007, 17 pages. |
| “Datadirect Storage Systems Selected for NCSA Cluster”, High Performance Computing, Aug. 15, 2003, pp. 2, vol. 12, No. 32, http://www.hpcwire/com/hpcwire/hpewireWWW/03/0815/105731.html. |
| David Morgenstern, “Is there a Flash Memory RAID in your Future?”, Nov. 8, 2006, http://www.eweek.com-eWeek, Ziff Davis Enterprise Holdings Inc., 4 pages. [Retrieved Mar. 18, 2010]. |
| David Woodhouse, Red Hat, Inc., JFFS: The Journaling Flash File System, Linux Symposium Jul. 2001 http://sourceware.org/jffs2/jffs2/pdf, “visited” Jun. 11, 2010. |
| ECC Algorithm, The Leader in Memory Technology, Samsung Electronics, Mar. 2005, http://www.samsung.com/global/business/semiconductor/productslftash-/FlashApplicationNote.html. |
| “ECC and Signal Processing Technology for Solid State Drives and Multi-bit per cell NAND Flash Memories”, Forward Insights, 2012, pp. 21, 2nd Edition, Report No. FI-NFL-FSP-0112. |
| “EEL-6892-Virtual Computers”, Lecture 18, downloaded Mar. 1, 2010, http://www.acis.ufl.edu/ming/lectures. |
| ELNEC, NAND Flash Memories and Programming NAND Flash Memories Using ELNEC Device Programmers, Application Note, Mar. 2007, pp. 1-32. |
| “EMC Virtual Infrastructure for Microsoft Applications—Data Center Solution Enabled by EMC Symmetrix V-Max and VMware ESC 3.5”, White Paper, EMC, Apr. 2009, pp. 30. |
| Eric Van Hensbergen, “Dynamic Policy Disk Caching for Storage Networking,” IBM Research Repor—RC24123 (W0611-189), Nov. 28, 2006, 13 pages. |
| Feresten, Paul, “NETAPP Thin Provisioning: Better for Business”, NETAPP White Paper, Network Appliance, Inc., Mar. 2007, WP-7017-0307,p p. 11. |
| “File Level Caching”, ADABAS Caching Facility, May 11, 2004, pp. 9. |
| “File System Primer”, CoolSolutionsWiki, downloaded Oct. 18, 2006, pp. 5, http://wiki.novell.com/index.php/ File.sub.--System.sub.--Primer. |
| Final Office Action for U.S. Appl. No. 13/539,235, filed Jun. 29, 2012, and mailed from the USPTO dated Nov. 9, 2015, 20 pgs. |
| Final Office Action, U.S. Appl. No. 11/952,109, filed Nov. 29, 2011. |
| Final Office Action, U.S. Appl. No. 14/866,461, dated Mar. 24, 2016. |
| “Finding the Perfect Memory”, Agiga Tech, White Paper, Sep. 3, 2009, pp. 15, Poway, California, US. |
| Flynn, et al., Final Office Action dated May 31, 2016 for U.S. Appl. No. 13/837,628. |
| Flynn, et al., Final Office Action dated Nov. 26, 2014 for U.S. Appl. No. 14/087,297. |
| Flynn, et al., Final Office Action dated Nov. 28, 2016 for U.S. Appl. No. 13/193,559. |
| Flynn, et al., Non-Final Office Action dated Aug. 14, 2014 for U.S. Appl. No. 14/087,297. |
| Flynn, et al., Non-Final Office Action dated Jan. 12, 2017 for U.S. Appl. No. 13/837,628. |
| Flynn, et al., Non-Final Office Action Dated Mar. 11, 2015 for U.S. Appl. No. 14/087,297. |
| Flynn, et al., Non-Final Office Action dated Mar. 18, 2016 for U.S. Appl. No. 13/193,559. |
| Flynn, et al., Non-Final Office Action dated Oct. 19, 2015 for U.S. Appl. No. 13/837,628. |
| Flynn, et al., Notice of Allowance dated Oct. 25, 2017 for U.S. Appl. No. 13/837,628. |
| Flynn, et al., Office Action dated Aug. 31, 2017 for U.S. Appl. No. 13/193,559. |
| Flynn, et al., Office Action dated Jul. 25, 2017 for U.S. Appl. No. 14/994,452. |
| Flynn,David et al., Final OfficeAction dated Sep. 16, 2016 for U.S. Appl. No. 14/309,751. |
| Flynn,David et al., Notice of Allowance dated Dec. 5, 2016 for U.S. Appl. No. 14/309,751. |
| Friedman, Mark, “File Cache Performance and Tuning,” http://msdn.microsoft.com/en-us/library/bb742613.aspx, published Jan. 2002. |
| Gal, Eran, et al., “A Transactional Flash File System for Microcontrollers,” School of Computer Science, Tel-Aviv University, USENIX Association, 2005 USENIX Annual Technical Conference, pp. 89-104. |
| Ganger, Gregory R., et al. “Soft updates: a solution to the metadata update problem in file systems.” ACM Transactions on Computer Systems (TOCS)18.2 (2000): 127-153. |
| Garfinkel, One Big File Is Not Enough: A Critical Evaluation of the Dominant Free-Space Sanitization Technique, 2006, pp. 135-151. |
| Gill, Binny S., “STOW: Spatially and Temporally Optimized Write Caching Algorithm”, IBM Almaden Research Center, 2009, pp. 21, http://www.usenix.org/event/usenix09/tech/slides/gill.pdf. |
| Gill, “WOW: Wise Ordering for Writes—Combining Spatial and Temporal Locality in Non-Volatile Caches”, IBM, Fast '05: 4th USENIX Conference on File and Storage Technologies, 2005. |
| Guerra Jorge, “Software Persistent Memory”, Florida International University, downloaded Jul. 11, 2013, pp. 13. |
| Han-joan Kim, Sang-goo Lee; “A New Flash Memory Management for Flash Storage System”; 1999; IEEE; pp. 284-289 (Year: 1999). |
| Hauck et al., “Abstract: Runlength Compression Techniques for FPGA Configurations”. |
| “High Speed, Elevated Board Stacking”, Samtec, 2007, pp. 1. |
| “How NTFS Works”, Updated Mar. 28, 2003, p. 34, http://technet.microsoff.com/en-us/library/cc781134(WS.10).aspx. |
| Huffman, “Non-Volatile Memory Host Controller Interface,” Apr. 14, 2008, 65 pgs. |
| Hutsell, Woody, “An In-depth Look at the RamSan-500 Cached Flash Solid State Disk”, Texas Memory Systems, White Paper, Mar. 2008, pp. 16. |
| “Hynix 48-GB Flash MCP”, Barracuda Networks, Sep. 6, 2007, pp. 21, http://hardware.slashdot.org/story/07/09/06/146218/hynix-48-GB-flash.mcp. |
| Hynix Semiconductor, Intel Corporation, Micron Technology, Inc. Phison Electronics Corp., Sony Corporation, Spansion, Stmicroelectronics, “Open NAND Flash Interface Specification,” Revision 2.0, Feb. 27, 2008. |
| Hynix Semiconductor, Intel Corporation, Micron Technology, Inc. Phison Electronics Corp., Sony Corporation, Spansion, STMicroelectronics, “Open NAND Flash Interface Specification,” Revision 2.1, Jan. 14, 2009. |
| “Hystor: Making SSDs the ‘Survival of the Fittest’ in High-Performance Storage Systems”, Feb. 2010, pp. 14. |
| IBM, “Method to Improve Reliability of SSD Arrays”, ip.com PriorArtDatabase Technical Disclosure, Nov. 5, 2009, pp. 6, IPCOM000189338D, www.ip.com. |
| IEEE Dictionary, “Atomic transaction,” 7th edition, Published in 2000, Last updated Feb. 27, 2007. |
| Information Technology, “SCSI Object-Based Storage Device Commands,” 2 (OSD-2), Project T10/1729-D, Revision 4, published Jul. 30, 2004, printed Jul. 24, 2008. |
| “Intel Turbo Memory with User Pinning”, Intel NAND Storage Solutions, 2008, pp. 4, www.intel.com/go/nand. |
| International Preliminary Report in Application No. PCT/US2010/048174 dated Mar. 22, 2012, 6 pages. |
| International Preliminary Report in Application No. PCT/US2010/048320, dated Mar. 22, 2012, 6 pages. |
| International Preliminary Report in Application No. PCT/US2010/048321, dated Mar. 22, 2012, 7 pages. |
| International Preliminary Report in Application No. PCT/US2011/045801 dated Feb. 14, 2013, 5 pages. |
| International Preliminary Report in Application No. PCT/US2012/022244 dated Aug. 1, 2013, 5 pages. |
| International Search Report and Written Opinion in Application No. PCT/US2010/048174 dated Apr. 29, 2011, 7 pages. |
| International Search Report and Written Opinion in Application No. PCT/US2011/036539 dated Jan. 2, 2012, 6 pages. |
| International Bureau, International Reporton Patentability for PCT/US2011/036539, dated Nov. 22, 2012. |
| International Preliminary Report in Application No. PCT/US2007/086690 dated Mar. 11, 2009, 12 pages. |
| International Preliminary Report in Application No. PCT/US2007/086703 dated Nov. 19, 2009, 10 pages. |
| International Preliminary Report in Application No. PCT/US2007/086705 dated Dec. 10, 2009, 10 pages. |
| International Preliminary Report in Application No. PCT/US2011/045801 dated Feb. 7, 2013, 6 pages. |
| International Search Report and Written Opinion in Application No. PCT/US2007/086690 dated Aug. 7, 2008, 8 pages. |
| International Search Report and Written Opinion in Application No. PCT/US2007/086705 dated Nov. 16, 2009, 15 pages. |
| “Internet Backbone and Colocation Provider”, Hurricane Electric Internet Services, downloaded Sep. 28, 2011, pp. 1, Fremont, California, US. |
| “Introducing Box Hill's Fibre Box”, Fibre Channel News, Jan. 16, 1997, p. 5, http://hsi.web.cern.ch/HSI/fcs/news/jandec97.htm. |
| Introduction to Samsung's Linux Flash File System—RFS: Application Note, Version 1.0 Samsung Electronics, Nov. 2006, 6 pages. |
| “ioDrive—Frequently Asked Questions”, Clustered Storage Solutions: Products, downloaded Feb. 16, 2010, pp. 2, http://www.clusteredstorage.com/clustered.sub.--storage.sub.--solutions.html. |
| Jagmohan, “Write Amplification Reduction in NAND Flash through Multi-Write Coding”, .COPYRGT.2010, IBM T.J. Watson Research Center. |
| James S. Plank, “A Tutorial on Reed-Solomon coding for Fault Tolerance in RAID-like Systems,” Technical Report CS-96-332, Department of Computer Science, Univ. of Tennessee, Sep. 1997, 19 pages. |
| John Ayer et al., “Dynamic Bus Mode Reconfiguration of PCI-X and PCI Designs”, Mar. 2007. |
| John Makulowich, “Strategies, Players and Emerging Markets,” Washington Technology, Jun. 26, 1997, http://washingtontechnology.com/articles/1997/06/26/strategies-players-an- d-emerging-markets.aspx, 6 pages. [Retrieved Sep. 7, 2010]. |
| Johnson et al., “Single-Event Upset Simulation on an FPGA”, 2002. |
| Johnson, Michael K., “An Introduction to Block Device Drivers”, Jan. 1, 1995, pp. 6. |
| Josephson et al., “DFS: A file system for virtualized flash storage.” ACM Trans. Storage 6, 3, Article 14 (Sep. 2010), 25 pages. |
| “jZip A Free WinZip Alternative”, First JZip by Greg Kowal, 2012. |
| Kazmi, “Non-Transparent Bridging Makes PCI-Express HA Friendly,” PLX Technology, EEtimes.com, Aug. 14, 2003. |
| Kennedy, “Exploiting Redundancy to Speedup Reconfiguration of an FPGA”, 2003. |
| Kim, Jin-Ki, “Low Stress Program and Single Wordline Erase Schemes for NAND Flash Memory”, MOSAID Technologies Incorporated, 2007, pp. 2, Ottawa, Ontario, Canada. |
| Kleiman, S. R., “Vnodes: An Architecture for Multiple File System Types in Sun UNIX”, Sun Microsystems, Jan. 1, 1986, pp. 10. |
| Lattice Semiconductor Corporation, “Parallel Flash Programming and FPGA Configuration”, Aug. 2007. |
| Leventhal, “Flash Storage Memory, Communications of the ACM”, http://arstechnica.com/hardware/news/2009/09/intels-new-flash-tech-to-bri- ng-back-turbo-memory-for-real, ACM, vol. 51, No. 7, pp. 47-51, Jul. 2008. |
| Li, Shu, “Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding”, IEEE Transactions on Very Large Scale Integration Systems, Oct. 2010, p. 9, vol. 18, No. 10. |
| Lottiaux, Renaud, “OpenMosix, OpenSSI and Kerrighed: A Comparative Study”, INRIA Institut National De Recherche en Informatique et en Automatique, Nov. 2004, pp. 23, No. 5399. |
| Macko et al. “Tracking Back References in a Write-Anywhere File System” Proceedings of the 8th USENIX Conference on File and Storage Technologies, (2010), 3 pages. |
| Malventano, Allyn, “DDRdrive Hits the Ground Running-PCI-E RAM-based SSD”, PC Perspective, May 4, 2009, pp. 2, http://www.pcper.com/article.php?aid=704. |
| Matthias Nubling, OMF—an object request broker for the process control application domain, 1999, pp. 126-134, available at http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/6433/17161/00792056-.pdf?arnumber=792056 (last visited on Mar. 11, 2010). |
| Megiddo, Nimrod, “Arc: A Self-Tuning, Low Overhead Replacement Cache”, USENIX Association, Mar. 31-Apr. 2, 2003, pp. 17, Proceedings of FAST '03: 2nd USENIX Conference on File and Storage Technologies, San Francisco, California, US. |
| Mellor, Chris, “New RAM Shunts Data Into Flash in Power Cuts”, The Channel, Oct. 19, 2011, p. 1, http://www.channelregister.co.uk/2011/10/19/viing.sub.--hybrid.sub.--dram- .sub.--nand/. |
| Mesnier, Mike, “Object-based Storage”, IEEE Communications Magazine, Aug. 2003, pp. 7, Storage Area Networking, 0163-6804/03. |
| ‘Method for Fault Tolerance in Nonvolatile Storage’, Ip.com, IPCOM000042269D, Feb. 2005. |
| Michael Burrows et al., On line Data Compression in a Log Structured File system, Apr. 15, 1992. |
| Michael Factor et al., Object Storage: The Future Building Block For Storage Systems, Global Data Interoperability—Challenges and Technologies, (Sardinia, Italy) Jun. 2005; also published as LGDI '05: Proceedings of the 20051 EEE International Symposium on Mass Storage Systems and Technology (Washington, DC, USA), pp. 119-123, 2005, IEEE Computer Society. |
| Micron Technology, Inc., “NAND Flash 101: An Introduction to NAND Flash and How to Design It in to Your Next Product (TN-29-19),” http://www.micron.com/.about./media/Documents/Products/Technical%20Note/N-AND%20Flash/145tn2919.sub.--nand .sub.--101.pdf, 2006, visited May 10, 2010. |
| Micron Technology, Inc., “Technical Note: Design and Use Considerations for NAND Flash Memory (TN-29-17),” http://download.micron.com/pdf/technotes/nand/tn2917.pdf, 2006, visited May 10, 2010. |
| Micron Technology, Inc., “Technical Note: Hamming Codes for NAND Flash Memory Devices (TN-29-08),” 2005, http://www.micron.com/.about./media/Documents/Products/Technical%20Note/N-AND%20Flash/tn2908.sub.--NAND.sub.--hamming.sub.--ECC.sub.--code.pdf, visited May 10, 2010. |
| Micron, “TN-29-42: Wear-Leveling Techniques in NAND Flash Devices,” Mar. 10, 2010. |
| Morex-Files, http://savolainen.wordpress.com/2008/12/, Dec. 7, 2008, visited Aug. 16, 2012. |
| “NAND Flash Memories and Programming NAND Flash Memories Using ELNEC Device Programmers”, ELNEC, Aug. 2008, pp. 44, Application Note, an.sub.--elnec.sub.--nand.sub.--flash, version 2.10. |
| Non-Final Office Action for U.S. Appl. No. 14/045,605, filed Oct. 3, 2013, and mailed from the USPTO dated Sep. 24, 2015, 29 pgs. |
| “Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group Announces 1.0 Specification”, VNMHCI Working Group, Apr. 15, 2008, pp. 2, http://www.businesswire.com/news/home/2008041.5005169/en/Non-Volatile. |
| Notice of Allowance Received from USPTO, U.S. Appl. No. 12/981,394, dated Oct. 12, 2011. |
| Notice of Allowance, U.S. Appl. No. 13/830,652, dated Apr. 14, 2015. |
| Notice of Rejection in Japense Application No. 2009-540483 dated Jan. 10, 2012, 6 pages. |
| Numonyx Nand Flash Translation Layer (NFTL), http://d1 .amobbs.com/bbs.sub.--upload782111/files.sub.--46/purdev.sub.--6- 84405XFKZAB.pdf, 2011 visited Jun. 12, 2015. |
| Numonyx Nand Flash Translation Layer (NFTL), http://www.numonyx.com/Documents/User%20Guides/UM0405.pdf, 2009, visited Dec. 28, 2009. |
| Object Store, IBM Haifa Labs, Mar. 16, 2006, available at http://www.haifa.ibm.com/projects/storage/objectstore/overview.html (last visited on Mar. 11, 2010). |
| Office Action, U.S. Appl. No. 11/952,116, dated Jun. 24, 2010. |
| Office Action in Chinese Application No. 200780050989.5 dated Dec. 31, 2010, 12 pages. |
| Office Action in Chinese Application No. 200980121088 dated Feb. 7, 2013, 10 pages. |
| Office Action in EP Application No. 07869018.7 dated Nov. 17, 2010, 2 pages. |
| Office Action in European Patent Application No. 07869020.3 dated Oct. 21, 2010, 8 pages. |
| Office Action Received from USPTO, U.S. Appl. No. 11/952,091, dated Feb. 7, 2012. |
| Office Action in 200780050973.4, the Chinese Nationalization of U.S. Appl. No. 11/952,123. |
| Office Action, U.S. Appl. No. 12/098,433, dated Mar. 29, 2011. |
| Office Action, U.S. Appl. No. 12/098,433, dated Nov. 10, 2010. |
| Office Action, U.S. Appl. No. 14/866,461, dated Jul. 26, 2016. |
| Office Action, U.S. Appl. No. 14/866,461, filed Nov. 4, 2015. |
| Oman, PS Stand-Alone and Multi-DEvices Share Common Driver, IBM Mar. 31, 2005. |
| P. Gutmann, Secure Deletion of Data from Magnetic and Solid-State Memory, Proceedings of the Sixth USENIX Security Symposium, Jul. 1996, 14 pages, XP-002190890, San Jose, California. |
| P201014PCT (2380.2.57pct), Application No. PCT/US2012/022244, International Search Report and Written Opinion, dated Jul. 30, 2012, 12 pages. |
| P201021pct, Application No. PCT/US2011/064728, International Search Report and Written Opinion, dated Jul. 31, 2012. |
| PCT/US2007/025050, International Preliminary Reporton Patentability, dated Aug. 20, 2009. |
| PCT/US2007/025050, International Search Report and Written Opinion, dated Jul. 30, 2009. |
| PCT/US2007/025054, International Preliminary Reporton Patentability, dated Jun. 18, 2009. |
| PCT/US2007/025054, International Search Report and Written Opinion, dated Oct. 29, 2008. |
| PCT/US2007/025188, International Search Report and Written Opinion, dated May 30, 2008. |
| PCT/US2007/086704, International Preliminary Reporton Patentability, dated Jun. 18, 2009. |
| PCT/US2007/086704, International Search Report and Written Opinion, dated Sep. 29, 2008. |
| Pei Cao, et al., “The TicklerTAlP parallel RAID architecture,” The Annual International Symposium on Computer Architecture, May 1993, pp. 52-63. |
| Peterson, et al., Final Office Action dated May 4, 2017 for U.S. Appl. No. 13/539,235. |
| Peterson, et al., Non-Final Office Action dated Jul. 14, 2016 for U.S. Appl. No. 13/539,235. |
| “Pivot3 RAIGE Cluster: Technology Overview”, White Paper, www.pivots,com, Jun. 2007, pp. 1-17. |
| Porter, Donald E., et al., “Operating System Transactions,” Department of Computer Sciences, The University of Texas at Austin, SOSP '09, Oct. 11-14, 2009, Big Sky, Montana, ACM 978-1-60558-752-3/09/10, Oct. 2009. |
| Prado et al., “A Standard Product Approach to Spaceborne Payload Processing”, 2001. |
| Probert, David B., “Windows Kernel Internals Cache Manager”, Microsoft Corporation, May 13, 2010, pp. 48. |
| Probert, David B., “Windows Kernel Internals”, Microsoft Corporation, May 13, 2010, pp. 48. |
| Probert, “Windows Kernel Internals Cache Manager,” Microsoft Corporation, http://www.i.u.-tokyo.co.jp/edu/training/ss/lecture/new-documents/Lecture- s/15-CacheManager/CacheManager.pdf, printed May 15, 2010. |
| Ralph O. Weber, SCSI Object-Based Storage Device Commands (ODS), Ansi, Jul. 30, 2004, pp. 0-74, Part 1 of 3. |
| Ralph O. Weber, SCSI Object-Based Storage Device Commands (OSD), ANSI, Jul. 30, 2004, pp. 165-171, Part 3 of 3. |
| Ralph O. Weber, SCSI Object-Based Storage Device Commands (OSD), ANSI, Jul. 30, 2004, pp. 75-164, Part 2 of 3. |
| Ranaweera, 05-270RO, SAT: Write Same (10) command (41h), T10/05, Jul. 7, 2005, www.t10.org/ftp/t10/document.05/05-270r0.pdf, last visited Apr. 11, 2013. |
| Randal, Paul S., “Understanding Logging and Recovery in SQL Server,” Published Feb. 2009; URL https://technet.microsoft.com/en-us/magazine/2009.02.logging.aspx; accessed Sep. 11, 2015. |
| Renata Recio, “A Tutorial of the RDMA Model,” HPC wire, The Leading Source for Global News and Informationcovering the Ecosystem of High Productivity Computing, Sep. 15, 2006, http:l/archive.hpcwire.com/hpc/885757.html, pp. 1-6. [Retrieved Mar. 28, 2013]. |
| Rose, Mike, “FPGA PCIe Bandwidth”, University of California San Diego, Jun. 9, 2010, pp. 7, Department of Computer Science and Engineering. |
| Rosenblum, et al., The Design and Implementation of a Log-Structured File System, ACM Transactions on computer Systems (TOCS) 10.1 (1992): 26-52. |
| Russinovich, Mark E., “Windows Internals, Fifth Edition,” Chapters 11-12: “Common Log File System,” “NTFS Design Goals and Features,” Published Jun. 17, 2009. |
| Salcic, “PROTOS—A microcontroller/FPGA-based prototyping system for embedded applications”, 1997. |
| Sandisk, SanDisk Extreme FFS Significantly Improves SSD performance, http://www.gadgetadvisor.com/computer-hardware/sandisk-extremeffs-sig . . . , last visited Dec. 18, 2009. |
| Sandisk, “SanDisk Extreme FFS speeds SSDs, ”http://www.semiaccurate.com/2009/06/08/sandisk- extreme-ffs-speeds-ssds/, last visited Dec. 18, 2009. |
| Sandisk, “SanDisk Introduces Extreme FFS, Aims 100 Times Faster SSDs”, http://www.physorg.com/news145186489.html, last visited Dec. 18, 2009. |
| Savov, Vlad, “Viking Modular's Satadimm Jacks an SSD Into Your Memory Slot”, Aug. 27, 2010, pp. 6. |
| Sears, Russell C., “Stasis: Flexible Transactional Storage”, University of California at Berkeley, Jan. 8, 2010, pp. 176, Technical Report No. UCB/EECS-2010-2, http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-2.html. |
| Sears, Russell, et al., “Stasis: Flexible Transactional Storage,” University of California, Berkeley, USENIX Association, OSDI '06: 7.sup.th USENIX Symposium on Operating Systems Design and Implementation, pp. 29-44, Nov. 6, 2006. |
| Second Office Action in CN Application No. 200980121088 dated Jul. 12, 2013, 9 pages. |
| Seltzer, Margo, et al., “Transaction Support in Read Optimized and Write Optimized File Systems,” Department of Electrical Engineering and Computer Science, University of California Berkeley, California 94720, Proceedings of the 16.sup.th VLDB Conference, Brisbane, Australia, 1990. |
| Seltzer, Margo Ilene, “File System Performance and Transaction Support,” A.B. (Harvard/Radcliffe College) 1983, A dissertation submitted in partial satisfaction of the requirements of the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California at Berkeley, 1992. |
| Seltzer, Margo Ilene, “Transaction Support in a Log-Structured File System”, Harvard University, pp. 8, Mar. 7, 2013. |
| Seltzer, “Transaction Support in a Log-Structured File System”, Harvard University Division of Applied Sciences, published Jan. 1, 1993 (Chapters, pp. 52-69). |
| Shibata “19nm 112.8mm2 64Gb Multi-Level Flash Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface” Flash Memory Summit, (2012), 30 pages. |
| Shimpi, Anand Lal, “The SSD Anthology Understanding SSDs and New Drives”, Revised Mar. 18, 2009, pp. 59. |
| Shrout, Ryan, “Gigabyte iRAM Solid State SATA Storage Review”, PC Perspective, Apr. 5, 2006, pp. 2, http://www.pcper.com/article.php?aid=224&type=expert. |
| Shu, “Data Set Management Commands Proposal for ATA8-ACS2”, Oct. 5, 2007, Revision 3. |
| Shu Etal, U.S. Provisional U.S. Appl. No. 60/912,728, filed Apr. 19, 2007. |
| Shu, Frank, “Data Set Management Commands Proposal for ATA8-ACS2”, Microsoft Corporation, Sep. 5, 2007, pp. 8, Revision 2, Redmond, Washington, US. |
| Small et al., “PCI Bus Master in a Quicklogic 8000 Gate FPGA”. |
| Spillane, Richard P., “Enabling Transactional File Access via Lightweight Kernel Extensions”, USENIX Association, published Feb. 25, 2009, pp. 14, 7th USENIX Conference on File and Storage Technologies. |
| Staf, “Adaptation of OSEck for an FPGA-Based Soft Processor Platform”, Aug. 2007. |
| State Intellectual Property Office, Office Action, CN Application No. 200780050970.0, dated Jun. 29, 2011. |
| State Intellectual Property Office, Office Action, CN Application No. 200780050970.0, dated Oct. 28, 2010. |
| State Intellectual Property Office, Office Action, CN Application No. 200780050983.8, dated May 18, 2011. |
| State Intellectual Property Office, Office Action, CN Application No. 200780051020.X, dated Jul. 6, 2011. |
| State Intellectual Property Office, Office Action, CN Application No. 200780051020.X, dated Nov. 11, 2010. |
| State Intellectual Property Office, Office Action, CN Application No. 200780051020.X, dated Nov. 7, 2011. |
| State Intellectual Property Office, Third Office Action, CN Application No. 200780050970.0, dated Jan. 5, 2012. |
| Stodolsky, D., “Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays”, Proceedings of the Annual International Symposium on Computer Architecture, May 16-19, 1993, pp. 12, XP010095790 ISBN: 978-0-8186-3810-7, San Diego, California, US. |
| Stokes, Jon, “Intel's New Flash Tech to Bring Back Turbo Memory, for Real”, http://arstechnica.com/hardware/news/2009/09/intels-new-flash-tech- -to-bring-back-turbo-memory-for-real.ars, retrieved Apr. 23, 2012. |
| Suh, Kang-Deog, “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, Nov. 30, 1995, pp. 8, vol. 30, No. 11, New York, US. |
| Sunita Jain et al., “Point-to-Point Connectivity Using Integrated Endpoint Block for PCI Express Design”, Oct. 4, 2007. |
| “T10/05-270r0 SAT—Write Same (10) command (41h)”, Network Appliance, Jul. 7, 2005, p. 2. |
| “(Take 2): Transcendent Memory (“tmem”) for Linux”, LWN Merchandise, 2009, pp. 3, http://lwn.net/Articles/340409/. |
| Tai, et al., NAND vx. NOR Flash Technology, M-Systems, www2.electronicproducts.com/PrintArticle.aspx?ArticleURL-FEBMSY1 .Feb. 2002.- html, visited Nov. 22, 2010. |
| Tai, “NAND vs. NOR Flash Technology”, M-Systems, published Feb. 1, 2002 (http://www2.electronicproducts.com/NAND.sub.--vs.sub.--NOR.sub.--flash.s- ub.--technology-article-FEBMSY1-feb2002-html.aspx) accessed May 29, 2012. |
| Terry et al., U.S. Appl. No. 60/797,127, “Filesystem-aware Block Storage System, Apparatus, and Method,” filed May 3, 2006. |
| “The Advantages of Object-Based Storage-Secure, Scalable, Dynamic Storage Devices”, Seagate Research Technology Paper, Apr. 2005, pp. 7, Scotts Valley, California, US. |
| United States Patent Office, Office Action, U.S. Appl. No. 11/952,113, dated Mar. 6, 2012. |
| United States Patent and Trademark Office, Notice of Allowance, U.S. Appl. No. 12/878,981, dated Jun. 25, 2012. |
| United States Patent Office, Final Office Action, U.S. Appl. No. 13/193,559, dated Dec. 16, 2014, 32 pages. |
| United States Patent Office, Non-Final Office Action, U.S. Appl. No. 13/107,820, dated Feb. 22, 2013. |
| United States Patent Office, Non-Final Office Action, U.S. Appl. No. 13/335,922, dated Aug. 29, 2013, 8 pages. |
| United States Patent Office, Non-Final Office Action, U.S. Appl. No. 13/539,235, dated Feb. 13, 2015,16 pages. |
| United States Patent Office, Notice of Allowance, U.S. Appl. No. 13/694,000, dated Feb. 4, 2015, 22 pages. |
| United States Patent Office, Notice of Allowance, U.S. Appl. No. 14/866,461, dated Nov. 8, 2016, 6 pages. |
| United States Patent Office, Office Action, U.S. Appl. No. 14/042,189, dated Jun. 4, 2015, 31 pages. |
| United States Patent Office, Pre-Interview Communication, U.S. Appl. No. 13/193,559, dated Jul. 8, 2014. |
| U.S. Appl. No. 13/480,791, Office Action, dated Aug. 3, 2012. |
| U.S. Appl. No. 11/952,091, 2380.2.1, Notice of Allowance, dated Jun. 28, 2012. |
| U.S. Appl. No. 11/952,095, 2380.2.2, Office Action, dated Feb. 14, 2012. |
| U.S. Appl. No. 11/952,095, 2380.2.2, Office Action, dated Jun. 8, 2011. |
| U.S. Appl. No. 11/952,095, 2380.2.2, Office Action, dated Sep. 4, 2013. |
| U.S. Appl. No. 11/952,095, OfficeAction, dated Oct. 29, 2010. |
| U.S. Appl. No. 11/952,098, Final Office Action, dated Sep. 18, 2012. |
| U.S. Appl. No. 11/952,098, Office Action, dated Jan. 13, 2012. |
| U.S. Appl. No. 11/952,098, Office Action, dated Jan. 7, 2011. |
| U.S. Appl. No. 11/952,098, Office Action, dated Oct. 8, 2013. |
| U.S. Appl. No. 11/952,101, Office Action, dated Dec. 22, 2011. |
| U.S. Appl. No. 11/952,101, Office Action, dated Jan. 6, 2011. |
| U.S. Appl. No. 11/952,109, Office Action, dated Jul. 1, 2011. |
| U.S. Appl. No. 11/952,109, Office Action, dated Mar. 17, 2011. |
| U.S. Appl. No. 11/952,115, Notice of Allowance, dated Apr. 26, 2011. |
| U.S. Appl. No. 11/952,115, Office Action, dated Mar. 10, 2010. |
| U.S. Appl. No. 11/952,120, Notice of Allowance, dated Dec. 20, 2010. |
| U.S. Appl. No. 11/952,120, Office Action, dated Apr. 20, 2010. |
| U.S. Appl. No. 11/952,120, OfficeAction, dated Aug. 13, 2010. |
| U.S. Appl. No. 11/952,121 Non-Final Office Action dated Dec. 19, 2016. |
| U.S. Appl. No. 11/952,123, Final Office Action, dated Oct. 5, 2010. |
| U.S. Appl. No. 11/952,123, Notice of Allowance, dated Apr. 8, 2011. |
| U.S. Appl. No. 11/952,123, Notice of Allowance, dated Jan. 19, 2011. |
| U.S. Appl. No. 11/952,123, OfficeAction, dated May 5, 2010. |
| U.S. Appl. No. 12/098,427, Office Action, dated Jun. 19, 2012. |
| U.S. Appl. No. 12/098,427, Notice of Allowance, dated Sep. 27, 2012. |
| U.S. Appl. No. 12/098,431, Notice of Allowance, dated Dec. 16, 2011. |
| U.S. Appl. No. 12/098,431, Office Action, dated Aug. 12, 2011. |
| U.S. Appl. No. 12/098,433, Notice of Allowance, dated Nov. 23, 2011. |
| U.S. Appl. No. 12/098,434, Office Action, dated Oct. 29, 2010. |
| U.S. Appl. No. 12/273,532, Notice of Allowance, dated Apr. 6, 2011. |
| U.S. Appl. No. 12/273,532, Notice of Allowance, dated Jul. 29, 2011. |
| U.S. Appl. No. 12/790,920, Office Action, dated Sep. 4, 2012. |
| U.S. Appl. No. 12/877,971, Notice of Allowance, dated Jan. 17, 2014. |
| U.S. Appl. No. 12/877,971, Notice of Allowance, dated Sep. 20, 2013. |
| U.S. Appl. No. 12/877,971, Office Action, dated Sep. 27, 2012. |
| U.S. Appl. No. 12/878,981, Notice of Allowance, dated Aug. 28, 2012. |
| U.S. Appl. No. 12/878,987, Notice of Allowance, dated Mar. 21, 2013. |
| U.S. Appl. No. 12/878,987, Office Action, dated Oct. 18, 2012. |
| U.S. Appl. No. 12/879,004, Notice of Allowance, dated Aug. 13, 2013. |
| U.S. Appl. No. 12/879,004, Office Action, dated Sep. 28, 2012. |
| U.S. Appl. No. 12/885,285, Notice of Allowance, dated Feb. 4, 2013. |
| U.S. Appl. No. 12/885,285, Notice of Allowance, dated Oct. 17, 2012. |
| U.S. Appl. No. 12/981,394, Notice of Allowance, dated Feb. 6, 2012. |
| U.S. Appl. No. 12/986,117, Office Action, dated Nov. 1, 2013. |
| U.S. Appl. No. 13/015,458, Notice of Allowance, dated Sep. 19, 2012. |
| U.S. Appl. No. 13/015,458, Office Action, dated Sep. 7, 2012. |
| U.S. Appl. No. 13/075,000, Notice of Allowance, dated Sep. 27, 2012. |
| U.S. Appl. No. 13/075,000, Office Action, dated Apr. 23, 2012. |
| U.S. Appl. No. 13/075,000, Office Action, dated Nov. 16, 2011. |
| U.S. Appl. No. 13/075,000, Office Action, dated Sep. 1, 2011. |
| U.S. Appl. No. 13/088,211, 3430.257, Final Office Action, dated Dec. 29, 2014. |
| U.S. Appl. No. 13/088,211, 3430.257, Notice of Allowance, dated Apr. 15, 2015. |
| U.S. Appl. No. 13/107,820, Notice of Allowance, dated Jul. 31, 2013. |
| U.S. Appl. No. 13/174,449, Office Action, dated Sep. 11, 2012. |
| U.S. Appl. No. 13/182,315, Notice of Allowance, dated Dec. 17, 2012. |
| U.S. Appl. No. 13/189,402, Notice of Allowance, dated Nov. 15, 2012. |
| U.S. Appl. No. 13/204,551, Notice of Allowance, dated Jul. 12, 2012. |
| U.S. Appl. No. 13/204,551, Office Action, dated Jan. 13, 2012. |
| U.S. Appl. No. 13/209,007, Notice of Allowance, dated Apr. 4, 2013. |
| U.S. Appl. No. 13/248,006, Notice of Allowance, dated Nov. 8, 2013. |
| U.S. Appl. No. 13/248,006, Office Action, dated Aug. 30, 2013. |
| U.S. Appl. No. 13/324,942, Notice of Allowance, dated May 2, 2013. |
| U.S. Appl. No. 13/372,430, Notice of Allowance, dated Nov. 3, 2014. |
| U.S. Appl. No. 13/372,430, Advisory Action, dated Aug. 6, 2014. |
| U.S. Appl. No. 13/372,430, Final Office Action, dated Apr. 21, 2014. |
| U.S. Appl. No. 13/372,430, Office Action, dated Nov. 7, 2013. |
| U.S. Appl. No. 13/406,287, Office Action, dated Jun. 2, 2014. |
| U.S. Appl. No. 13/406,287, Pre-Office Action, dated Dec. 16, 2013. |
| U.S. Appl. No. 13/600,077, Notice of Allowance, dated Apr. 30, 2013. |
| U.S. Appl. No. 13/600,077, Office Action, dated Jan. 7, 2013. |
| U.S. Appl. No. 13/607,486, Notice of Allowance, dated Jul. 11, 2013. |
| U.S. Appl. No. 13/607,486, Office Action, dated Jan. 10, 2013. |
| U.S. Appl. No. 13/652,427, Office Action, dated Nov. 20, 2014. |
| U.S. Appl. No. 13/730,602, Office Action, dated Jan. 15, 2015. |
| U.S. Appl. No. 13/776,389, Final Office Action, dated Jun. 20, 2014. |
| U.S. Appl. No. 13/776,389, Office Action, dated Dec. 16, 2013. |
| U.S. Appl. No. 13/776,406, Notice of Allowance, dated May 13, 2014. |
| U.S. Appl. No. 13/776,406, Office Action, dated Nov. 6, 2013. |
| U.S. Appl. No. 13/800,628, Office Action, dated Dec. 5, 2014. |
| U.S. Appl. No. 13/830,652, Final Office Action, dated Jan. 7, 2015. |
| U.S. Appl. No. 13/830,652, Office Action, dated Aug. 12, 2014. |
| U.S. Appl. No. 13/834,955, Final Office Action, dated Sep. 8, 2014. |
| U.S. Appl. No. 13/834,955, Office Action, dated Apr. 4, 2014. |
| U.S. Appl. No. 13/836,826, Notice of Allowance, dated Jul. 30, 2015. |
| U.S. Appl. No. 13/836,826, Office Action, dated Feb. 24, 2015. |
| U.S. Appl. No. 13/838,070, Notice of Allowance, dated Aug. 26, 2015. |
| U.S. Appl. No. 13/931,897, Notice of Allowance, dated Dec. 23, 2013. |
| U.S. Appl. No. 13/931,897, Office Action, dated Sep. 6, 2013. |
| U.S. Appl. No. 14/011,395, Final Office Action, dated Jun. 26, 2014. |
| U.S. Appl. No. 14/011,395, Final Office Action, dated May 18, 2015. |
| U.S. Appl. No. 14/011,395, Notice of Allowance, dated Aug. 19, 2015. |
| U.S. Appl. No. 14/011,395, Office Action, dated Jan. 16, 2014. |
| U.S. Appl. No. 14/011,395, Office Action, dated Oct. 31, 2014. |
| U.S. Appl. No. 60/718,768, Provisional, filed Aug. 20, 2005. |
| USPTO, Notice of Allowance forU.S. Appl. No. 12/986,117 dated Jun. 5, 2013. |
| USPTO, Notice of Allowance, U.S. Appl. No. 11/952,109, dated Aug. 31, 2012. |
| USPTO, Office Action for U.S. Appl. No. 11/952,113, dated Dec. 15, 2010. |
| USPTO, Office Action for U.S. Appl. No. 12/711,113, dated Jun. 6, 2012. |
| USPTO, Office Action for U.S. Appl. No. 12/711,113, dated Nov. 23, 2012. |
| USPTO, Office Action for U.S. Appl. No. 12/879,004 dated Feb. 25, 2013. |
| USPTO, Office Action for U.S. Appl. No. 12/986,117, dated Apr. 4, 2013. |
| USPTO, Office Action for U.S. Appl. No. 13/118,237 dated Apr. 22, 2013. |
| USPTO, Office Action for U.S. Appl. No. 13/607,486 dated May 2, 2013. |
| USPTO, Office Action, U.S. Appl. No. 11/952,109, dated May 1, 2012. |
| Volos, Haris, et al., “Mnemosyne: Lightweight Persistent Memory,” Computer Sciences Department, University of Wisconsin-Madison, Skype Limited, ASPLOS '11, Mar. 5-11, 2011, Newport Beach, California, ACM 978-1-4503-0266-1/11/03, Mar. 5, 2011. |
| Wacha, Rosie; A Reliability Enhancing Mechanism fora Large Flash Embedded Satellite Storage System Improving RAID-Based Storage Systems with Flash Memory, Oct. 20-21, 2009. |
| Wacha, Rosie, “Improving RAID-Based Storage Systems with Flash Memory”, First Annual ISSDM/SRL Research Symposium, Oct. 20-21, 2009, pp. 21. |
| Walp, David, “System Integrated Flash Storage”, Microsoft Corporation, 2008, pp. 35. |
| Walp, “System Integrated Flash Storage,” Microsoft Corporation, 2008, http://download.microsoft.com/download/5/E/6/5E66B27B-988B-4F50-AF3A-C2FF-1E62180F/COR-T599 WHO8.pptx, Printed Apr. 6, 2010, 8 pgs. |
| Wang, Feng, “OBFS: A File System for Object-based Storage Devices”, 21st IEEE/12th NASA Goddard Conference on Mass Storage Systems and Technologies (MSST2004), Apr. 2004, pp. 18, College Park, Maryland, US. |
| Weber, Ralph O., “Information Technology—SCSI Object-Based Storage Device Commands”, Seagate Technology, Jul. 30, 2004, pp. 187, Project T10/1355-D, Reference No. ISO/IEC 14776-391 : 200x ANSI INCITS. .200x. |
| Weissel, Andreas, “Revisiting Log-Structured File Systems for Low-Power Portable Storage,” Published Mar. 2005; Accessed at URL: https://www4.cs.fau.de/weissei/Publications/Papers/IWSSPS05.pdf. |
| Whyte, Barry, “IBM San Volune Controller 4.2.1 Cache Partitioning”, Redpaper IBM Corporation, Apr. 30, 2008, pp. 12, REDP-4426-00, Poughkeepsie, New York, US. |
| Wikipedia, “Adaptive Replacement Cache”, last modified Jun. 25, 2012, http://en.wikipedia.org/wiki/Adaptive.sub.--l replacement.sub.--cache. |
| Wikipedia, “Journaling File System”. Published on Jul. 4, 2009. URL: https://en.wikipedia.org/wiki/Journaling.sub.--file.sub.--system. |
| Wikipedia, Lustre (file system), http://en.wikipedia.org/wiki/Lustre.sub.--(file system), last visited Apr. 29, 2010. |
| Wikipedia, “Object Storage Device,” http://en.wikipedia.org/wiki/Object-storage-device, last visited Apr. 29, 2010. |
| Wikipedia. “Transaction log”. Published on Jul. 4, 2009. URL: https://en.wikipedia.org/wiki/Transaction.sub.--log. |
| “Windows PC Accelerators”, Nov. 30, 2006, pp. 1-16, XP002476842, URL:http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde--d599bac8184a/perfaccel.doc. |
| WIPO, International Preliminary Report on Patentability for PCT/US2008/059048, dated Oct. 20, 2009. |
| WIPO, International Preliminary Report on Patentability for PCT/US2009/039618, dated Oct. 12, 2010. |
| WIPO, International Search Report and Written Opinion for PCT/US2007/086687, dated Sep. 5, 2008, 21 pages. |
| WIPO, International Search Report and Written Opinion for PCT/US2008/059048, dated Aug. 25, 2008. |
| WIPO, International Search Report and Written Opinion for PCT/US2009/039618, dated Jul. 3, 2009. |
| WIPO, International Search Report and Written Opinion for PCT/US2010/048325, dated Jun. 1, 2011, 6 pages. |
| WIPO, International Search Report and Written Opinion for PCT/US2011/025885, dated Sep. 28, 2011, 9 pages. |
| WIPO, International Search Report and Written Opinion for PCT/US2011/65927, dated Aug. 28, 2012. |
| WIPO, International Search Report and Written Opinion for PCT/US2012/029722, dated Oct. 30, 2012. |
| WIPO, Preliminary Report on Patentability for PCT/US2007/086691, dated Feb. 16, 2009, 15 pages. |
| Wright, Charles P., “Amino: Extending ACID Semantics to the File System”, p. 1, Mar. 7, 2013. |
| Wright,Charles P. et al., Extending ACID Semantics to the File System, IBM T.J. Watson Research Center, Stony Brook University, ACM Transactions on Storage, vol. 3, No. 2, May 2007, pp. 1-40. |
| Wu, Michael, et al., “eNVy: A Non-Volatile, Main Memory Storage System,” Department of Electrical and Computer Engineering, Department of Computer Science, Rice University, ASPLOS VI-10/94 San Jose, California, 1994, ACM 0-89791-660-3/94/0010, pp. 86-97, 1994. |
| “Sybase: Maximizing Performance through Solid State File-Caching”, SolidData Systems Best Practices Guide, May 2000, pp. 4, Santa Clara, California, US. |
| Yehuda, et al.,Atomicity of Restful Radosgw Operations, The Ceph Blog, Nov. 7, 2011, (Nov. 7, 2011), XP055148638, Retrieved from the Internet: URL:http://ceph.com/dev-notes/atomicity-of-restful-radosgw-operations/, [retrieved on Feb. 23, 2016], 3 pgs. |
| Zhang, Yiying, “De-indirection for Flash-based SSDs with Nameless Writes”, University of Wisconsin-Madison, 2012, p. 16, www.usenix.org/event/fast12/tech/full.sub.--papers/Zhang. |
| Zircon UL Data Sheet, Remote Management Controller, 2001, Qlogic Corporation. |
| Public file history of U.S. Pat. No. 8,762,658, titled “Systems and Methods for Persistent Deallocation,” to Flynn et al. Aug. 3, 2012. |
| Public file history of U.S. Pat. No. 9,632,727 B2, titled “Systems and Methods for Identifying Storage Resources That Are Not in Use” to Flynn et al. (Jun. 19, 2014). |
| SD Specifications Part 1 Physical Layer Simplified Specification Version 1.10, SD Group and SD Card Association Technical Committee (Mar. 18, 2005). |
| Serial ATA: High Speed Serialized AT Attachment Revision 1.0, Serial ATA International Organization (Aug. 29, 2001). |
| Serial ATA (SATA) Revision 2.5, Serial ATA International Organization (Oct. 27, 2005). |
| U.S. Appl. No. 60/974,470 for “Apparatus, System, And Method for Object-Oriented Solid-State Storage,” to Flynn et al. (“Sept. '07 provisional”). filed Sep. 22, 2007. |
| U.S. Appl. No. 60/873,111 titled “Elemental Blade System,” to Flynn et al. (filed Dec. 6, 2006). |
| Wayback Machine Archive of Microsoft WinHEC 2007 Conference Presentations Website, captured Sep. 12, 2007, https://web.archive.org/web/20070214023104/http://www.microsoft.com/whdc/winhec. |
| William D. Brown & Joe E. Brewer, Nonvolatile Semiconductor Memory Technology (IEEE 1998). |
| Amended Scheduling Order, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020), ECF No. 48. (Nov. 24, 2020). |
| American National Standard for Information Technology—AT Attachment with Packet Interface—6 (ATA/ATAPI-6), ANSI INCITS 361-2002 (Sep. 2002) (excerpts filed with permission). |
| American National Standard for Information Technology—AT Attachment with Packet Interface—7 vol. 1—Register Delivered Command Set, Logical Register Set (ATA/ATAPI-7 V1), ANSI INCITS 397-2005 (Feb. 7, 2005) (excerpts filed with permission). |
| American National Standard for Information Technology-ATA/ATAPI Command Set—2 (ACS-2), ANSI INCITS 482- 2012 (May 30, 2012) (excerpts filed with permission). |
| Apr. 2007 Plenary Minutes 2, e07156r0 (T13 and INCITS, Apr. 24, 2007). |
| Brian Dipert & Markus Levy, Designing With Flash Memory (Annabooks 1994). |
| Claim Construction Order, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020), ECF No. 67. Mar. 12, 2021. |
| Computer generated redline comparison of changes from the Shu Provisional to the Shu Patent, Jun. 4, 2021. |
| Curriculum vitae of Jacob Baker, Ph.D., P.E. (Jun. 2021). |
| Curriculum vitae of Sylvia Hall-Ellis, Ph.D. Nov. 2020. |
| Declaration of Frank Shu Regarding Publication of Proposals (Ex. 1018 and 1019) dated Jun. 2, 2021. |
| Declaration of R. Jacob Baker, Ph.D., P.E., Regarding U.S. Pat. No. 9,632,727. (Dec. 22, 2020). |
| Docket Report for Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020) (accessed Dec. 22, 2020). |
| Eran Gal et al., Mapping Structures for Flash Memories: Techniques and Open Problems, Proceedings of the IEEE International Conference On Software-Science, Technology & Engineering (“SwSTE'05”) (digital version), Herzlia, Israel, 2005, pp. 83-92, doi: 10.1109/SWSTE.2005.14. |
| Excerpt of Plaintiffs Responses to Defendant's First Set of Interrogatories (No. 16) (Apr. 26, 2021), Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020). Apr. 26, 2021. |
| Exhibit A to Plaintiffs First Amended Infringement Contentions: Unification Technologies' Allegations of Infringement with Respect to U.S. Pat. No. 8,762,658, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020). |
| Exhibit B to Plaintiffs First Amended Infringement Contentions: Unification Technologies' Allegations of Infringement with Respect to U.S. Pat. No. 8,533,406, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020). |
| Exhibit C to Plaintiffs First Amended Infringement Contentions: Unification Technologies' Allegations of Infringement with Respect to U.S. Pat. No. 9,632,727, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020). |
| Expert Declaration of Jacob Baker, Ph.D., P.E., Regarding U.S. Pat. No. 8,533,406 (Dec. 22, 2020). |
| Expert Declaration of Jacob Baker, Ph.D., P.E., Regarding U.S. Pat. No. 8,762,658 (Jun. 4, 2021). |
| Expert Declaration of Jacob Baker, Ph.D., P.E., Regarding U.S. Pat. No. 9,632,727 (Jun. 4, 2021). |
| Expert Report of Sylvia D. Hall-Ellis, Ph.D., Regarding Public Availability of the IBM Journal Publication (Ex. 1027), dated May 26, 2021. |
| Expert Report of Sylvia Hall-Ellis, Ph.D. in Support of Public Availability of the Gal Publication. (Dec. 17, 2020). |
| Filed Stipulations of Petitioners for U.S. Pat. No. 8,533,406. Dec. 22, 2020. |
| Filed Stipulations of Petitioners for U.S. Pat. No. 8,762,658. (Dec. 22, 2020). |
| Filed Stipulations of Petitioners for U.S. Pat. No. 9,632,727. (Dec. 22, 2020). |
| Frank Shu & Nathan Obr, Data Set Management Commands Proposal for ATA8-ACS2 Revision 1, T13 (Jul. 26, 2007). |
| Frank Shu & Nathan Obr, Notification of Deleted Data Proposal for ATA8-ACS2 Revision 0, T13 (Apr. 21, 2007, 2007). |
| Frank Shu & Nathan Obr, Notification of Deleted Data Proposal for ATA8-ACS2 Revision 1, T13 (Jul. 26, 2007). |
| Frank Shu & Nathan Obr, Notification of Deleted Data Proposal for ATA8-ACS2 Revision 2, T13 (Septembers, 2007). |
| Frank Shu, Notification of Deleted Data Proposal for ATA8-ACS2, T13 (rev. 0 Apr. 21, 2007). |
| Frank Shu, Solid-State Drives: Next-Generation Storage, Microsoft WinHEC 2007 (May 14-17, 2007). |
| Frank Shu, Windows 7 Enhancements for Solid-State Drives, Microsoft WinHEC 2008 (Nov. 4-6, 2008). |
| H. Niijima, Design of a Solid-State File Using Flash Eeprom, IBM Journal of Research and Development, vol. 39, No. 5, pp. 531-545, Sep. 1995. |
| IDS submitted on Sep. 25, 2013 during prosecution U.S. Pat. No. 8,762,658. |
| Institute for the Advancement of the American Legal System, Civil Case Processing in the Federal District Courts (2009). |
| Judge Albright, Order Governing Proceedings - Patent Case (rev. 3.2). Nov. 12, 2020. |
| Mapping Structures for Flash Memories: techniques and open problems, IEEE Xplore, https://ieeexplore.ieee.org/document/1421068 (last visited Dec. 18, 2020). |
| MARC record for Library of Congress, Nov. 30, 2020. |
| MARC record for the print digital version of the IEEE International Conference on Software-Science, Technology & Engineering Proceedings in the Linda Hall Library (Sep. 1, 2008). |
| MARC record for the print version of the IEEE International Conference on Software-Science, Technology & Engineering Proceedings obtained from the OCLC bibliographic database, 2005. |
| Micron's Preliminary Identification of Extrinsic Evidence, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020). |
| Original Complaint for Patent Infringement, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020), ECF No. 1. Jun. 5, 2020. |
| Plaintiffs Reply Claim Construction Brief, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020), ECF No. 57. Feb. 3, 2021. |
| Plaintiffs Revised Claim Constructions, Unification Techs. LLC v. Micron Tech. Inc., No. 6:20-cv-500 (W.D. Tex. 2020). Dec. 9, 2020. |
| Proceedings. IEEE International Conference on Software—Science, Technology and Engineering, IEEE Computer Society, www.computer.org/csdl/proceedings/swste/2005/12OmNC17hWm (last visited Oct. 30, 2020). |
| Public file history of U.S. Pat. No. 8,533,406, titled “Apparatus, System, and Method for Identifying Data That is No. Longer in Use,” to Flynn et al. (Sep. 7, 2012). |
| Number | Date | Country | |
|---|---|---|---|
| 20210294753 A1 | Sep 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60974470 | Sep 2007 | US | |
| 60873111 | Dec 2006 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15402936 | Jan 2017 | US |
| Child | 17343116 | US | |
| Parent | 11952095 | Dec 2007 | US |
| Child | 15402936 | US |
