Apparatus, system, and method to adaptively optimize power dissipation and broadcast power in a power source for a communication device

Description

INTRODUCTION

The present disclosure is directed generally to techniques to adaptively optimize power dissipation and broadcast power in a power source for a communication device. More particularly, the present disclosure is directed to techniques to adaptively optimize power dissipation and broadcast power in a power source for an ingestible communication device. In particular, the present disclosure is directed to techniques to adaptively optimize power dissipation or adaptively optimize broadcast power for an ingestible event marker (IEM) (or a combination thereof), which acts as a galvanic electrical power source, e.g., battery, while dissimilar materials dissolve when exposed to a conducting fluid. Once energized in the manner discussed herein, the IEM communicates a broadcast signal, as described in more detail hereinbelow. Accordingly, it may be desirable, during an IEM broadcast cycle, to optimize transmission of signals while minimizing the charge removed from the galvanic battery source. It may be further desirable to optimize signal transmission by controlling the combination of current drained from the battery and the pulse width of a transmission pulse during the broadcast cycle and balancing the output charge against a pre-determined battery recovery voltage or battery impedance measurement.

The present disclosure also is directed generally to an apparatus, system, and method to determine the availability of battery power prior to the ingestible communication device entering a high current draw mode of operation. For ingestible device, such as IEM, operations, where the battery impedance is determined by the amount of material dissolution over time, and could vary by a factor of ten or more, it may be desirable to know that the battery is capable of sustaining a predetermined current draw prior to performing broadcast communication operations.

The present disclosure also is directed generally to an apparatus, system, and method for integrated circuits using the substrate as a negative terminal. It is not uncommon for complementary metal oxide semiconductor (CMOS) devices using P type starting material to have their substrate referenced to the most negative potential of the system. For an ingestible device, such as IEM, this substrate connection forms the negative terminal of the power source, while the top of the semiconductor wafer is connected to the positive terminal of the power source. Given this configuration, it may be difficult to provide a negative terminal connection on the top side of the wafer due to the possibility of either shorting the positive terminal during power source activation, or causing increased leakage currents between the two terminals. This difficulty in providing a negative terminal on the top side of the wafer and relying on the substrate connection only, may cause measurement inaccuracies at wafer sort test due to the impedance from the substrate to the on chip circuits connected to the negative terminal. Accordingly, it may be desirable to provide a negative terminal connection that can be placed on the top side of the wafer that is activated only during test modes and is left in a high impedance state during all other modes of operation.

The present disclosure also is directed generally to an apparatus, system, and method to separate a power source from a broadcast power source in an ingestible device, such as an IEM. In a typical architecture, the power source of an IEM is shared between the digital circuits, analog circuits and I/O circuits. This sharing of the power source results in additional circuitry of which is required to disconnect the shared power source from the analog and/or digital circuits prior to broadcast as to not affect their operation and store enough charge on storage device so that the analog and digital circuits remain operational during the time the power source is disconnected from these circuits. Accordingly, it may be desirable to provide a method whereby the IEM power source can be physically separated into multiple power sources of predetermined values allowing the removal of the charge storage device. In addition, it may be desirable to provide an architecture to de-sensitize the digital and analog circuits from any coupling effect that the close proximity of one power source to another may cause.

SUMMARY

In one aspect, a method of stabilizing battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet is provided. The method comprises receiving, by a logic circuit, a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller; determining, by the logic circuit, a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; and performing, by the logic circuit, either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

FIGURES

FIG. 1 is a block diagram representation of one aspect of an event indicator system with dissimilar metals positioned on opposite ends.

FIG. 2 is a block diagram illustration of one aspect of a control device used that may be employed in the system of FIG. 1.

FIG. 3 is a block diagram of one aspect of an event indicator system in communication with a receiver.

FIG. 4A illustrates one aspect of a beacon switching module providing a sniff period longer than a transmit signal repetition period.

FIG. 4B illustrates one aspect of a beacon switching module providing a short but frequent sniff period and a long transmit packet are provided.

FIG. 5 illustrates one aspect of a decision logic for an automatic calibration process.

FIG. 6 illustrates one aspect of a decision logic for an automatic calibration tune-up process.

FIG. 7 illustrates one aspect of a decision logic for an automatic calibration tune-down process.

FIG. 8 illustrates one aspect of a battery availability determination circuit to determine the availability of battery power prior to the ingestible communication device entering a high current draw mode of operation.

FIG. 9 illustrates a circuit diagram for providing a negative terminal connection that can be placed on the top side of a wafer that is activated only during test modes and is left in a high impedance state during all other modes of operation.

DESCRIPTION

Before explaining various aspects of apparatuses, systems, and methods for adaptively optimizing power dissipation and broadcast power in a power source for a communication device in detail, it should be noted that the aspects of such techniques disclosed herein are not limited in application or use to the details of construction and arrangement of parts illustrated in the following description and accompanying drawings. The various aspects may be implemented or incorporated in other aspects, variations and modifications, and may be practiced or carried out in various ways. Further, unless otherwise indicated, the terms and expressions employed herein have been chosen for the purpose of describing the illustrative aspects for the convenience of the reader and are not for the purpose of limitation thereof. Further, it should be understood that any one or more of the disclosed aspects, expressions thereof, and examples, can be combined with any one or more of the other disclosed aspects, expressions thereof, and examples, without limitation.

Embodiment 1

In one aspect, the present disclosure is directed generally to an apparatus, system, and method for adaptively optimizing power dissipation and broadcast power in a power source, such as a battery, for a communication device. More particularly, in one aspect, the present disclosure is directed to an apparatus, system, and method for adaptively optimizing power dissipation and broadcast power in a power source for an ingestible communication device. More particularly, in yet another aspect, the present disclosure is directed to an apparatus, system, and method for adaptively optimizing power dissipation and broadcast power in a battery for an IEM, for example.

In one aspect techniques for adaptively optimizing power dissipation and broadcast power in a power source, such as a battery, for a communication device may be implemented with automatic calibration decision logic employing tune-up and tune-down procedures for adaptively optimizing power dissipation and broadcast power in a battery. In accordance with the present disclosure, the automatic calibration decision logic, including tune-up and tune-down procedures for adaptively optimizing power dissipation and broadcast power in a battery can be practiced, is implemented in a system comprising an IEM. Aspects of IEM devices are disclosed in U.S. Pat. No. 7,978,064 to Zdeblick et al., titled “Communication System with Partial Power Source,” which is incorporated herein by reference in its entirety.

Before describing various aspects of the automatic calibration decision logic and tune-up/tune-down procedures for adaptively optimizing power dissipation and broadcast power in a battery, the present disclosure now turns to a brief description of a system in which the automatic calibration decision logic and tune-up/tune-down procedures for adaptively optimizing power dissipation and broadcast power in a battery can be practiced.

Accordingly, FIG. 1 is a block diagram representation of one aspect of an event indicator system 100 with dissimilar metals positioned on opposite ends. In one aspect, the system 100 can be used in association with any pharmaceutical product. In one aspect, the system, may be used to determine when a patient takes the pharmaceutical product, such as a pill, tablet, or capsule, without limitation. The scope of the present disclosure, however, is not limited by the environment and the product that is used with the system 100. For example, the system 100 may be placed on a tablet or within a capsule and placed within a conducting liquid. The tablet or capsule would then dissolve over a period of time and release the system 100 into the conducting liquid. Thus, in one aspect, the tablet or capsule may contain the system 100 without a pharmaceutical agent or product. Such a capsule, for example, may be used in any environment where a conducting liquid is present and with any product, such as an active pharmaceutical agent, vitamin, placebo, without limitation. In various examples, the capsule or tablet may be dropped into a container filled with jet fuel, salt water, tomato sauce, motor oil, or any similar product. Additionally, the capsule containing the system 100 may be ingested at the same time that a pharmaceutical product is ingested in order to record the occurrence of the event, such as when the product was taken or to trigger any other event.

In the specific example of the system 100 combined with the pharmaceutical product, as the product or pill is ingested, the system 100 is activated. The system 100 controls conductance to produce a unique current signature that is detected, thereby signifying that the pharmaceutical product has been taken. The system 100 includes a framework 102. The framework 102 is a chassis for the system 100 and multiple components are attached to, deposited upon, or secured to the framework 102. In this aspect of the system 100, a digestible first material 104 is physically associated with the framework 102. The material 104 may be chemically deposited on, evaporated onto, secured to, or built-up on the framework all of which may be referred to herein as “deposit” with respect to the framework 102. The material 104 is deposited on one side of the framework 102. The materials of interest that can be used as material 104 include, but are not limited to: Cu or CuI. The material 104 is deposited by physical vapor deposition, electrodeposition, or plasma deposition, among other protocols. The material 104 may be from about 0.05 to about 500 μm thick, such as from about 5 to about 100 μm thick. The shape is controlled by shadow mask deposition, or photolithography and etching. Additionally, even though only one region is shown for depositing the material, each system 100 may contain two or more electrically unique regions where the material 104 may be deposited, as desired.

At a different side, which may be the opposite side as shown in FIG. 1, a digestible second material 106 is deposited, such that the materials 104 and 106 are dissimilar. Although not shown, the different side selected may be the side next to the side selected for the material 104. The scope of the present invention is not limited by the side selected and the term “different side” can mean any of the multiple sides that are different from the first selected side. Furthermore, even though the shape of the system is shown as a square, the shape may be any geometrically suitable shape. The first and second materials 104, 106 are selected such that they produce a voltage potential difference when the system 100 is in contact with conducting liquid, such as body fluids. The materials of interest for material 106 include, but are not limited to: Mg, Zn, or other electronegative metals. As indicated above with respect to the first material 104, the second material 106 may be chemically deposited on, evaporated onto, secured to, or built-up on the framework. Also, an adhesion layer may be necessary to help the second material 106 (as well as the first material 104 when needed) to adhere to the framework 102. Typical adhesion layers for the second material 106 are Ti, TiW, Cr or similar material. Anode material and the adhesion layer may be deposited by physical vapor deposition, electrodeposition or plasma deposition. The second material 106 may be from about 0.05 to about 500 μm thick, such as from about 5 to about 100 μm thick. However, the scope of the present invention is not limited by the thickness of any of the materials nor by the type of process used to deposit or secure the materials to the framework 102.

According to the disclosure set forth, the materials 104, 106 can be any pair of materials with different electrochemical potentials. Additionally, in the embodiments wherein the system 100 is used in-vivo, the materials 104, 106 may be vitamins that can be absorbed. More specifically, the materials 104, 106 can be made of any two materials appropriate for the environment in which the system 100 will be operating. For example, when used with an ingestible product, the materials 104, 106 are any pair of materials with different electrochemical potentials that are ingestible. An illustrative example includes the instance when the system 100 is in contact with an ionic solution, such as stomach acids. Suitable materials are not restricted to metals, and in certain embodiments the paired materials are chosen from metals and non-metals, e.g., a pair made up of a metal (such as Mg) and a salt (such as CuCl or CuI). With respect to the active electrode materials, any pairing of substances—metals, salts, or intercalation compounds—with suitably different electrochemical potentials (voltage) and low interfacial resistance are suitable.

Materials and pairings of interest include, but are not limited to, those reported in Table 1 below. In one aspect, one or both of the metals may be doped with a non-metal, e.g., to enhance the voltage potential created between the materials as they come into contact with a conducting liquid. Non-metals that may be used as doping agents in certain embodiments include, but are not limited to: sulfur, iodine and the like. In another embodiment, the materials are copper iodine (CuI) as the anode and magnesium (Mg) as the cathode. Aspects of the present disclosure use electrode materials that are not harmful to the human body.

TABLE 1

TABLE 1

Anode
Cathode

Metals
Magnesium, Zinc

Sodium (†),

Lithium (†)

Iron

Salts

Copper salts: iodide, chloride, bromide,

sulfate, formate, (other anions possible)

Fe³⁺ salts: e.g. orthophosphate,

pyrophosphate, (other anions possible)

Oxygen (††) on platinum, gold

or other catalytic surfaces

Intercalation
Graphite with Li,
Vanadium oxide Manganese oxide

compounds
K, Ca, Na, Mg

Thus, when the system 100 is in contact with the conducting liquid, a current path, is formed through the conducting liquid between the first and second materials 104, 106. A controller 108 is secured to the framework 102 and electrically coupled to the first and second materials 104, 106. The controller 108 includes electronic circuitry, for example control logic that is capable of controlling and altering the conductance between the materials 104, 106.

The voltage potential created between the first and second materials 104, 106 provides the power for operating the system 100 as well as produces the current flow through the conducting fluid and the system. In one aspect, the system 100 operates in direct current mode. In an alternative aspect, the system 100 controls the direction of the current so that the direction of current is reversed in a cyclic manner, similar to alternating current. As the system 100 reaches the conducting fluid or the electrolyte, where the fluid or electrolyte component is provided by a physiological fluid, e.g., stomach acid, the path for current flow between the materials 104, 106 is completed external to the system 100; the current path through the system 100 is controlled by the controller 108. Completion of the current path allows for the current to flow and in turn a receiver 304 (shown in FIG. 3), can detect the presence of the current and receive the information transmitted/radiated by the system 100. In one aspect, the receiver recognizes that the system 100 has been activated and the desired event is occurring or has occurred.

In one aspect, the two materials 104, 106 may be similar in function to the two electrodes needed for a direct current power source, such as a battery. The conducting liquid acts as the electrolyte needed to complete the power source. The completed power source described is defined by the physical chemical reaction between the materials 104, 106 of the system 100 and the surrounding fluids of the body. The completed power source may be viewed as a power source that exploits reverse electrolysis in an ionic or a conductive solution such as gastric fluid, blood, or other bodily fluids and some tissues. Additionally, the environment may be something other than a body and the liquid may be any conducting liquid. For example, the conducting fluid may be salt water or a metallic based paint.

In certain aspects, the two materials 104, 106 may be shielded from the surrounding environment by an additional layer of material. Accordingly, when the shield is dissolved and the two dissimilar materials 104, 106 are exposed to the target site, a voltage potential is generated.

In certain aspects, the complete power source or supply is one that is made up of active electrode materials, electrolytes, and inactive materials, such as current collectors, packaging, etc. The active materials are any pair of materials with different electrochemical potentials. Suitable materials are not restricted to metals, and in certain embodiments the paired materials are chosen from metals and non-metals, e.g., a pair made up of a metal (such as Mg) and a salt (such as CuI). With respect to the active electrode materials, any pairing of substances—metals, salts, or intercalation compounds—with suitably different electrochemical potentials (voltage) and low interfacial resistance are suitable.

A variety of different materials may be employed as the materials that form the electrodes. In certain aspects, electrode materials are chosen to provide for a voltage upon contact with the target physiological site, e.g., the stomach, sufficient to drive the system of the identifier. In certain embodiments, the voltage provided by the electrode materials upon contact of the metals of the power source with the target physiological site is 0.001 V or higher, including 0.01 V or higher, such as 0.1 V or higher, e.g., 0.3 V or higher, including 0.5 volts or higher, and including 1.0 volts or higher, where in certain embodiments, the voltage ranges from about 0.001 to about 10 volts, such as from about 0.01 to about 10 V.

The first and second materials 104, 106 provide the voltage potential to activate the control device 108. Once the control device 108 is activated or powered up, the control device 108 can alter conductance between the materials 104, 106 in a unique manner. By altering the conductance between materials 104, 106, the control device 108 is capable of controlling the magnitude and the duty cycle of the current through the conducting liquid that surrounds the system 100. This produces a unique current signature that can be detected and measured by the receiver 304 (shown in FIG. 3), which can be positioned internal or external to the body. Information can be communicated by the system 100 in the form of packets until the first and second materials can no longer sustain the power source. In addition to controlling the magnitude of the current path between the materials, non-conducting materials, membrane, or “skirt” are used to increase the “length” of the current path and, hence, act to boost the conductance path, as disclosed in the U.S. patent application Ser. No. 12/238,345 entitled, “In-Body Device with Virtual Dipole Signal Amplification” filed Sep. 25, 2008, the entire content of which is incorporated herein by reference. Alternatively, throughout the disclosure herein, the terms “non-conducting material,” “membrane,” and “skirt” are interchangeably with the term “current path extender” without impacting the scope or the present embodiments and the claims herein. The skirt elements 105, 107 may be associated with, e.g., secured to, the framework 102. Various shapes and configurations for the skirt are contemplated as within the scope of the present invention. For example, the system 100 may be surrounded entirely or partially by the skirt and the skirt maybe positioned along a central axis of the system 100 or off-center relative to a central axis. Thus, the scope of the present disclosure as claimed herein is not limited by the shape or size of the skirt. Furthermore, in other embodiments, the first and second materials 104, 106 may be separated by one skirt that is positioned in any defined region between the materials 104, 106.

Referring now to FIG. 2, a block diagram representation of the controller 108 is shown. The device 108 includes a control module 202, a counter or clock 204, a memory 206, and a logic circuit 208. Additionally, the controller 108 may include one or more sensor modules. The control module 202 has an input 210 electrically coupled to the first material 104 and an output 212 electrically coupled to the second material 106. The control module 202, the clock 204, the memory 206, and the logic circuit 208 (and optionally the sensor modules) also have power inputs (some not shown). The power for each of these components is supplied by the voltage potential produced by the chemical reaction between the first and second materials 104, 106 and the conducting fluid, when the system 100 is in contact with the conducting fluid. The control module 202 controls the conductance through logic that alters the overall impedance of the system 100. The control module 202 is electrically coupled to the clock 204. The clock 204 provides a clock cycle to the control module 202. Based upon the programmed characteristics of the control module 202, when a set number of clock cycles have passed, the control module 202 alters the conductance characteristics between the first and second materials 104, 106. This cycle is repeated and thereby the controller 108 produces a unique current signature characteristic. The control module 202 is also electrically coupled to the memory 206. Both the clock 204 and the memory 206 are powered by the voltage potential created between the first and second materials 104, 106.

As shown in FIG. 3, in one aspect, a logic circuit 208 is provided to monitor the current drain and impedance of the resulting power source or battery formed between the first and second materials when the system is immersed in an ionic fluid. In one aspect, the logic circuit 208, comprising a sample-and-hold and an analog-to-digital converter (ADC), is configured as an automatic calibration algorithm or process to adaptively optimize power dissipation and broadcast power in the resulting power source. In one aspect, and described in more detail hereinbelow, the logic circuit 208 monitors and adjusts the pulse width and current limit of the output of the system 100 in order to stabilize the battery voltage and the duty cycle of the transmitted signal, while optimizing the power delivered to the receiver 304 (shown in FIG. 3). In one aspect, the algorithm may be implemented to sample the value of the battery voltage (V_BATT) during the transmission of a predetermined data packet. In one aspect, adjustments to the pulse width and/or current limit may take effect during the transmission of a subsequent packet, such as, for example, during the transmission of the next data packet. The algorithm settings (starting pulse width, minimum and maximum current limits) may be programmed into the memory 206, such as a non-volatile memory, for example. This programming step may be performed, for example, at the wafer sort stage. In operation, the logic circuit 208 may execute a tune-up or tune-down procedure depending on the state of the battery recovery voltage and battery impedance. The logic circuit 208, including the tune-up and tune-down procedures, is described in more detail hereinbelow with reference to FIGS. 5-7. The logic circuit 208 may be implemented in hardware, software, or a combination thereof. In one aspect, the logic circuit 208 may be implemented either as a processor, state machine, digital signal processor, discrete logic among other implementations, which would be readily apparent to one of ordinary skill in the art. In one aspect, the logic circuit 208 may be embodied in an application specific integrated circuit (ASIC). Thus, the use of the term algorithm or procedure should not necessarily be interpreted as the execution of computer instructions. In one aspect, the logic circuit 208 is powered by the voltage potential created between the first and second materials 104, 106.

FIG. 3 is a block diagram of one aspect of a communication system 300 where an event indicator system 100 is in communication with a receiver 304 over communication link 308. It will be appreciated that the communication link 308 can be a current flow produced by ionic emission or a wireless link, without limitation. In one aspect, the logic circuit 208 is coupled to a battery 302 power source, which is modeled as a voltage source V_BATThaving an internal impedance Z_BATTand output current (i). The logic circuit 208 monitors the output current (i) of the battery 302 and the impedance Z_BATTof the battery 302. In one aspect, the battery 302 is formed when the first and second materials 104, 106 are immersed in an ionic fluid as described in connection with FIGS. 1 and 2. Aspects of a receiver 304 device are disclosed in U.S. Pat. No. 8,114,021 to Robertson et al., titled “Body-associated Receiver and Method,” which is incorporated herein by reference in its entirety.

In one aspect, the logic circuit 208 is configured to execute an automatic calibration algorithm or process to adaptively optimize power dissipation and broadcast power of the event indicator system 100. In one aspect, the controller 202 of the event indicator system 100 outputs a broadcast signal 306 to the receiver 304. The broadcast signal 306 is comprised of a sequence of pulses transmitted at a predetermined frequency (f). The individual pulses of the broadcast signal 306 define a bit of information and a sequence of pulses defines a packet of information. The pulses have a period (T) and a pulse width (w) during which time the output signal is active. The inverse of the pulse period (T) is the frequency of the broadcast signal 306. The pulses may be transmitted at a predetermined duty cycle, which is defined as the ratio of the pulse width (w) and the period (T).

f=1/T Hz
Duty Cycle=w/T

In one aspect, the controller 202 may transmit a broadcast signal 306 comprising a first packet of information, where the first packet comprises a predetermined number of pulses m (e.g., m bits of information) at a first frequency f₁. In one aspect, the controller 202 may transmit multiple first packets comprising the predetermined number of bits at the first frequency f₁. At some time later, the controller 202 may start broadcasting a second packet of information, where the second packet comprises a predetermined number of pulses n (e.g., n bits of information) at a second frequency f₂. In one aspect, the series of first packets at f₁are broadcast to the receiver 304 at just enough power to wake up the receiver 304. The actual data or information associated with the event indicator system 100 is broadcast via the second aeries of packets at f₂. Thus, once the receiver 304 detects the first packets, it prepares to receive the data broadcast via the second packets.

The first frequency f₁may be any predetermined frequency and in one aspect may be any frequency from about 10 to about 30 kHz and more preferably about 20 kHz. The second frequency f₂may be any predetermined frequency and in one aspect may be any frequency from about 10 to about 15 kHz and more preferably about 12½ kHz.

In one aspect, the event indicator system 100 may broadcast a predetermined number of packets, for example, three to six packets or more, at the first frequency f₁to delay the broadcast time between a packet at the first frequency f₁and a packet at the second frequency f₂, or by changing the time interval between packets to avoid transmission collisions. Likewise, in one aspect, the event indicator system 100 may broadcast a predetermined number of packets, for example, three to six packets or more, at the second frequency f₂to avoid transmission collisions. It will be appreciated, however, that the number of repeated packet transmissions at first or second frequency f₁, f₂may be determined statistically based on the number of event indicator systems 100 ingested by the patient.

In one aspect, as described in more detail hereinbelow, the logic circuit 208 monitors and adjusts the pulse width (w) of the controller 202 output and the current (i) limit of a broadcast signal 306 generated by the event indicator system 100 in order to stabilize the battery voltage V_BATTand the duty cycle of the broadcast signal 306 pulses, while optimizing the power delivered to the receiver 304. In one aspect, the logic is configured to sample the battery voltage V_BATTduring the broadcast transmission of a predetermined data packet by the controller 202. In one aspect, adjustments to the pulse width (w) and/or current (i) limit may be determined for a current packet broadcast and may be applied to a subsequent packet, such as, for example, during the broadcast transmission of the next data packet. The algorithm settings such as, for example, starting pulse width (w_o), minimum current (i_min), and maximum current (i_max) limits may be programmed into the memory 206 (FIG. 2), such as a non-volatile memory, for example. This programming step may be performed, for example, at the wafer sort stage.

In one aspect the minimum current i_minis about 1 mA and the maximum current i_maxis about 4 mA. In one aspect, the minimum duty cycle DC_minis about 15% and the maximum duty cycle DC_maxis about 50%. These values are merely examples, and the present system should not be limited in this context.

In operation, the logic circuit 208 may execute a tune-up or tune-down procedure depending on the state of the battery 302 recovery voltage V_BATTand impedance Z_BATT. The logic circuit 208, including the tune-up and tune-down procedures, is described in more detail hereinbelow with reference to FIGS. 5-7.

The logic circuit 208 may be implemented in hardware, software, or a combination thereof. In one aspect, the logic circuit 208 may be implemented either as a processor, digital signal processor, discrete logic, or state machine, among other implementations, which would be readily apparent to one of ordinary skill in the art. In one aspect, the logic circuit 208 may be embodied in an application specific integrated circuit (ASIC). Thus, the use of the term algorithm or procedure should not necessarily be interpreted as the execution of computer instructions.

Although the aspects illustrated in connection with FIGS. 1-3, the logic circuit 208 is described in connection with adaptively optimizing power dissipation and broadcast power in a power source created between the first and second materials 104 and 106, the logic circuit 208 is not limited in this context. For example, the logic circuit 208 may be configured to adaptively optimize power dissipation and broadcast power in any energy source, such as, a conventional battery.

The receiver 304 may further employ a beacon functionality module. In various aspects, a beacon switching module may employ one or more of the following: a beacon wakeup module, a beacon signal module, a wave/frequency module, a multiple frequency module, and a modulated signal module.

The beacon switching module may be associated with beacon communications, e.g., a beacon communication channel, a beacon protocol, etc. For the purpose of the present disclosure, beacons are typically signals sent by the controller 108 either as part of a message or to augment a message (sometimes referred to herein as “beacon signals”). The beacons may have well-defined characteristics, such as frequency. Beacons may be detected readily in noisy environments and may be used for a trigger to a sniff circuit, such as described below.

In one aspect, the beacon switching module may comprise the beacon wakeup module, having wakeup functionality. Wakeup functionality generally comprises the functionality to operate in high power modes only during specific times, e.g., short periods for specific purposes, to receive a signal, etc. An important consideration on a receiver portion of a system is that it be of low power. This feature may be advantageous in an implanted receiver, to provide for both small size and to preserve a long-functioning electrical supply from a battery. The beacon switching module enables these advantages by having the receiver operate in a high power mode for very limited periods of time. Short duty cycles of this kind can provide optimal system size and energy draw features.

In practice, the receiver 304 may “wake up” periodically, and at low energy consumption, to perform a “sniff function” via, for example, a sniff circuit. It is during this period that the receiver 304 detects the first packet at the first frequency f₁. For the purpose of the present application, the term “sniff function” generally refers to a short, low-power function to determine if a transmitter, e.g., the communication system 100, is present. If a communication system 100 broadcast signal 306 is detected by the sniff function, the receiver 304 may transition to a higher power communication decode mode. If a communication system 100 broadcast signal 306 is not present, the receiver 304 may return, e.g., immediately return, to sleep mode. In this manner, energy is conserved during relatively long periods when a transmitter signal is not present, while high-power capabilities remain available for efficient decode mode operations during the relatively few periods when a broadcast signal 306 is present. Several modes, and combination thereof, may be available for operating the sniff circuit. By matching the needs of a particular system to the sniff circuit configuration, an optimized system may be achieved.

FIG. 4A illustrates a diagram 400 where a beacon switching module wherein a sniff period 401 is longer than a broadcast signal 306 (FIG. 3) repetition period 403. The time function is provided on the horizontal axis. As shown, the broadcast signal 306 repeats periodically at a repetition period of 403, with a sniff function also running. In practice, effectively, the sniff period 401 may be longer than the broadcast signal 306 repetition period 403. In various aspects, there may be a relatively long period of time between the sniff periods. In this way, the sniff function, e.g., implemented as a sniff circuit, is guaranteed to have at least one transmission to occur each time the sniff circuit is active.

FIG. 4B illustrates a diagram 410 where the beacon switching module provides a short but frequent sniff period 405 and a long transmit packet 407 are provided. The sniff circuit will activate at some point during the transmit time. In this manner, the sniff circuit may detect the transmit signal and switch into a high power decode mode.

An additional beacon wakeup aspect is to provide the “sniffing” function in a continuous mode. This aspect of the transbody beacon transmission channel may exploit the fact that the total energy consumption is the product of average power consumption and time. In this aspect, the system may minimize the total energy consumption by having very short periods of activity, in which case the periods of activity are averaged down to a small number. Alternately, a low continuous sniff activity is provided. In this case, the configuration provides a sufficiently low power so that the transmission receiver runs continuously with total energy consumption at an appropriate level for the parameters of a specific system.

In one aspect, the sniff module of the receiver 304 is configured to scan for data encoded by the controller 202 in current flow produced by ionic emission. The data is received at the receiver 304 as a conductive signal at a set schedule, e.g., every 20 seconds. The period during active sniff is limited, e.g., 300 msec. This relatively low duty-cycle allows for lower average power functionality for extended system life. The receiver 304 determines if a broadcast signal 306 is present and if that broadcast signal 306 has a valid ID. If no signal having a valid ID is detected during active sniff, the active sniff is turned off until the next predetermined active period. If a broadcast signal 306 having a valid ID is received, the receiver 304 determines if the signal 306 received is from a previously detected ionic transmitter. If the broadcast signal 306 is from a previously detected ionic transmitter, the receiver 304 determines whether the count (in other words, individual valid detections of the same ID) in the current wake up cycle (specified time since the last reported ID, such as 10 minutes) is greater than a specified number (such as 50) as measured by a threshold counter. If the count exceeds this threshold as determined by the threshold counter the receiver 304 returns to sniff mode. If the count does not exceed the threshold value, the receiver operates in 100% detection mode to analyze the received data encoded in the current flow by the ionic emission. Once the received data is decoded and analyzed, the receiver 304 determines that the data encoded in the current flow is coming from a different valid source than previously detected, then the threshold counter is reset.

In another aspect, the incoming broadcast signal 306 to the receiver 304 represents the signals received by electrodes, bandpass filtered (such as from 10 KHz to 34 KHz) by a high frequency signaling chain (which encompasses the carrier frequency), and converted from analog to digital. The broadcast signal 306 is then decimated and mixed at the nominal drive frequency (such as, 12.5 KHz, 20 KHz, etc.) at a mixer. The resulting signal is decimated and low-pass filtered (such as 5 KHz BW) to produce the carrier signal mixed down to carrier offset-signal. The carrier offset-signal is further processed (fast Fourier transform and then detection of two strongest peaks) to provide the true carrier frequency signal. This protocol allows for accurate determination of the carrier frequency of the transmitted beacon.

Having described in FIGS. 1-4, a general ingestible device system 100 in which the apparatus, system, and method to adaptively optimize power dissipation and broadcast power in a battery 302 may be practiced, the present disclosure now turns to a description of a flow diagram illustrating one aspect of a process for an automatic calibration decision logic 500 as shown in FIG. 5. The automatic calibration decision logic 500 can be implemented by the logic circuit 208. Accordingly, the automatic calibration decision logic 500 will be described with reference to FIGS. 1-5. During a broadcast cycle by the communication system 100, it is desirable to optimize the broadcast signal 306 while minimizing the charge removed from the battery 302 using one aspect of the procedure described in FIG. 5. The broadcast signal 306 may be optimized by controlling the combination of current (i) and pulse width (w) during a broadcast cycle, and balancing the output charge against a pre-determined battery 302 recovery voltage V_BATT-RECor battery impedance Z_BATTmeasurement.

In one aspect, this may be accomplished by a “tune-up” and “tune-down” process or algorithm as described in connection with FIGS. 6 and 7. During the tune-up phase the current (i) or pulse width (w) of the broadcast cycle is increased until the pre-determined battery 302 recovery voltage V_BATT-RECor battery impedance Z_BATThas been obtained. This step is then increased by one to ensure that the battery 302 voltage V_BATTis greater than the battery 302 recovery voltage V_BATT-REC. The “tune-down” phase is then entered whereby the other parameter, current (i) or pulse width (w) of the broadcast cycle is decreased until the predetermined battery 302 recovery voltage V_BATT-RECor battery impedance Z_BATTis once again detected. This combination of broadcast current (i) and pulse width (w) is then stored in memory and used during a single broadcast cycle of a subsequent packet, e.g., the next packet.

In one aspect, the process of determining the battery 302 recovery voltage V_BATT-RECor battery impedance Z_BATTis accomplished by sampling the recovery voltage V_BATT-RECof the battery 302 during a non broadcast cycle, and performing an average value calculation on the result. In addition, a starting value of current (i) and pulse width (w), as well as a maximum value of current (i) and pulse width (w) may be utilized by the optimization process to ensure that the minimum and maximum broadcast parameters are not violated.

During conventional transmission of broadcast signal 306, all the power of the battery 302 is exploited by essentially shorting the battery 302. This leads to a longer recovery time and faster discharge rate for the battery 302. In one aspect, the automatic calibration decision logic 500 provides a method for adaptively optimizing dissipation and broadcast power to extend the life of the battery 302 while still providing enough broadcast power to the controller 202 for suitable detection by the receiver 304. In one aspect, the automatic calibration decision logic 500 may be implemented by the logic circuit 208. Accordingly, with reference now to FIG. 5, one aspect of an automatic calibration decision logic 500. In one aspect, the automatic calibration decision logic 500 may be employed to adjust the pulse width (w) and current (i) limit of the broadcast signal 306 output by the controller 202 in order to stabilize the battery voltage V_BATTand the duty cycle of the broadcast signal 306, while optimizing the power delivered to the receiver 304. In one aspect, the logic 500, samples the value of V_BATTduring a data packet transmission. In one aspect, the data packet transmission may be a 20 kHz data packet. Adjustments to the pulse width (w) and/or current (i) limit take effect starting with a subsequent data packet, such as, for example, the next data packet. In one aspect, the logic 500 settings (starting pulse width, minimum and maximum current limit) are programmable in the non-volatile memory 206 (FIG. 2) at wafer sort.

With reference now to FIGS. 3 and 5, at 502, the automatic calibration decision logic 500, e.g., the logic circuit 208, waits for the next available broadcast packet in order to characterize the battery voltage V_BATTand impedance Z_BATT. At decision block 504, the logic circuit 208 determines whether the last broadcast packet is in the transmission queue. If no, the logic 500 process continues along the No branch and waits for the last packet. If yes, the logic 500 process continues along the Yes branch. At 506, the logic circuit 208 samples the battery 302 voltage V_BATTand counts using a counter, e.g., determines, the number of cycles in which the sampled battery voltage (V_CAP) is less than a nominal battery voltage (V_BATT_—_NOM), e.g., V_CAP<V_BATT_—_NOM, from the i_thbit to the j_thbit of the broadcast packet. At decision block 508, the logic circuit 208 determines whether the sampled voltage V_CAPis less than the nominal battery voltage V_BATT_—_NOMfor more than half the cycles between the i_thand j_thbit of the broadcast packet. The sampled battery voltage (V_CAP) may be determined by the logic circuit 208 using, for example, the sample-and-hold circuit and an ADC, much like the sample-and-hold circuit 808 and analog-to-digital converter 812 shown and described in connection with FIG. 8, for example. Accordingly, in one aspect, the logic circuit 208 may be configured to employ internal or external sample-and-hold circuit and analog-to-digital converter circuits to sample the battery voltage.

When the sampled voltage V_CAPis less than the nominal battery voltage V_BATT_—_NOMfor more than half the cycles between the i_thand j_thbit of the broadcast packet, the logic 500 process continues along the Yes branch to the “tune-down” process 700, which is described in connection with FIG. 7. Briefly, during the “tune-down” 700 process, the current (i) or pulse width (w) of the broadcast cycle is decreased until the predetermined battery 302 recovery voltage V_BATT-RECor battery impedance Z_BATTis once again detected.

When the sampled voltage V_CAPis less than the nominal battery voltage V_BATT_—_NOMfor less than half the cycles between the i_thand j_thbit of the broadcast packet, the logic 500 process continues along the No branch to decision block 510 to determine the operating mode.

In one aspect, the logic 500 can be configured to operate on X-bit multiple cycle operating mode or a Y-bit single cycle operating mode. When operating in the X-bit multiple cycle mode, at 512 the logic circuit 208 count the number of cycles in which the sampled voltage is less than the nominal battery voltage, e.g., V_CAP<V_BAT_—_NOM, from the (j+1)_thbit to the k_thbit. Otherwise, at 514 the logic circuit 208 counts the number of cycles in which V_CAP<V_BAT_—_NOMfrom the (k+1)_thbit to the 6 bit. After counting such number of cycles, at decision block 516 the logic 500 determines whether the sampled voltage V_CAPis greater than the nominal battery voltage V_BATT_—_NOM, e.g., V_CAP<V_BAT_—_NOM, for more than half the cycles. When the sampled voltage V_CAPis not greater than the nominal battery voltage V_BATT_—_NOM, e.g., V_CAP<V_BAT_—_NOM, for more than half the cycles, the logic continues along No branch to 502, where it waits for a new broadcast packet and the process begins anew.

Accordingly, the process 500 determines a predetermined threshold of where the battery 302 should operate. For example, in one example, as long as the battery 302 voltage is about 1V and recovers to about 1V, then the system 300 is likely to operate within design parameters. Decision logic for automatic calibration tune-up and tune-down processes, as described hereinbelow in connection with FIGS. 6 and 7, are employed to change both the current (i) that is delivered by the battery 302 and the pulse width (w) of the broadcast signal 306 to optimize the total charge being delivered by the battery 302.

FIG. 6 illustrates one aspect of a decision logic 600 for an automatic calibration tune-up process. In one aspect, the decision logic 600 may be implemented by the circuit 208, for example. When the automatic calibration decision logic 500 process passes to the tune-up decision logic 600 portion of the automatic calibration process, at decision block 602, the decision logic 600 determines whether the battery 302 current (i) is at a maximum current limit (i_max). When the battery 302 current (i) is at the maximum current limit (i_max), the logic 600 process continues along Yes branch to decision block 604, where it determines whether a bit of the broadcast signal 306 pulse width (w) is at the maximum pulse width (w_max). When the pulse width (w) is less than the maximum pulse width (w_max) (w<w_max), at 610, the logic 600 process increases the pulse width (w) by a predetermined increment value. In one aspect, the f₁frequency increment value is about 2 μs, and may be selected from the range of about 7.5 μs to about 25 μs, for example. When the pulse width (w) is at the maximum pulse width (w_max) (w=w_max), at 612 the logic 600 process takes no action.

When the battery 302 current (i) is not at the maximum current limit (i_max), the logic 600 process continues along No branch to decision block 606, where it determines whether the battery current (i) is at the minimum current (i_min) limit, which is predetermined by a value stored in non-volatile memory, for example, about 1 mA. When the battery 302 current (i) is not at the minimum current limit (i_min), the logic 600 process continues along No branch to 608 to set the pulse width to default to increase current limit. When the battery 302 current (i) is at the minimum current limit (i_min), the logic 600 process continues along Yes branch to decision block 614 to determine whether the pulse width (w) is set to the default pulse width value. When the pulse width (w) is not set to the default pulse width value, the logic 600 process proceeds along No branch to 616 to increase the pulse width by a predetermined pulse width increment value. In one aspect, the predetermined pulse width increment value is about 2 μs. When the pulse width (w) is set to the default pulse width value, the logic 600 process proceeds along Yes branch to 618 to increase the current (i) limit by a predetermined current increment value. In one aspect, the predetermined current increment value is about 200 μA and may be selected from the range of about 200 μA to about 4 mA, for example.

FIG. 7 illustrates one aspect of a decision logic 700 for an automatic calibration tune-down process. In one aspect, the decision logic 700 may be implemented by the circuit 208, for example. When the automatic calibration decision logic 500 process passes to the tune-down decision logic 700 portion of the automatic calibration process, at decision block 702, the decision logic 700 determines whether the battery 302 current (i) is at a minimum current limit (i_min). When the battery 302 current (i) is at the minimum current limit (i_min), the logic 700 process continues along Yes branch to decision block 704, where it determines whether a bit of the broadcast signal 306 pulse width (w) is at the minimum pulse width (w_min). When the pulse width (w) is greater than the minimum pulse width (w_max) (w>w_max), at 710, the logic 700 process decreases (reduces) the pulse width (w) by a predetermined decrement value. In one aspect, the f₁frequency decrement value is about 2 μs and may be selected from the range of about 7.5 μs to about 25 μs, for example. When the pulse width (w) is at the minimum pulse width (w_min) (w=w_min), at 712 the logic 700 process takes no action.

When the battery 302 current (i) is not at the minimum current limit (i_max), the logic 700 process continues along No branch to decision block 706 to determine whether the battery current (i) is at the maximum current (i_max) limit of about 4 mA. When the battery 302 current (i) is not at the maximum current limit (i_max), the logic 700 process continues along No branch to 708 to set the pulse width to default to reduce the current limit. When the battery 302 current (i) is at the maximum current limit (i_max), the logic 700 process continues along Yes branch to decision block 714 to determine whether the pulse width (w) is set to the default pulse width value. When the pulse width (w) is not set to the default pulse width value, the logic 700 process proceeds along No branch to 716 to decrease or reduce the pulse width by a predetermined pulse width decrement value. In one aspect, the predetermined pulse width decrement value is about 2 μs and may be selected from the range of about 7.5 μs to about 25 μs, for example. When the pulse width (w) is set to the default pulse width value, the logic 700 process continues along Yes branch to 718 to decrease or reduce the current (i) limit by a predetermined current decrement value. In one aspect, the predetermined current decrement value is about 200 μA and may be selected from the range of about 200 μA to about 4 mA, for example.

Embodiment 2

With reference now to FIG. 8, in another aspect, the present disclosure is directed generally to an apparatus, system, and method to determine the availability of battery power prior to the ingestible communication device entering a high current draw mode of operation. For ingestible device, such as IEM, operations, where the impedance Z_BATTof the battery 802 is determined by the amount of material dissolution over time, and could vary by a factor of ten or more, it may be desirable to know that the battery 802 is capable of sustaining a predetermined current draw prior to performing broadcast communication operations. One example of this type of operation is the reading or programming of a non volatile memory, whereby a failure of the reading or writing of that memory would result in non-operation or incorrect operation of the IEM.

In one aspect, a battery availability determination circuit 800 maybe employed to determine the availability of battery power prior to the ingestible communication device entering a high current draw mode of operation. In one aspect, the battery availability determination circuit 800 comprises a power on reset control logic circuit 822 and a low power ADC 812 are used to determine the impedance Z_BATTof the battery 802. The power on reset control logic circuit 822 is configured to control the operation of first and second analog switches 818, 820 to connect either a first, second, or third load resistance R1, R2, or R3, respectively, in parallel with the battery 802. A voltage 806 developed across each resistor R1, R2, R3, is coupled into an input 804 of a sample-and-hold (S/H) circuit 808. The output 810 of the S/H circuit 808 is coupled to and measured by the ADC 812. The measured battery voltage (Vb_meas) output 814 of the ADC 812 is coupled to the logic circuit 208 (FIG. 3) of the communication system 300 (FIG. 3) for calculating the impedance Z_BATTof the battery 802 based on two out three of the voltage measurements. A reference voltage 816 (V_REF) may be provided internal or external to the ADC 812.

The operation of the battery availability determination circuit 800 is as follows. The power on reset control logic circuit 822 receives a power on reset signal 832 and detects a point when the battery 802 has reached a pre-determined voltage and current capacity. At this point in time, the ADC 812 is enabled and performs the following measurements. A first known resistor R1 of typical value is connected from the battery 802 to ground by a first analog switch 818 via control 826 and the battery voltage across the first resistor R1 is measured by the ADC 812 by way of the S/H circuit 808. The measured battery voltage Vb_meas1is then provided to the logic circuit 208 (FIG. 3). A typical value for the first known predetermined resistor R1 is about 1.5 kΩ and may be selected from the range of about 1.275 kΩ to about 1.725 kΩ, or 1.5 kΩ±15%, for example.

A second known resistor R2 of high value is connected from the battery 802 to ground by a second analog switch 820 via control 824 and the battery voltage developed across the second resistor R2 is measured by the ADC 812 by way of the S/H circuit 808. The measured battery voltage Vb_meas2is then provided to the logic circuit 208 (FIG. 3). A typical value for the second known predetermined resistor R2 is about 15 kΩ and may be selected from the range of about 12.75 kΩ to about 17.25 kΩ, or 15 kΩ±15%, for example.

A third known resistor R3 of low value is connected from the battery 802 to ground by a third analog switch 828 via control 830 and the battery voltage developed across the third resistor R3 is measured by the ADC 812 by way of the S/H circuit 808. The measured battery voltage Vb_meas3is then provided to the logic circuit 208 (FIG. 3). A typical value for the third known predetermined resistor R3 is about 1Ω and may be selected from the range of about 0.85Ω to about 1.15Ω, or 1Ω±15%, for example.

The values of the high value resistor R2 and the low value resistor R3 may be chosen such that the resultant voltage across either of the resistors R2, R3 will within the ADC 812 measurement range for the battery 802 impedances V_BATTbeing considered. By using two of the three measured battery voltage, Vb_meas1(1.5 kΩ), Vb_meas2(15 kΩ), and Vb_meas3(1Ω) values, the battery impedance is calculated in accordance with the following formula, which employs Vb_meas1and Vb_meas2, for example.

$Z_{BATT} = \frac{{Vb}_{meas 1} - {Vb}_{meas 2}}{\frac{{VB}_{meas 2}}{R 1} - \frac{{VB}_{meas 1}}{R 2}}$

For Vb_meas2and Vb_meas3, the formula is:

$Z_{BATT} = \frac{{Vb}_{meas 3} - {Vb}_{meas 2}}{\frac{{VB}_{meas 2}}{R 3} - \frac{{VB}_{meas 3}}{R 2}}$

For Vb_meas1and Vb_meas3, the formula is:

$Z_{BATT} = \frac{{Vb}_{meas 3} - {Vb}_{meas 1}}{\frac{{VB}_{meas 1}}{R 3} - \frac{{VB}_{meas 3}}{R 1}}$

When the impedance Z_BATTof the battery 802 is within acceptable parameters, the high current operation of the battery 802 is enabled, when the battery impedance Z_BATTis outside of this range, however, the communication circuit 300 (FIG. 3) (e.g., the IEM) will return to a sleep state and wake up after a predetermined amount of time, or at another occurrence of the power on reset signal 832.

Embodiment 3

With reference now to FIG. 9, in another aspect, the present disclosure is directed generally to an apparatus, system, and method for integrated circuits using the substrate as a negative terminal. It is not uncommon for complementary metal oxide semiconductor (CMOS) devices using P type starting material to have their substrate referenced to the most negative potential of the system. For an ingestible device, such as IEM, this substrate connection forms the negative terminal of the power source, while the top of the semiconductor wafer is connected to the positive terminal of the power source. Given this configuration, it may difficult to provide a negative terminal connection on the top side of the wafer due to the possibility of either shorting the positive terminal during power source activation, or causing increased leakage currents between the two terminals. This difficulty in providing a negative terminal on the top side of the wafer and relying on the substrate connection only, may cause measurement inaccuracies at wafer sort test due to the impedance from the substrate to the on chip circuits connected to the negative terminal. Accordingly, in one aspect, a negative terminal connection is provided that can be placed on the top side of the wafer that is activated only during test modes and is left in a high impedance state during all other modes of operation.

Accordingly, in one embodiment, FIG. 9 illustrates a circuit diagram 900 for providing a negative terminal connection that can be placed on the top side of a wafer that is activated only during test modes and is left in a high impedance state during all other modes of operation. As illustrated in FIG. 9, a test logic 902 circuit has a test detect input channel and an output channel 906 coupled to the gate terminal of an N-channel field effect transistor device 910. The drain terminal of the N-channel device 910 is coupled to the V_SSPAD of a P-channel semiconductor wafer through a probe needle. The source terminal of the N-channel device 910 is coupled to the negative substrate 912 of the semiconductor integrated circuit (IC) and provides an internal connection to the substrate. The IC is first powered with the substrate 912 being the negative terminal. A test mode can be entered by applying the correct voltages and frequency signature to a test enable pin 904 of the test logic 902. Once in the test mode, a signal is activated that enables the N-channel device 901 with a lower ON resistance than the substrate 912 resistance to redirect the current flow through the N-channel device 910 rather than the substrate 912 connection.

Embodiment 4

The present disclosure also is directed generally to an apparatus, system, and method to separate the power source from the broadcast power source in an ingestible device, such as an IEM. In a typical architecture, the power source of an IEM is shared between the digital circuits, analog circuits and I/O circuits. This sharing of the power source results in additional circuitry to: (1) disconnect the shared power source from the analog and digital circuits prior to broadcast as to not affect their operation; (2) store enough charge on storage device so that the analog and digital circuits remain operational during the time the power source is disconnected from these circuits; and (3) connect only to the broadcast circuits, connect the power source to the analog and digital circuits after the broadcast cycle has completed and only when the power source has recovered to a voltage equal to or greater than the potential on the storage device. Accordingly, in one aspect, the present disclosure provides a method whereby the IEM power source can be physically separated into multiple power sources of predetermined values allowing the removal of the charge storage device. In another aspect, the present disclosure provides an architecture to de-sensitize the digital and analog circuits from any coupling effect that the close proximity of one power source to another may cause.

Accordingly, in one aspect the present disclosure describes a method whereby the IEM power source can be physically separated into multiple power sources of predetermined values allowing the removal of the charge storage device. In addition, the present disclosure provides an architecture that is utilized to de-sensitize the digital and analog circuits from any coupling effect that the close proximity of one power source to another may cause.

In one aspect, a method is provided whereby a single IEM power source is divided into multiple smaller power sources. By controlling the area of the positive electrode, it is possible to control the available charge that can be supplied to the circuits connected to that electrode. Further, using a low drop out voltage regulator whose input is connected to one of the power sources and whose output is connected to the analog or digital circuits to be controlled by that power source, and is lower in potential than the power source, any intermittent effects of one power source coupling to another power source can be minimized.

It is also possible to electrically connect and/or disconnect two or more of the power sources to accommodate differing power requirements of the analog and digital circuits. As an example, if one power source has the primary function to power the broadcast circuits, and the second power source has the primary function to power all analog and digital circuits during the broadcast cycle, then one could through a switch, connect both power sources together during non broadcast cycles allowing the analog and digital circuits additional capacity to perform functions that may exceed the capacity of the second power source if used by itself.

Some aspects of the functional modules described in this disclosure may be implemented, for example, using a machine-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the aspects. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software. The machine-readable medium or article may include, for example, any suitable type of memory, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disk Read Only Memory (CD-ROM), Compact Disk Recordable (CD-R), Compact Disk Rewriteable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, universal serial bus (USB) flash drive, various types of Digital Versatile Disk (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, such as C, C++, Java, BASIC, Perl, Matlab, Pascal, Visual BASIC, arrangement language, machine code, and so forth.

While various details have been set forth in the foregoing description, it will be appreciated that the various aspects of the apparatus, system, and method to adaptively optimize power dissipation and broadcast power in a power source for a communication device may be practiced without these specific details. For example, for conciseness and clarity selected aspects have been shown in block diagram form rather than in detail. Some portions of the detailed descriptions provided herein may be presented in terms of instructions that operate on data that is stored in a computer memory. Such descriptions and representations are used by those skilled in the art to describe and convey the substance of their work to others skilled in the art. In general, an algorithm refers to a self-consistent sequence of steps leading to a desired result, where a “step” refers to a manipulation of physical quantities which may, though need not necessarily, take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It is common usage to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. These and similar terms may be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

Unless specifically stated otherwise as apparent from the foregoing discussion, it is appreciated that, throughout the foregoing description, discussions using terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

It is worthy to note that any reference to “one aspect,” “an aspect,” “one embodiment,” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, appearances of the phrases “in one aspect,” “in an aspect,” “in one embodiment,” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more aspects.

Some aspects may be described using the expression “coupled” and “connected” along with their derivatives. It should be understood that these terms are not intended as synonyms for each other. For example, some aspects may be described using the term “connected” to indicate that two or more elements are in direct physical or electrical contact with each other. In another example, some aspects may be described using the term “coupled” to indicate that two or more elements are in direct physical or electrical contact. The term “coupled,” however, also may mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Aspects of the invention are also defined in the following clauses.

Clause 1. A method of stabilizing battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet, the method comprising:

receiving, by a logic circuit, a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller;

determining, by the logic circuit, a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; and

performing a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

Clause 2. The method of clause 1, comprising:

performing a tune-up procedure when the sampled battery voltage is greater than the nominal battery voltage for more than one half of a total number of cycles counted; and

performing a tune-down procedure when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of a total number of cycles counted.

Clause 3: The method of clause 1 or 2, comprising determining, by the logic circuit, an operating mode, wherein the operating mode is either an X-bit multiple cycle operating mode or a Y-bit single cycle operating mode when the number of cycles in which the sampled battery voltage is not less than the nominal battery voltage for more than one half of a total number of cycles counted.

Clause 4: The method of clause 3, comprising determining, by the logic circuit, the number of cycles over a second subset of the predetermined number of bits of the broadcast packet in which the sampled battery voltage is greater than the nominal battery voltage.

Clause 5: Method of clause 4, comprising determining, by the logic circuit, whether the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet; preferably further comprising:

waiting, by the logic circuit, for a subsequent broadcast packet when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet; and

performing the tune-up procedure when the number of cycles in which the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet.

Clause 6: The method of any of the preceding clauses, comprising determining, by the logic circuit, the number of cycles over a third subset of the predetermined number of bits of the broadcast packet in which the sampled battery voltage is greater than the nominal battery voltage, preferably comprising determining, by the logic circuit, whether the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet, the method preferably comprising:

waiting, by the logic circuit, for a subsequent broadcast packet when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet; and

performing the tune-up procedure when the number of cycles in which the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet.

Clause 7: The method of any of the preceding clauses, wherein the tune-up procedure, comprises:

determining, by a logic circuit, whether a battery current as defined by a predetermined programmable value is at a maximum current limit;

determining, by the logic circuit, whether the battery current is at a minimum current limit when the battery current is less than the maximum current limit;

determining, by the logic circuit, whether a bit of the broadcast packet has a default pulse width when the battery current is at the minimum current limit; and

increasing the pulse width when the pulse width is not at the default pulse width; and

increasing the current limit when the pulse width is at the default pulse width, preferably comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the minimum current limit and/or comprising:

determining, by the logic circuit, whether the pulse width is at a maximum pulse width when the battery current is at the maximum current limit; and

increasing, by the logic circuit, the pulse width when the pulse width is not at a maximum pulse width.

Clause 8: The method of clause 7, comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the minimum current limit and/or:

determining, by the logic circuit, whether the pulse width is at a maximum pulse width when the battery current is at the maximum current limit; and

increasing, by the logic circuit, the pulse width when the pulse width is not at a maximum pulse width.

Clause 9: The method of any of the preceding clauses, wherein the tune-down procedure, comprises:

determining, by a logic circuit, whether a battery current is at a minimum current limit;

determining, by the logic circuit, whether the battery current is at a maximum current limit when the battery current is less than the minimum current limit;

determining, by the logic circuit, whether a bit of the broadcast packet has a default pulse width when the battery current is at the maximum current limit; and

decreasing the pulse width when the pulse width is not at the default pulse width; and

decreasing the current limit when the pulse width is at the default pulse width.

Clause 10: The method of clause 9, comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the maximum current limit and/or determining, by the logic circuit, whether the pulse width is at a minimum pulse width when the battery current is at the minimum current limit; and reducing, by the logic circuit, the pulse width when the pulse width is not at a minimum pulse width.

Clause 11: A logic circuit configured to stabilize battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet, the logic circuit comprising a processor configured to:

receive a broadcast packet having a predetermined number of bits for communication to a receiver located remotely from the controller;

determine a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; and

perform a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

Clause 12: The logic circuit of clause 11, comprising:

a sample-and-hold circuit; and

an analog-to-digital converter, each coupled to the processor and the battery;

wherein the analog-to-digital converter samples the battery voltage to determine the sampled battery voltage,

wherein the logic circuit preferably comprises a battery coupled to the processor.

Clause 13: The logic circuit of clause 11 or 12, wherein the logic circuit is configured to perform the method as defined in any of clauses 1-10.

Clause 14: A communication system comprising a logic circuit according to any of clauses 11-13, wherein the battery device is an event indicator system,

the event indicator system comprising dissimilar metals positioned on opposite ends, wherein the event indicator is configured to generate a voltage potential when the dissimilar metals positioned on opposite ends dissolve in a conducting fluid.

Clause 15: The communication system of clause 14, comprising:

a sample-and-hold circuit; and

an analog-to-digital converter, each coupled to the processor and the event indicator;

wherein the analog-to-digital converter is to sample the voltage potential to determine the sampled battery potential.

While certain features of the aspects have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the aspects.

Claims

1. A method of stabilizing battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet, the method comprising: receiving, by a logic circuit, a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller;determining, by the logic circuit, a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; andperforming a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.
2. The method of claim 1, comprising: performing a tune-up procedure when the sampled battery voltage is greater than the nominal battery voltage for more than one half of a total number of cycles counted; andperforming a tune-down procedure when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of a total number of cycles counted.
3. The method of claim 1, comprising determining, by the logic circuit, an operating mode, wherein the operating mode is either an X-bit multiple cycle operating mode or a Y-bit single cycle operating mode when the number of cycles in which the sampled battery voltage is not less than the nominal battery voltage for more than one half of a total number of cycles counted.
4. The method of claim 3, comprising determining, by the logic circuit, the number of cycles over a second subset of the predetermined number of bits of the broadcast packet in which the sampled battery voltage is greater than the nominal battery voltage.
5. The method of claim 4, comprising determining, by the logic circuit, whether the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet.
6. The method of claim 5, comprising: waiting, by the logic circuit, for a subsequent broadcast packet when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet; andperforming the tune-up procedure when the number of cycles in which the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet.
7. The method of claim 3, comprising determining, by the logic circuit, the number of cycles over a third subset of the predetermined number of bits of the broadcast packet in which the sampled battery voltage is greater than the nominal battery voltage.
8. The method of claim 7, comprising determining, by the logic circuit, whether the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet.
9. The method of claim 8, comprising: waiting, by the logic circuit, for a subsequent broadcast packet when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet; andperforming the tune-up procedure when the number of cycles in which the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet.
10. The method of claim 1, wherein the tune-up procedure, comprises: determining, by a logic circuit, whether a battery current as defined by a predetermined programmable value is at a maximum current limit;determining, by the logic circuit, whether the battery current is at a minimum current limit when the battery current is less than the maximum current limit;determining, by the logic circuit, whether a bit of the broadcast packet has a default pulse width when the battery current is at the minimum current limit; andincreasing the pulse width when the pulse width is not at the default pulse width; andincreasing the current limit when the pulse width is at the default pulse width.
11. The method of claim 10, comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the minimum current limit.
12. The method of claim 10, comprising: determining, by the logic circuit, whether the pulse width is at a maximum pulse width when the battery current is at the maximum current limit; andincreasing, by the logic circuit, the pulse width when the pulse width is not at a maximum pulse width.
13. The method of claim 1, wherein the tune-down procedure, comprises: determining, by a logic circuit, whether a battery current is at a minimum current limit;determining, by the logic circuit, whether the battery current is at a maximum current limit when the battery current is less than the minimum current limit;determining, by the logic circuit, whether a bit of the broadcast packet has a default pulse width when the battery current is at the maximum current limit; anddecreasing the pulse width when the pulse width is not at the default pulse width; anddecreasing the current limit when the pulse width is at the default pulse width.
14. The method of claim 13, comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the maximum current limit.
15. The method of claim 13, comprising: determining, by the logic circuit, whether the pulse width is at a minimum pulse width when the battery current is at the minimum current limit; andreducing, by the logic circuit, the pulse width when the pulse width is not at a minimum pulse width.
16. A logic circuit configured to stabilize battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet, the logic circuit comprising: a processor configured to receive a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller;determine a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; andperform a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.
17. The logic circuit of claim 16, comprising: a sample-and-hold circuit; andan analog-to-digital converter, each coupled to the processor and the battery;wherein the analog-to-digital converter samples the battery voltage to determine the sampled battery voltage.
18. The logic circuit of claim 17, comprising a battery coupled to the processor.
19. A communication system, comprising: a processor configured to stabilize a voltage potential generated by an event indicator while optimizing power delivered to a receiver during communication of a broadcast packet by the event indicator to the receiver, the broadcast packet having a predetermined number of bits; andan event indicator system with dissimilar metals positioned on opposite ends, wherein the event indicator is configured to generate a voltage potential when the dissimilar metals positioned on opposite ends dissolve in a conducting fluid;wherein the processor is further configured to:determine a number of cycles in which a sampled voltage potential is either greater than or less than or equal to a nominal voltage potential over a first subset of the predetermined number of bits of the broadcast packet;perform a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.
20. The communication system of claim 19, comprising: a sample-and-hold circuit; andan analog-to-digital converter, each coupled to the processor and the event indicator;wherein the analog-to-digital converter is to sample the voltage potential to determine the sampled battery potential.

Parent Case Info

This application claims priority to International Application No. PCT/US2013/065041 filed Oct. 15, 2013, which application, pursuant to 35 U.S.C. §119 (e), claims priority to the filing date of U.S. Provisional Patent Application Ser. No. 61/715,610 filed Oct. 18, 2012; the disclosures of which are herein incorporated by reference.

PCT Information

Filing Document	Filing Date	Country	Kind
PCT/US2013/065041	10/15/2013	WO	00

Publishing Document	Publishing Date	Country	Kind
WO2014/062674	4/24/2014	WO	A

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	Number	Date	Country
	20150294077 A1	Oct 2015	US

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	Number	Date	Country
	61715610	Oct 2012	US

Apparatus, system, and method to adaptively optimize power dissipation and broadcast power in a power source for a communication device

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