J. Cortadella, et al., "Designing a Branch Target Buffer for Executing Branches with Zero Time Cost in a Risc Processor," Microprocessing & Microprogramming, vol. 24, No. 1-5, pp. 573-580, Aug. 1988. |
G. S. Rao, "Byte Operand Buffer for Predicting the Outcome of Conditional Branches," IBM Technical Disclosure Bulletin, vol. 25, No. 3A, pp. 1289-1291, Aug. 1982. |
J. F. Hughes, et al., "Implementation of a Byte Buffer for IBM 3033 Processor," IBM Technical Disclosure Bulletin, vol. 25, No. 3A, pp. 1236-1237, Aug. 1982. |
J. A. DeRosa, et al., "An Evaluation of Branch Architectures," The 14th Annual International Symposium on Computer Architecture, pp. 10-16, Jun. 2-5, 1987. |