Patent Application
20140369143
Programmable elements are included in integrated circuits to store information to be retained even when power is not provided to the circuits. The programmable elements are non-volatile and may be programmed to store the desired information. Examples of non-volatile elements include fuses, antifuses, and non-volatile memory elements. Examples of the types of information programmed in the programmable elements of an integrated circuit include device information, device configuration information, device operation information, as well as other information.
In a particular example for memory circuits, programmable elements may be used to store memory address mapping information related to mapping memory addresses to redundant memory elements. Mapping memory address to redundant memory allows for “repairing” defective memory of a main memory array by accessing the redundant memory to which the memory address of the defective memory is mapped instead of the memory of the main memory array that is defective. A redundant memory element typically has a respective associated set of programmable elements that are used to store memory address information when the redundant memory element is used, and a respective set of latches into which a programmed memory address is latched for operation. Thus, when the respective associated set of programmable elements is enabled and programmed with a memory address, the redundant memory element is accessed when a memory access operation is requested for that memory address. However, if a redundant memory element is not used, the respective associated set of programmable elements remains unprogrammed.
As the capacity of memory circuits has increased, the number of redundant memory elements has increased as well. Along with the additional redundant memory elements, a corresponding number of sets of programmable elements and sets of latches have been added. The additional redundant memory elements and respective sets of associated programmable elements and sets of latches result in larger integrated circuit area and increased manufacturing complexity. Often much of the redundant memory elements are not used because there are fewer defective memory locations than available redundant memory elements. The unprogrammed sets of programmable elements and unused redundant memory in effect represent wasted space. The amount of redundant memory elements and respective associated sets of programmable elements could be reduced to address the issue, however, it is desirable to maintain the number of redundant memory elements because the number of defective memory that will be in need of repair is unpredictable.
Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.
The apparatus further includes a redundant memory programmable element block 120 which includes programmable elements (e.g., fuses, antifuses, non-volatile memory, etc.) that are configured to be programmed with the memory addresses of memory that are to be mapped to redundant memory. The programmable elements may be further programmed with location information for redundant memory to which programmed memory addresses are mapped. The programmable elements of the programmable element block 120 may be arranged as sets of programmable elements, with each set of programmable elements configured to be programmed with a memory address to be mapped to redundant memory and location information for the redundant memory to which the respective programmed memory address is to be mapped. The memory address programmed in the programmable elements and mapped to redundant memory may represent one or more memory addresses of memory. That is, one or more memory locations may be mapped to redundant memory by virtue of mapping a memory address to the redundant memory.
Programmable element block logic 130 included in the apparatus is configured to perform operations, for example, to access the sets of programmable elements of the programmable element block 120 and associate any programmed memory addresses with redundant memory to which the programmed memory addresses are mapped, for example, based on the programmed memory addresses and location information. Redundant memory logic 140 included in the apparatus may be configured to perform operations for mapping memory addresses of defective memory to redundant memory during operation of the apparatus, for example, comparing incoming memory addresses of memory to be accessed to addresses of memory that are mapped and accessing the associated redundant memory.
As will be described in more detail below, in contrast to conventional redundant memory arrangements having a set of programmable elements associated with a respective redundant memory element, memory addresses to be mapped to redundant memory elements are programmed in the programmable element block 120 and associated with the redundant memory elements. The total number of programmable elements included in the programmable element block 120 may be less than the total number of programmable elements for conventional redundant memory arrangements, which may allow the number of programmable elements related to redundant memory operation to be reduced while maintaining the number of redundant memory available for memory repair.
The memory sections 210(0)-210(M) include memory that may be accessed to store information and to retrieve stored information. The memory of memory sections 210 may be arranged in rows and columns, with a memory cell located at the intersection of a row and column, which may be accessed by providing row and column addresses corresponding to the row and column. The redundant memory sections 220(0)-210(M) include redundant memory elements (not shown in
In some embodiments, the redundant memory elements of the redundant memory section 220 are columns of redundant memory to which the memory addresses of a column or columns of memory of the associated memory section 210 may be mapped. A redundant memory element of redundant memory section 220 may be one column of redundant memory or a group of two or more columns of redundant memory. In some embodiments, the redundant memory elements of the redundant memory section 240 are row of redundant memory to which the memory addresses of a row or rows of memory of the memory sections 210(0)-210(M) may be mapped. A redundant memory element of redundant memory section 240 may be one row of redundant memory or a group of two or more rows of redundant memory. The redundant memory elements of the redundant memory sections 220 and 240 may have other configurations as well. For example, the redundant memory elements of the redundant memory sections 220 and/or 240 may include one or more memory sections of redundant memory, or one or more memory blocks of redundant memory. The memory sections and/or memory blocks of redundant memory may also be shared with one or more of the memory sections 210(0)-210(M).
A redundant address latch 320 is associated with a respective redundant memory element 310. A memory address may be mapped to a redundant memory element 310 by latching the memory address to be mapped in the associated redundant address latch 320. For example, a memory address latched in redundant address latch 320(0) is mapped to redundant memory element 310(0), a memory address latched in redundant address latch 320(1) is mapped to redundant memory element 310(1), a memory address latched in redundant address latch 320(2) is mapped to redundant memory element 310(2), and so on. The memory address that is latched in a redundant address latch 320 may be a memory address programmed in the programmable element block 120 (
The redundant memory elements 310(0)-310(P) may have various configurations. For example, a redundant memory element 310 may include one or more redundant columns of memory. In other embodiments, a redundant memory element 310 may include one or more rows of redundant memory. A redundant memory element 310 may include one or more memory sections of redundant memory, or one or more memory blocks of redundant memory. Additionally, several memory addresses, for example, memory addresses for memory along a column or columns of memory or memory addresses for memory along a row or rows of memory, may be mapped to a redundant memory element when associated with a memory address.
The programmable elements of a programmable element set 410 may be programmed with a memory address to be mapped to redundant memory element. Additional information, for example, location information for the redundant memory section to which the programmed memory address is mapped, may also be programmed in the programmable elements of the programmable element set 410. A programmable element set 410 may further include enable information, which may be used to indicate that a programmable element set having the enable information programmed has been programmed with a memory address. Greater or fewer programmable element sets 410(0)-410(R) than those shown in
The programmable element block 400 may be used for mapping memory addresses of different-sized memory spaces. For example, in some embodiments, a programmable element block 400 may be used for mapping memory addresses of an entire array of memory. In some embodiments, a programmable element block 400 may be used for mapping memory addresses of a portion of the array, such as for one or more memory blocks, or for one or more memory sections. An apparatus may include one or more programmable element blocks for programming memory addresses to be mapped.
The number of bits for the redundant memory location information 510 and the memory address to be mapped 520 may be based at least in part, for example, on the configuration of redundant memory sections for a region of memory, and the configuration of memory for the region of memory. By way of a non-limiting example, a memory array may include 16 memory blocks, with each memory block including 16 memory sections. Thus, the memory array includes a total of 256 memory sections. Each of the memory sections is associated with a respective redundant memory section (for a total of 256 redundant memory sections) to which memory addresses for the associated memory section may be mapped. The redundant memory section includes redundant memory elements, each of which may be used for mapping one of 128 different memory addresses of the associated memory section (e.g., a memory section may include 128 columns of memory, with each column of memory having a respective column address).
In the present example, the redundant memory location information 510 may include 8-bits of information to select one of the 256 redundant memory sections, for example, to locate a redundant memory section to which memory addresses of the associated memory section may be mapped. The memory address to be mapped 520 may include 7-bits of information to identify which of the 128 different memory addresses of a memory section will be mapped to a redundant memory element. The enable information 530 may have 1-bit of information, which when programmed (e.g., to a high logic level) indicates that the programmable element set has been programmed with information.
In some embodiments, the number of bits for the information programmed in a programmable element set may be different, for example, between programmable element sets configured to be programmed with information for mapping column addresses to columns of redundant memory and programmable element sets configured to be programmed with information for mapping row addresses to rows of redundant memory. In some embodiments, a programmable element set includes information in addition, or in the alternative to the information previously described with reference to
As previously described, the information programmed in a programmable element set may be used to locate the redundant memory section to which the memory address also programmed in the programmable element set is to be mapped. Which of the redundant memory elements of the located redundant memory section (e.g., by the redundant memory location information 510) used for the mapping will be described in greater detail below.
At step 610 the redundant memory location information for a programmable element set is decoded to locate a redundant memory section. The redundant memory section located by the redundant memory location information is associated with a respective memory section having a memory address that is to be mapped to a redundant memory element in the redundant memory section. Following the locating of the redundant memory section based on the redundant memory location information, at step 620 availability of a redundant memory element of the redundant memory section to be associated with a memory address is checked. A redundant memory element may be not be available, for example, if it has already been enabled to have a memory address mapped to it (e.g., the respective redundant address latch has a memory address already latched) or the redundant memory element is inoperable (e.g., defective).
If it is determined at step 630 that the redundant memory element is available, the memory address to be mapped that is programmed in the same programmable element set as the redundant memory location information is latched into the redundant address latch of the available redundant memory element at step 640. As a result of latching the memory address in the redundant address latch, the redundant memory element now associated with the memory address will be accessed instead of the memory in the memory section corresponding to the memory address. If it is determined at step 630 that the redundant memory element is not available, the availability of another redundant memory element of the located redundant memory section is checked. If the other redundant memory element is available, the memory address to be mapped is latched in the redundant address latch for the available redundant memory element. However, if the other redundant memory element is not available, yet another redundant memory element of the redundant memory section is checked for availability.
The availability of a redundant memory element may be indicated by enable information associated with the redundant memory element and/or with the redundant address latch. A redundant memory element and/or associated redundant address latch that is indicated as enabled is not available for latching a memory address, such as when the redundant address latch already latches a memory address, or when the redundant memory element is inoperable.
In some embodiments, enable information is latched by a portion of the redundant address latch responsive to latching of a memory address programmed in a programmable element set. Enable information programmed with a memory address in the programmable element set enable information (e.g., enable information 530 of
As previously discussed, a memory address to be mapped is programmed in a programmable element set along with location information for redundant memory to which the memory address may be mapped. All of the memory addresses programmed in the programmable element sets of a programmable element block are associated to redundant memory to complete the mapping. An operation may be performed to associate the memory addresses programmed in the programmable element block to the redundant memory. The operation 600 previously described is an example of an operation that associates the programmed memory address with a particular redundant memory element of the located redundant memory. Other operations for associating memory addresses and redundant memory may be used as well.
The association of memory addresses and redundant memory may be performed responsive to an event, for example, upon power-up of a memory. In some embodiments, the association of memory addresses and redundant memory may be performed responsive to a user provided command and/or to an internal command generated when an operating condition occurs.
The memory further includes a redundant memory programmable element block 750 and programmable element block logic 752 according to an embodiment of the invention. The redundant memory programmable element block 750 which includes programmable elements that are configured to be programmed with the memory addresses of memory that are to be mapped to redundant memory, as well as additional information, such as redundant memory location information and enable information. The programmable element block logic 752 is configured to perform operations, for example, to access the sets of programmable elements of the programmable element block 750 and associate any programmed memory addresses with redundant memory to which the programmed memory addresses are mapped based on the programmed memory addresses and location information.
The row and column addresses are provided by the address latch 710 to a row address decoder 722 and a column address decoder 728, respectively. The column address decoder 728 selects bit lines extending through the array 702 corresponding to respective column addresses. The row address decoder 722 is connected to word line driver 724 that activates respective rows of memory cells in the array 702 corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry 730 to provide read data to a data output buffer 734 via an input-output data bus 740. Write data are applied to the memory array 702 through a data input buffer 744 and the memory array read/write circuitry 730. The command decoder 706 responds to memory commands applied to the command bus 708 to perform various operations on the memory array 702. In particular, the command decoder 706 is used to generate internal control signals to read data from and write data to the memory array 702.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
