Patent Application
20250068345
Information may be stored on memory cells of a memory device. The memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). Information in the memory cells may decay over time. For example, the information may be stored as a charge on a capacitor which may decay over time. The memory device may perform refresh operations to restore the information and prevent information from being lost.
Certain patterns of access may cause an increased rate of information decay in nearby memory cells (e.g., the memory cells along nearby word lines). Memories may use various schemes to identify which memory cells are affected by such patterns such that targeted refresh operations can be performed before those memory cells lose their information. There is need to balance the targeted refresh operations with the time and power they use.
The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure or its applications or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings which form a part hereof, and which are shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the disclosure. Moreover, for the purpose of clarity, detailed descriptions of certain features will not be discussed when they would be apparent to those with skill in the art so as not to obscure the description of embodiments of the disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims.
Information in a memory array may be accessed by one or more access operations, such as read or write operations. During an example access operation a word line may be activated based on a row address and then selected memory cells along that active word line may have their information read or written to based on which bit lines are accessed, which may be based on a column address. The memory array may be refreshed on a row by row basis (e.g., as part of an auto-refresh and/or self-refresh mode) where the memory cells along each row are refreshed periodically. The speed at which the rows are refreshed (e.g., the maximum time any given row will go between refreshes) may be determined based on an expected rate of information decay.
Various patterns of access to a row (an aggressor row) may cause an increased rate of information decay in nearby memory cells (e.g., along victim rows). For example, a ‘row hammer’ may involve repeated accesses to the aggressor row which may increase a rate of decay in adjacent rows (and/or in rows which are further away). Accordingly, it may be important to track a number of accesses to each row to determine if they are aggressors, such that the victim rows can be identified and refreshed as part of a targeted refresh operation. For example, each word line may have an associated count value which is used to determine how many times that word line has been accessed. Based on those access counts, rows may be identified for targeted refresh operations. There may be a need to manage how the memory identifies rows to balance detecting rows so they can be refreshed before information is lost against the time and power that those targeted refresh operations use. There may be a need to ensure that potential aggressors are identified while filtering out un-needed targeted refresh operations.
The present disclosure is drawn to apparatuses, systems, and methods for per-row count based refresh target identification. A memory device includes a number of word lines, each of which stores a count value. A refresh control circuit of the memory device identifies the rows with the N highest count values and stores the row address and count value in a register. For example, in an example embodiment where N is 1, the row and count value with the highest count value is stored. In an embodiment where N is 2, the two rows and their count values with the highest and next highest count value are stored. When a targeted refresh operation is called for, the stored row with the worst count value is compared to a threshold. If the count value has crossed the threshold, a targeted refresh operation is performed on victims associated with the address and the count is reset. If the count value has not crossed the threshold, then the targeted refresh operation may be skipped.
The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. In the embodiment of
The selection of the word line WL is performed by a row decoder 108 and the selection of the bit lines BL is performed by a column decoder 110. In the embodiment of
Some of the memory cells may be set aside as counter memory cells 126. The counter memory cells may store count values XCount, each of which is associated with one of the word lines. Each count value XCount may be stored in counter memory cells 126 along the word line that the count value is associated with. The count value XCount may be stored as a binary number, with each bit stored in a memory cell along the word line. For the sake of clarity, a single bit line of counter memory cells 126 is shown in
The counter memory cells 126 may be referred to as such due to their use (storing the count values) and in some embodiments may be structurally similar to, or identical to, the other memory cells of the array. In some embodiments, the counter memory cells 126 may be grouped together (e.g., at the end of the word line). Other distributions of the counter memory cells 126 along the word line may be used in other example embodiments. In some embodiments, the counter memory cells 126 may not be directly accessible by external devices such as controllers (e.g., to prevent the count values from being overwritten). In other words, the bit lines associated with the counter memory cells 126 may not be accessed by a normal column address.
The semiconductor device 100 may employ a plurality of external terminals that include command and address (C/A) terminals coupled to a command and address bus to receive commands and addresses, and a CS signal, clock terminals to receive clocks CK and/CK, data terminals DQ to provide data, and power supply terminals to receive power supply potentials VDD, VSS, VDDQ, and VSSQ.
The clock terminals are supplied with external clocks CK and/CK that are provided to an input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and/CK clocks. The ICLK clock is provided to the command decoder 110 and to an internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operation of various internal circuits. The internal data clocks LCLK are provided to the input/output circuit 122 to time operation of circuits included in the input/output circuit 122, for example, to data receivers to time the receipt of write data.
The C/A terminals may be supplied with memory addresses. The memory addresses supplied to the C/A terminals are transferred, via a command/address input circuit 102, to an address decoder 104. The address decoder 104 receives the address and supplies a decoded row address XADD to the row decoder 108 and supplies a decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD. The C/A terminals may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. The access commands may be associated with one or more row address XADD, column address YADD, and bank address BADD to indicate the memory cell(s) to be accessed.
The commands may be provided as internal command signals to a command decoder 106 via the command/address input circuit 102. The command decoder 106 includes circuits to decode the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal to select a word line and a column command signal to select a bit line.
The device 100 may receive an access command which is a row activation command ACT. When the row activation command ACT is received, a bank address BADD and a row address XADD are timely supplied with the row activation command ACT.
The device 100 may receive an access command which is a read command. When a read command is received, a bank address BADD and a column address YADD are timely supplied with the read command, read data is read from memory cells in the memory array 118 corresponding to the row address XADD and column address YADD. The read command is received by the command decoder 106, which provides internal commands so that read data from the memory array 118 is provided to the read/write amplifiers 120. The read data is output to outside from the data terminals DQ via the input/output circuit 122. The access count XCount stored counter memory cells 126 of the row associated with the row address XADD are read to the refresh address control circuit 116, and an updated value of the access count XCount′ is written back to the counter memory cells 126 of the row XADD.
The device 100 may receive an access command which is a write command. When the write command is received, a bank address BADD and a column address YADD are timely supplied with the write command, write data supplied to the data terminals DQ is written to a memory cells in the memory array 118 corresponding to the row address and column address. The write command is received by the command decoder 106, which provides internal commands so that the write data is received by data receivers in the input/output circuit 122. Write clocks may also be provided to the external clock terminals for timing the receipt of the write data by the data receivers of the input/output circuit 122. The write data is supplied via the input/output circuit 122 to the read/write amplifiers 120, and by the read/write amplifiers 120 to the memory array 118 to be written into the memory cell MC. Similar to the read operation described above, the access count Xcount stored in counter memory cells 126 of the row associated with the row address XADD are read to the refresh address control circuit 116, and an updated value of the access count Xcount′ is written back to the counter memory cells 126 of the row XADD.
The device 100 may also receive commands causing it to carry out refresh operations. For example, a controller of the memory may put the device 100 into an auto-refresh mode and provide refresh signal REF. The device 100 may also enter a self-refresh mode where the refresh signal is generated internally. Since other than the source of the refresh signal, the two operations may generally be similar, the present disclosure will generally describe auto-refresh operations (for example the refresh signal may be referred to as an ‘auto-refresh signal’). However, it should be understood that the present disclosure may apply to self-refresh (or other refresh modes) as well.
The refresh signal REF may be a pulse signal which is activated when the command decoder 106 receives a signal which indicates an auto-refresh command. In some embodiments, the auto-refresh command may be externally issued to the memory device 100. In some embodiments, the auto-refresh command may be periodically generated by a component of the device (e.g., as part of a self-refresh mode). In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal REF may also be activated. The refresh signal REF may be activated once immediately after command input, and thereafter may be cyclically activated at desired internal timing. Thus, refresh operations may continue automatically. A self-refresh exit command may cause the automatic activation of the refresh signal REF to stop and return to an IDLE state.
The refresh signal REF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies a refresh row address RXADD to the row decoder 108, which refreshes a wordline WL identified by the refresh row address RXADD.
The refresh address control circuit 116 controls a type of refresh operation with timing based on the refresh signal REF, and generates and provides the refresh address RXADD. The refresh address control circuit 116 may be controlled to change details of the refreshing address RXADD (e.g., how the refresh address is calculated, the timing of the refresh addresses), or may operate based on internal logic.
The refresh address control circuit 116 may selectively output a targeted refresh address (e.g., a victim address) or a sequential refresh address (e.g., an auto-refresh address) as the refreshing address RXADD. The sequential refresh addresses may be generated based on a sequence of addresses. For example, each sequential refresh may be based on a previous sequential refresh address (e.g., RXADD (i)=RXADD (i−1)+1). The refresh address control circuit 116 may cycle through the sequence of sequential addresses at a rate determined by REF. In some embodiments, the sequence of sequential addresses may include all the addresses in the memory bank 118. In some embodiments, the auto-refresh signal REF may be issued with a frequency such that most or all of the addresses in the memory bank 118 are refreshed within a certain period (e.g., such that there is a maximum specified time between two consecutive sequential refreshes of a given word line), which may be based on an expected rate at which information in the memory cells MC decays.
The refresh address control circuit 116 also performs targeted refresh operations. As part of a targeted refresh operation the refresh address control circuit generates one or more refresh addresses based on an identified aggressor address. The aggressor addresses are row addresses identified as aggressors based on the count value XCount associated with that address. The refresh address control circuit 116 stores one or more candidate addresses and their associated counts in a candidate register. When a row is accessed, the count value XCount is read out and updated (e.g., by being incremented). The updated count value is compared to the stored count values in the candidate register. If the updated count value is greater, it is stored in the register and the current row address is written to the register (overwriting a previous entry). In this manner, the candidate register stores the addresses and counts with the highest count values. The depth of the register may determine how many addresses and counts are stored.
Refresh operations are performed with a timing based on a timing of the refresh signal REF or based on an RFM command. Responsive to REF, the refresh address control circuit may perform multiple ‘pumps’ of an internal refresh signal, and a refresh operation may be performed for each of those pumps. Each pump may be used for a sequential refresh operation, a targeted refresh operation, or may be skipped (e.g., no refresh operation performed). In some embodiments, the targeted refresh address may be issued in (e.g., “steal”) a pump which would otherwise have been used for a sequential refresh operation. In some embodiments, certain time slots may be reserved for targeted refresh addresses. Responsive to an RFM command, the refresh control circuit 116 may perform multiple pumps, all of which may be used for targeted refresh operations.
When a targeted refresh operation is called for, either by the internal logic of the refresh control circuit 116 or due to an external command such as a refresh management (RFM) command, the refresh control circuit 116 may determine if the stored address in the candidate register is an aggressor. For example, the stored count value may be compared to a threshold and if the count has crossed the threshold (e.g., is greater than the threshold), then the stored address may be identified as an aggressor, and one or more targeted refresh addresses may be generated based on the aggressor. Responsive to the targeted refresh operation being performed, the count value XCount in the counter memory cells 126 associated with the identified aggressor may be changed, such as being reset (e.g., to an initial value such as 0). If the stored count value had not crossed the threshold, then the stored address is not an aggressor and the targeted refresh operation may be skipped.
The threshold may be a setting of the memory device 100 in some embodiments. For example, a mode register 130 may store the threshold value. The mode register 130 may store a collection of registers, each of which store settings and/or information about the memory device. Some registers may be modified by a controller (e.g., to change settings) via mode register write operation. Some registers may be set by a non-volatile storage element on the memory, such as a fuse array. The controller may perform mode register read operations to determine the state of selected registers. An aggressor threshold register may set a value of the threshold. If the threshold is increased, fewer targeted refresh operations will occur and if it is decreased, more will occur. If the threshold is set to 0, then a targeted refresh will always be performed when a targeted refresh is called for.
The refresh address control circuit 116 may use different methods to calculate a targeted refresh address based on the aggressor address based on the access count. For example the victim addresses may include word lines adjacent to the aggressor word line (e.g., XADD+1 and XADD−1) and/or may include wordlines further away (e.g., XADD+/−2, XADD+/−3, etc.). In some embodiments, more than one victim address may correspond to a given aggressor address. In this case the refresh address control circuit may queue up multiple targeted refresh addresses, and provide them sequentially when it determines that a targeted refresh address should be provided. The refresh address control circuit 116 may provide the targeted refresh address right away, or may queue up the targeted refresh address to be provided at a later time (e.g., in the next time slot available for a targeted refresh).
The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.
The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 122. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals in an embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals in another embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit 122 so that power supply noise generated by the input/output circuit 122 does not propagate to the other circuit blocks.
Certain internal components and signals of the refresh address control circuit 216 are shown to illustrate the operation of the refresh address control circuit 216. For example, the refresh control circuit 216 may include an RHR state control circuit 242 which determines if sequential or targeted refreshes are performed, an aggressor detector circuit 217 which identifies addresses as aggressors HitXADD, and a refresh address generator 250 which generates the refresh address RXADD. Also shown is a counter circuit 246 which manages the values of XCount stored in the counter memory cells 226 of the memory array 218.
The dotted line around the refresh address control circuit 216, the row decoder 208, and the memory array 218 is shown to represent that in certain embodiments, each of the components within the dotted line may correspond to a particular bank of memory, and that these components may be repeated for each of the banks of memory. In some embodiments, the components shown within the dotted line may be associated with each of the memory banks. Thus, there may be multiple refresh address control circuits 216 and row decoders 208. For the sake of brevity, components for only a single bank will be described.
A DRAM interface 240 may provide one or more signals to an address refresh control circuit 216 and row decoder 208 which in turn (along with a column decoder, not shown) may perform access operation on a memory array 218. When a row of the memory array 218 is accessed, the values of the counter memory cells 226 along that row are read to the counter circuit 246. For example, the counter memory cells 226 may store the bits of a binary number that represents the count value. For example, if the number is a 16-bit number, then 16 or more counter memory cells may store the bits of the number.
The counter 246 may determine a value of the access count for that row based on the values read from the counter memory cells 226. The counter 246 may be a count control circuit, which may manage a value of the count stored in the counter memory cells 226 (e.g., by reading the raw data in the counter memory cells 226 as a numerical value, writing new numerical values to the counter memory cells 226 etc.). The counter circuit 246 may change the count value (e.g., by incrementing the count value) write the changed count value back to the counter memory cells and provide the changed count value to the aggressor detector circuit 217. The aggressor detector circuit 217 includes an aggressor candidate register 244 and a register management circuit 245. The candidate register 244 stores a set of candidate row addresses and their associated count values. During an access operation, the register management circuit 245 compares the accessed row address XADD and its updated count value XCount′ to the stored addresses. If the address XADD matches, then its count value in the register 244 is updated to XCount′. If there is not a match, the count value is stored and the address is stored if the count value is greater than one of the stored count values, with the row address XADD and count XCount′ replacing a previous entry with the lowest count value.
During refresh operations (e.g., responsive to REF and/or RFM) the refresh state controller 242 determines a type of refresh operation and provides internal refresh signals IREF and/or RHR. The signal RHR indicates that a targeted refresh operation should be performed. Responsive to RHR, the aggressor detector circuit 217 compares the stored value XCount with the highest value to a threshold. If the value crosses the threshold, then the row address associated with that count is identified as an aggressor HitXADD and provided to a refresh address generator 250, which generates one or more refresh addresses RXADD based on the aggressor HitXADD. The row decoder 208 then performs a refresh operation on the word line indicated by RXADD. An additional operation is performed to have the counter 246 read out of the count value XCount associated with the aggressor HitXADD from the counter memory cells 226 and reset that count (e.g., to an initial value such as 0).
The DRAM interface 240 may represent one or more components which provides signals to components of the bank. For example, the DRAM interface 240 may represent components such as the command address input circuit 102, the address decoder 104, and/or the command decoder 106 of
The aggressor detection circuit 217 includes a candidate register 244 which stores a set of candidate addresses and their associated count values. The candidate register 244 includes a number of slots, each of which stores an address and count value. The number of slots determines how many addresses and count values can be stored. The candidate register 244 stores the addresses with the highest count values. During access operations, the aggressor detection circuit 217 receives row address XADD and their associated updated count value XCount from the counter circuit 246. A register management circuit 245 includes a comparator circuit 248 which compares the updated count value to the stored count values. If the updated count value is greater, then the row address XADD and updated count value XCount′ overwrite the stored address and count value. In some embodiments, the new row and count may overwrite the stored address with the lowest count value.
The refresh state controller 242 may receive the auto-refresh signal REF and determine what type and how many refresh operations should occur. The refresh state control circuit 242 provides one or more activations of internal refresh signals IREF and RHR. Responsive to the activations of the internal refresh signals, the refresh address generator performs a refresh operation (or skips performing a refresh operation if the aggressor detector does not identify an aggressor HitXADD). The refresh state controller 242 provides the signal RHR to indicate a targeted refresh operation. The refresh state controller 242 provides the signal RHR responsive to RFM or based on internal logic responsive to REF. For example, the refresh state controller 242 may provide the RHR signal based on certain number of activations of REF (e.g., every 4th activation of REF) and/or based on a number of activations of IREF. In some embodiments, IREF alone may indicate a sequential refresh operation, while IREF and RHR together indicate a targeted refresh operation. Responsive to REF or RFM, the refresh state control may generate a number of activations of IREF (e.g., a number of pumps) and then activate RHR for the pumps which are used for targeted refresh operation.
Responsive to the signal RHR, the aggressor detector 217 determines if the stored address with the highest count value is an aggressor or not, and if so provides it as the aggressor address HitXADD. Responsive to no address in the candidate register 244 being an aggressor, no address is provided as HitXADD (which in turn causes the targeted refresh operations to be skipped). The aggressor detector circuit 217 determines if the address with the highest count value is an aggressor by comparing the count value to a threshold (e.g., with comparator circuit 248). If the count value has not crossed the threshold (e.g., is below the threshold) then the address is not an aggressor and no address is provided as HitXADD. If the address has crossed the threshold (e.g., meets or exceeds the threshold) then address is provided as HitXADD.
Responsive to one of the stored addresses being provided as HitXADD, the register management circuit 245 may perform an operation to reset the count value associated with that address. The register management circuit 245 may direct the row decoder 208 to read out the count value associated with HitXADD from the counter memory cells 226 to the counter circuit 246. The register management circuit 245 may direct the counter circuit 246 to reset the count value (e.g., to an initial value) and write the reset value back to the counter memory cells 226. The register management circuit 245 also removes the stored address and count value from the register 244.
The refresh address generator 250 includes a sequential refresh address generator 252 and a targeted refresh address generator 254. The sequential refresh address generator 252 generates a sequential refresh address as the refresh address RXADD when a sequential refresh operation is called for (e.g., when IREF is active but RHR is not). The sequential refresh address may be based on a previous sequential refresh address. For example, the sequential refresh address generator may have a counter circuit which increments a previous sequential refresh address value to achieve the next sequential refresh address.
The refresh address generator circuit 250 also includes a targeted refresh address generator circuit 254 which generates a targeted refresh address as the refresh address RXADD when it receives the RHR signal and an identified aggressor address HitXADD. If the signal RHR is provided, but HitXADD is not (e.g., because none of the addresses stored in the candidate register 244 have crossed the threshold) then the targeted refresh address generator may skip the targeted refresh operation by not providing a refresh address RXADD. The targeted refresh address generator 254 may determine the locations of one or more victim rows based on aggressor address HitXADD and provide them as the refresh address RXADD. In some embodiments, the victim rows may include rows which are physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD−1). In some embodiments, the victim rows may also include rows which are physically adjacent to the physically adjacent rows of the aggressor row (e.g., HitXADD+2 and HitXADD−2). Other relationships between victim rows and the identified aggressor rows may be used in other examples.
The row decoder 208 may perform one or more operations on the memory array 218 based on the received signals and addresses. For example, responsive to the activation signal ACT and the row address XADD (and IREF and RHR being at a low logic level), the row decoder 208 may direct one or more access operations (for example, a read operation) on the specified row address XADD. Responsive to an address RXADD and one or both of the signals IREF and RHR being active, the row decoder 208 may perform a refresh operation on the word line (or word lines) associated with RXADD. Responsive to the signal RHR being active but no address RXADD (e.g., because no address HitXADD was provided to the refresh address generator 250) then the row decoder 208 may skip the refresh operation.
Each of the registers 313 and 315 has a single slot which stores a single address and its related count value. The registers may include a number of content addressable memory (CAM) cells which allow comparing an input to the stored value. The register management circuits 312 and 314 can each read out of the stored address CAM_Adr and stored count CAM_CNT from their respective registers 313 and 315, and also write an address Worst_Adr and count Worst_CNT to their respective registers.
During an access operation, the bank logic 304 provides a row address XADD along with an activation signal ACT to the memory array such as 118 of
Both portions of the register management circuit 312 and 314 receive the row address XADD from a row address bus and the updated count value XCount′ from the counter. The count goes to the first register management portion 312 as RH1 CNT and to the second register management portion 314 as RH2 CNT. The register management portion 312 compares the count RH1 CNT to the stored CAM_CNT from the first register slot 312 and the register management portion 314 compares the count RH2 CNT to the stored CAM_CNT from the second register slot 315. If the count value RH1 CNT is greater than the value CAM_CNT read out from the register 313, then the register management circuit 312 provides XADD and RH1 CNT as the Worst_Adr and Worst_CNT, to overwrite the values stored in the register 313. Similarly, if the count value RH2 CNT is greater than the value CAM_CNT read out from the register 315, then the register management circuit 314 provides XADD and RH2 CNT as the Worst_Adr and Worst_CNT, to overwrite the values stored in the register 315.
During refresh operations, a first type or a second type of targeted refresh operation may be called for. The first type of targeted refresh operation may refresh word lines which have a first relationship with the identified aggressor, while the second type of targeted refresh operation may refresh word lines which have a second relationship with the identified aggressor. For example, the first type of targeted refresh operation may refresh word lines which are adjacent to the aggressor (e.g., +/−1) while the second type of targeted refresh operation may refresh word lines which are further away (e.g., +/−2). When the bank logic 304 calls for the first type of targeted refresh operation, the first refresh management portion 312 and register 313 may be used. When the bank logic calls for the second type of targeted refresh operation, the second refresh management portion 314 and register 315 may be used.
The bank logic 304 may call for the different types of targeted refresh operation based on internal logic For example, every Nth time the first type of targeted refresh operation is performed, the second type of targeted refresh operation may be performed as the next targeted refresh operation. Based on which type of targeted refresh operation is called for, the row hammer mitigation logic circuit 318 may use different logic to generate the refresh address RXADD.
The timing diagram shows 3 ‘rounds’ 410-430 of commands, each of which ends with a refresh command REF. The top line of each round shows a portion of an example sequence of commands which could be sent as part of the round, such as row activation commands ACT, precharge commands PRE, and write and read commands WRT and READ, as well as the refresh commands REF and RFM. Each round 410-430 also shows a table which represents a set of row addresses and their associated count values at the end of that round when the refresh command is received. Each round also shows a set of refresh pumps (e.g., activations of IREF and/or RHR) generated responsive to the refresh signal or the RFM command and how those pumps may be used.
At the end of the first round 410, the row address with the highest access count is Row_8 with a count of 186. However, this is below the aggressor threshold. Accordingly, responsive to the refresh signal REF, a set of pumps are generated, a first set of which is used for sequential refresh operations, but the last three of which are skipped.
At the end of the second round 420, the row with the highest count is now Row_2, with a count of 203. Since this is above the threshold value, responsive to the refresh signal REF, after the sequential refresh pumps are performed, three targeted refresh pumps are performed. The first pump is used to access the aggressor address (Row_2) and read out and reset its count value. In this example, the count value is reset to an initial value of 0. The next two pumps are used to refresh victim addresses based on the address of Row_2. In this case, the victim addresses are the adjacent rows, so Row_1 and Row_3 would be refreshed.
At the end of the third round 430, two row counts are over the threshold, for Row_1 and Row_4. However, since Row_4's count is higher than Row_1's count, the victims of Row_4 will be refreshed but not Row_1 as part of this refresh operation. At the end of the third round 430, a refresh management signal RFM is received, so only targeted refresh operations are performed. Three pumps are performed, one to reset the count value of Row_4, and then two pumps to refresh the adjacent rows (Row_3 and Row_5). Since Row 4's count has been reset, Row_1 is now the row with the highest count and will be reset as part of the next set of targeted refresh operations, unless another row's count passes it.
The method 500 may generally begin with block 510, which describes accessing a word line and updating a count value associated with the word line. The method 500 may include receiving a row address associated with the word line for example along a C/A terminal from a controller of a memory device. The method 500 may include activating the word line associated with the row address and reading the count value out from counter memory cells (e.g., 126 of
Box 510 may be followed by box 520, which describes storing a row address associated with the word line and the updated value in a candidate register (e.g., 244 of
Box 520 may include comparing the updated count value to the stored count value(s) in the candidate register. For example, a register management circuit (e.g., 245 of
Box 520 may be followed by box 530, which describes comparing the stored updated count value to a threshold responsive to a targeted refresh signal. The method 500 may include generating the targeted refresh signal based on a refresh management command or a refresh signal. For example, a refresh state control circuit (e.g., 242 of
Box 530 may be followed by box 540, which describes identifying the stored row address as an aggressor address if the stored updated count value has crossed the threshold. For example, the method 500 may include identifying the address in the candidate register with the highest count value as the aggressor if the count value has crossed the threshold.
If the highest count value has crossed the threshold, box 540 may be followed by box 550, which describes refreshing one or more word lines as part of a targeted refresh operation if the stored row address was identified as the aggressor address. The method 500 may include generating a refresh address based on the identified aggressor address (e.g., with a refresh address generator such as 250 of
The method 500 may include resetting count value responsive to identifying the stored row address as the aggressor address. For example, the resetting may include accessing the word line associated with the aggressor address, reading out the count value from the counter memory cells along that word line to the counter circuit, changing the count value (e.g., to reset it to an initial value such as 0) and writing the changed count value back to the counter memory cells. The resetting may be performed responsive to one of the activations of the targeted refresh signal.
If the highest count value has not crossed the threshold, then box 540 may be followed by skipping the targeted refresh operation. For example, when none of the stored count values have crossed the threshold, then the targeted refresh operation is skipped. For example, if no aggressor address is identified, the refresh address generator will not generate a refresh address responsive to the targeted refresh signal.
In some embodiments, the method 500 may include setting a value of the threshold. For example, the method 500 may include setting a threshold value in a mode register (e.g., 130 of
In some embodiments, the method 500 may include storing the row address in a first register or a second register (e.g., 313 or 315 of
It is to be appreciated that any one of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and/or processes or be separated and/or performed amongst separate devices or device portions in accordance with the present systems, devices and methods.
Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.
This application claims the benefit under 35 U.S.C. § 119 of the earlier filing date of U.S. Provisional Application Ser. No. 63/578,596 filed Aug. 24, 2024 the entire contents of which are hereby incorporated by reference in its entirety for any purpose.
| Number | Date | Country | |
|---|---|---|---|
| 63578596 | Aug 2023 | US |
