Patent Application
20240080229
This application claims priority to Greek Patent Application No. 20220100727, filed Sep. 6, 2022, the entire contents of which application are hereby incorporated herein by reference.
Embodiments of the present disclosure relate generally to network communications and, more particularly, to the operation of network data ports in network interface cards (NICs).
Communication systems leverage transmitters, receivers, switches, communication mediums (e.g., optical fibers, free space, etc.) and/or the like to communicably couple devices that form these communication systems. In some instances, Network Interface Cards (NIC) (e.g., network interface controllers, network adapters, local area network (LAN) adapters, physical network interfaces, and/or the like) that include network data ports are used in these communication systems to transfer data between electronic devices. Applicant has identified a number of deficiencies and problems associated with conventional communication systems. Through applied effort, ingenuity, and innovation, many of these identified problems have been solved by developing solutions that are included in embodiments of the present disclosure, many examples of which are described in detail herein.
Systems, apparatuses, methods, and computer program products are provided for eliminating or reducing the downtime of port switching in network communications. With reference to an example apparatus, a network interface device is provided. The network interface device may include at least one processor and a memory storing instructions that are operable, when executed by the processor, to cause the network interface device to perform a first link training process associated with a first data port of a network interface device coupled to a first communication link to determine a first communication parameter set for the first communication link. In response to determination of the first communication parameter set for the first communication link, the network interface device may deactivate the first data port and perform a second link training process associated with a second data port of the network interface device coupled to a second communication link to determine a second communication parameter set for the second communication link. Based at least in part on a network usage parameter set associated with a data plane of the network interface device, the network interface device may determine whether to activate the first data port associated with the first communication link concurrently with the second data port associated with the second communication link.
In some embodiments, the network interface device may perform the second link training process associated with the second data port based at least in part on the first communication parameter set for the first communication link.
In some embodiments, the network interface device may, in response to determination of the first communication parameter set for the first communication link, deactivate one or more hardware components associated with the first data port.
In some embodiments, the network interface device may, in response to determination of the first communication parameter set for the first communication link, deactivate one or more equalizers associated with the first data port.
In some embodiments, the network interface device may, in response to determination of the first communication parameter set for the first communication link, deactivate one or more drivers associated with the first data port.
In some embodiments, the network interface device may, based at least in part on network telemetry data associated with a telemetry system for the network interface device, determine whether to activate the first data port associated with the first communication link concurrently with the second data port associated with the second communication link.
In some embodiments, the network interface device may, based at least in part on predicted network usage for the network interface device during a first interval of time, determine whether to activate the first data port associated with the first communication link concurrently with the second data port associated with the second communication link.
In some embodiments, the network interface device may, in response to the network usage parameter set satisfying defined network usage criterion, activate the first data port associated with the first communication link concurrently with the second data port associated with the second communication link.
In some further embodiments, the network interface device may configure the first data port based at least in part on the first communication parameter set for the first communication link.
In some embodiments, the network interface device may, in response to failure of the second data port to satisfy defined operational quality criterion, activate the first data port associated with the first communication link and deactivate the second data port associated with the second communication link.
The above summary is provided merely for purposes of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Accordingly, it will be appreciated that the above-described embodiments are merely examples and should not be construed to narrow the scope or spirit of the disclosure in any way. It will be appreciated that the scope of the present disclosure encompasses many potential embodiments in addition to those here summarized, some of which will be further described below.
Having described certain example embodiments of the present disclosure in general terms above, reference will now be made to the accompanying drawings. The components illustrated in the figures may or may not be present in certain embodiments described herein. Some embodiments may include fewer (or more) components than those shown in the figures.
Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments are shown. Indeed, the embodiments of the present disclosure may include many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Where possible, any terms expressed in the singular form herein are meant to also include the plural form and vice versa, unless explicitly stated otherwise. Also, as used herein, the term “a” and/or “an” shall mean “one or more,” even though the phrase “one or more” is also used herein. Furthermore, when it is said herein that something is “based on” something else, it may be based on one or more other things as well. In other words, unless expressly indicated otherwise, as used herein “based on” means “based at least in part on” or “based at least partially on.” Like numbers refer to like elements throughout.
As used herein, the terms “network data ports,” “data network ports,” “network ports,” or “data ports” may be used interchangeably to refer to a communication endpoint used for transferring data to one or more other components of a network. As described hereinafter, each of these data ports may be configured to be selectively activated and/or deactivated so as to provide and preclude, respectively, network communication via the data port. As used herein, “operatively coupled” and “communicably coupled’ may mean that the components are coupled (e.g., electrically, optically, etc.) and/or are in communication with one another. Furthermore, operatively coupled may refer to components that are formed integrally with each other (e.g., as part of a common housing or structure) or components formed separately and coupled together. Furthermore, operatively coupled may refer to components that are directly connected to each other, connected to each other with one or more components (e.g., connectors) located between the components that are operatively coupled together, and/or connected to each other via a network (e.g., wired, wireless, or the like). Furthermore, operatively coupled may refer to components are permanently connected as well as detachable from one another.
As used herein, the term “determining” may be used to encompass a variety of actions such as, for example, calculating, computing, processing, deriving, investigating, ascertaining, and/or the like. Furthermore, determining may also include operations associated with receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and/or the like. Also, determining may be used herein to include resolving, selecting, choosing, calculating, establishing, and/or other similar or equivalent operations. Determining may also include ascertaining that a parameter matches a predetermined criterion, including that a threshold has been met, passed, exceeded, and so on.
It should be understood that the word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any implementation described herein as “exemplary” is not necessarily to be construed as advantageous over other implementations.
As described above, Network Interface Cards (NICs) often include network data ports that are used for transferring data between electronic devices of a network in a variety of applications. In conventional NIC implementations, the rate of data transfer required by the associated applications has been relatively low, thereby maintaining manageable power consumption of network data ports during transfer. As such, the thermal manageable of these NIC applications has similarly been manageable in that the ability to cool (e.g., dissipate heat) from the NICs has been similarly feasible. As the requirement for date rate transfer in different applications increases, however, the power consumption of the network data ports is becoming significant, thereby posing a challenge on the thermal design of the NIC based cards. In addition to the increasing total data transfer associated with NICs implementations, there is also a significant increase in the requirement for data transfer rate per lane. By way of example, a standard half-height, half-length card may be unable to accommodate more than one port cage due to the inability of these conventional NIC card implementations to sufficiently cool (e.g., dissipate heat from) the NIC card to required levels (e.g., set by regulation, standard, or the like).
In order to accommodate the requirements of increased data transfer rate per lane, a multi-port cage implementation may be used in which split cables from one cage aggregate several logic ports to multiple Top-of-Rack (ToR) switches. In some cases, the support for multiple ports is used for redundancy or resilience in that the desired system bandwidth is only capable of being supported by a single port connection. In other words, any additional port, while capable of transmitting data, may remain inoperable (e.g., not actively transmitting data) while the primary port is transmitting data for the multi-port implementation. The “active” or “passive” nature of the individual ports in these multi-port implementations may vary as described hereafter.
In some instances, such as when the multi-port cage includes at least two (2) ports, an “Active-Passive” configuration may be used. In such an implementation, a first logical port may be in an active state (e.g., transmitting data via the first logical port) while another, second logical port is in a passive state (e.g., a lack of transmission via the second logical port). The second logical port in the passive state may, when ordered, begin transmitting data, such as in stances in which the first logical port fails. Multi-port implementations that rely upon Active-Passive configurations, however, require a significant amount of time for a network data port to change from a passive state to an active state. This delay results in noticeable downtime of the network connection. In order to address these delays, some multi-port implementations rely upon an “Active-Active” configuration in which each of the first and second logical port are active. This configuration, however, consumes double the power of a single active port and further present a monumental increase in the thermal burden on the NIC based card. Moreover, in many cases, the internal bandwidth of the networking device does not support the aggregated rate of two active ports, thus the configuration of an “Active-Active” state may create an unnecessary congestion burden on the networking device (e.g., NIC or otherwise). As such, conventional multi-port network interface devices fail to provide reliable communication solutions that reduce downtime during port switching without increasing the congestion, power consumption, and/or thermal burden of the network interface device.
In order to confront these problems and others, the embodiments of the present disclosure provide a mechanism for operating in an “Active-Active” mode or an “Active-Passive” mode while maintaining a smooth transition (e.g., minimizing port delay) while switching between port states. By way of example, the methods and devices described herein may operate in an “Active-Passive” mode in which a first port is subjected to a link training session. Upon completion of the link training session, a data transfer with target Bit Error Rate (BER) is completed, the first port may save the link parameters, and the first port may be deactivated. Thereafter, a second port is activated, subjected to the link training session, and maintained as the active data network link. The link training session for the second port may be based at least in part on the link parameters saved during training of the first port so as to reduce the downtime associated with potential switches between these ports. In doing so, the embodiments of the present disclosure facilitate link parameter refresh by toggling between the first port and the second port based on environmental and system usage parameters.
With reference to
As shown, the first data port 101 (e.g., as applicable to each of the data ports) may include one or more communication lanes 103 that operate as the communication medium by which data, signals (e.g., optical, electrical, etc.), or the like are transmitted. By way of example, the first communication link coupled with the first data port 101 may provide data to the first data port 101 via the one or more inputs 102 for transmission along the respective communication lane 103 in the direction of respective outputs defined by these communication lanes 103 (e.g., to other devices communicable coupled to the communication lane(s) 103). The communication lanes 103 may define any communication medium by which data or signals may be transmitted, such as electrical wires, traces, or the like. Although described herein with reference to data transmitted as electrical signals, the present disclosure contemplates that the techniques described herein may be applicable to optical implementations in which optical signals are received from the first communication link. In such an example, the communication lanes 103 may be formed as optical fibers or an equivalent means by which optical signals (e.g., light) may be transmitted.
With continued reference to
As shown, the network interface device 100 may further include a GPU/CPU 400 that includes an equalization controller 105, a control logic block 110, a link training logic 115, and/or a firmware interface 120. Although described herein with reference to
As described hereafter with reference to
As shown, the GPU/CPU 400 may include an equalization controller 105 configured to control operation of the one or more equalizers 104. As described above, equalization of the one or more equalizers 104 may, in some embodiments, be implemented based on analog implementation. In other embodiments, equalization of the one or more equalizers 104 may be based on look-up tables. In any embodiment, the GPU/CPU 400 may, via the equalization controller 105 or otherwise, control operation of the equalizers 104. The equalization controller 105 may further independently control equalization of each communication lane 103. Operation of the one or more drivers 106 may be similarly controlled by the control logic 110, such that the control logic 110 may operate to rapidly activate (e.g., start) or deactivate (e.g., shut down) any of the one or more communication lanes 103. As described hereafter with reference to
Deactivation of the one or more hardware components may include removing a power source associated with the one or more hardware components and/or forcing the one or more hardware components into a low power/standby mode. In some embodiments, the time at which a particular communication lane 103, data port (e.g., first data port 101), etc. may be inactive (e.g., downtime) may be limited, such as by the requirements of the application associated with the network interface device 100. In such an embodiment, the GPU/CPU 400 may, instead of shutting down all of the one or more hardware components, maintain at least a portion or set of hardware components operational so as to facilitate a faster transition from a passive/standby mode to a fully operational/active mode to meet the downtime limits defined by the associated application.
The GPU/CPU 400 may further include link training logic 115 that includes circuitry components, logic, etc. configured to perform link training processes as described herein. By way of example, the link training logic may determine a first communication parameter set for the first communication link coupled to the first data port 101 and similarly determine a second communication parameter set for the second communication link coupled to the second data port. The present disclosure contemplates that the link training logic 115 may be configured to determine communication parameters associated with any of the data ports of the network interface device 100.
With reference to
Thereafter, as shown in operation 205, the network interface adapter 100 may perform a first link training process associated with the first data port to determine a first communication parameter set for the first communication link. The first link training process may be performed by the GPU/CPU 400 (e.g., by the control logic block 110, equalization controller 105, or the like) based on the link training logic 115. The first communication parameter set may refer to any characteristics, attributes, configurations, etc. association with proper establishment of communication with the first data port. In some embodiments, the first communication link may define, provide, or the like characteristics required to properly establish communication with the first communication link. The first data may therefore be configured by the first communication parameter set. By way of a non-liming example, the first communication parameter set may include data indicative of the clock frequency, number of active data lanes, data transmission rate, Bit Error Rate (BER), link partner clock frequency, signal phase offset and amplitude, equalizer tap coefficients, Clock and Data Recovery (CDR) taps, and/or the like to be used by the first data port when coupled with the first communication link. The present disclosure contemplates that the determination of the first communication parameter set may further be provided by an operator, user, system administrator, central control, and/or the like associated with the network interface device 100. In response to the completion of the first link training process, as shown in operation 210, the network inface device 100 may commence data transfer via the first data port based on the first communication parameter set.
Thereafter, as shown in operation 215, the network interface device 100 may deactivate the first data port. As described above, the network interface device may save or otherwise store the first communication parameter set and/or any other settings applied to the first data port and deactivate one or more hardware components associated with the first data port. Saving the first communication parameter set and/or other settings associated with the first data port may place the first data port in a standby mode or passive mode. This standby mode may allow the network interface device 100 to reactivate the first data port when needed as described hereafter with reference to operation block 230. In some embodiments, deactivating the one or more hardware components associated with the first data port may include deactivating the one or more equalizers of the first data port via the equalization controller 105 and/or the one or more drivers of the first data port via the control logic block 110. In some embodiments, deactivating the one or more hardware components may further include deactivating one or more of a host Serializer/Deserializer (SerDes), Optical Clock and Data Receiver (CDR)/Retimer, Digital Signal Processor (DSP) chip, laser/modulator driver amplifier, trans-impedance amplifier, transceiver microcontroller unit, electro-optic component bias, conditioning electronics, and/or the like. In some embodiments, selection of the one or more hardware components for deactivation may be based on a defined downtime requirement. In some embodiments, the one or more hardware components deactivated while deactivating the first data port may not include components such as laser bias and laser temperature stabilization circuitry in Wavelength Division Multiplexing (WDM) systems, which may be required for the first data port to remain in a standby or passive mode for faster transition to an active mode.
As shown in operation 220, the network interface device 100 may perform a second link training process associated a second data port of the network interface device coupled to a second communication link to determine a second communication parameter set for the second communication link. The second communication parameter set may refer to any characteristics, attributes, configurations, etc. association with proper establishment of communication with the second data port. In some embodiments, the second communication link may define, provide, or the like characteristics required to properly establish communication with the second communication link. By way of a non-liming example, the second communication parameter set may include data indicative of the clock frequency, number of active data lanes, data transmission rate, Bit Error Rate (BER), and/or the like to be used by the second data port when coupled with the second communication link. The present disclosure contemplates that the determination of the second communication parameter set may further be provided by an operator, user, system administrator, central control, and/or the like associated with the network interface device 100.
In some embodiments, the network interface device 100 may perform the second link training process associated with the second data port based at least in part on the first communication parameter set for the first communication link. By way of example, the GPU/CPU 400 may read, retrieve, or otherwise access the saved first communication parameter set associated with the first data port and perform the second link training process using one or more of the saved first communication parameters. Such an embodiment may operate to reduce the time consumed for performing the second link training process, thereby reducing the overall time consumed for switching between the first data port and the second data port. As shown in operation 325, the network interface device 100 may commence transferring data via the second data port.
As shown in operation 230, the network interface device 100 may determine whether to activate the first data port associated with the first communication link concurrently with the second data port associated with the second communication link based at least in part on a network usage parameter set associated with a data plane of the network device. The network interface device 100 may determine whether to activate the first data port concurrently with the second data port based on at least one of information received from the data plane, network telemetry data from a telemetry system, or the like. The network telemetry data received from the telemetry system may include data traffic conditions or the like indicative of the usage of the network associated with the network interface device. The information received from the data plane may include information associated with the data to be transmitted. Based at least in part on the information received from the data plane and/or the network telemetry data received from the telemetry system, the network interface device may determine whether more than a single data port (e.g., the first data port in addition to the second data port) is required. In other words, the system determines whether to operate the network interface device in an “Active-Active” mode or an “Active-Passive” mode as described above.
Example telemetry data, as described herein, may refer to any data generated by transceiver subsystems associated with the networking interface device 100, including a central processing unit managing the transceiver, onboard processors, offboard processors attached to the unit, a data plane accelerator processor, the data link layer, a network layer, a transport layer, a session layer, a presentation layer, and/or an application layer as would be evident to one of ordinary skill in the art in light of the present disclosure. Such an example telemetry system may be implemented in hardware through a dedicated processor or through a software element running on any of the available processors (e.g., processor 406 or the like).
In some embodiments, the network interface device 100 may leverage artificial intelligence and/or machine learning techniques to predict network usage (e.g., a network usage parameter set) for the network using the network interface device during a first interval of time. The network interface device 100 may use the predicted network usage to determine whether to activate the first data port concurrently with the second data port. In some embodiments, the network interface device 100 may determine that the predicted network usage during the first interval of time meets a defined network usage criterion and activate the first data port concurrently with the second data port to satisfy the predicted network usage.
In some embodiments, the network interface device 100 may determine that second data port has failed to satisfy a defined operational quality criterion and may activate the first data port. In such embodiments, the network interface device 100 may deactivate the second data port and activate the first data port. The network interface device 100 may save the second communication parameter set and other settings applied to the second data port before deactivating the second data port, thereby placing the second data port in a standby or passive mode and allowing faster activation of the second data port when required. In other embodiments, the network interface device 100 may, instead of deactivating the second data port, maintain the second data port operational concurrently with the first data port while relying upon the first data port for primary communication.
With reference to
The GPU/CPU 400 may include or otherwise be in communication with processing circuitry 402 that is configurable to perform actions in accordance with one or more example embodiments disclosed herein. In this regard, the processing circuitry 402 may be configured to perform and/or control performance of one or more functionalities of the GPU/CPU 400 in accordance with various example embodiments, and thus may provide means for performing functionalities of the GPU/CPU 400 in accordance with various example embodiments. The processing circuitry 402 may be configured to perform data processing, application execution and/or other processing and management services according to one or more example embodiments. In some embodiments, the GPU/CPU 400 or a portion(s) or component(s) thereof, such as the processing circuitry 402, may be embodied as or comprise a chip or chip set. In other words, the GPU/CPU 400 or the processing circuitry 402 may comprise one or more physical packages (e.g., chips) including materials, components and/or wires on a structural assembly (e.g., a baseboard). The structural assembly may provide physical strength, conservation of size, and/or limitation of electrical interaction for component circuitry included thereon. The GPU/CPU 400 or the processing circuitry 402 may therefore, in some cases, be configured to implement an embodiment of the disclosure on a single chip or as a single “system on a chip.” As such, in some cases, a chip or chipset may constitute means for performing one or more operations for providing the functionalities described herein.
In some example embodiments, the processing circuitry 402 may include a processor 406 and, in some embodiments, such as that illustrated in
The processor 406 may be embodied in a number of different ways. For example, the processor 406 may be embodied as various processing means such as one or more of a microprocessor or other processing element, a coprocessor, a controller or various other computing or processing devices including integrated circuits such as, for example, an ASIC (application specific integrated circuit), an FPGA (field programmable gate array), or the like. Although illustrated as a single processor, it will be appreciated that the processor 406 may comprise a plurality of processors. The plurality of processors may be in operative communication with each other and may be collectively configured to perform one or more functionalities of the GPU/CPU 400 as described herein. The plurality of processors may be embodied on a single computing device or distributed across a plurality of computing devices collectively configured to function as the GPU/CPU 400. In some example embodiments, the processor 406 may be configured to execute instructions stored in the memory 404 or otherwise accessible to the processor 406. As such, whether configured by hardware or by a combination of hardware and software, the processor 406 may represent an entity (e.g., physically embodied in circuitry—in the form of processing circuitry 402) capable of performing operations according to embodiments of the present disclosure while configured accordingly. Thus, for example, when the processor 406 is embodied as an ASIC, FPGA or the like, the processor 406 may be specifically configured hardware for conducting the operations described herein. Alternatively, as another example, when the processor 406 is embodied as an executor of software instructions, the instructions may specifically configure the processor 406 to perform one or more operations described herein.
In some example embodiments, the memory 404 may include one or more non-transitory memory devices such as, for example, volatile and/or non-volatile memory that may be either fixed or removable. In this regard, the memory 404 may comprise a non-transitory computer-readable storage medium. It will be appreciated that while the memory 404 is illustrated as a single memory, the memory 404 may comprise a plurality of memories. The plurality of memories may be embodied on a single computing device or may be distributed across a plurality of computing devices collectively configured to function as the GPU/CPU 400. The memory 404 may be configured to store information, data, applications, instructions and/or the like for enabling the GPU/CPU 400 to carry out various functions in accordance with one or more example embodiments. For example, the memory 404 may be configured to buffer input data for processing by the processor 406. Additionally or alternatively, the memory 404 may be configured to store instructions for execution by the processor 406. As yet another alternative, the memory 404 may include one or more databases that may store a variety of files, contents or data sets. Among the contents of the memory 404, applications may be stored for execution by the processor 406 in order to carry out the functionality associated with each respective application. In some cases, the memory 404 may be in communication with one or more of the processor 406, communication interface 410, or the controller 408 via a bus(es) for passing information among components of the GPU/CPU 400.
In some example embodiments, the GPU/CPU 400 may further include a communication interface 410. In some cases, the communication interface 410 may be any means such as a device or circuitry embodied in either hardware, or a combination of hardware and software that is configured to receive and/or transmit data from/to a network and/or any other device or circuitry in communication with the processing circuitry 402. By way of example, the communication interface 410 may be configured to enable the GPU/CPU 400 to communicate with the one or more user devices. In this regard, for example, the communication interface 410 may be configured to be an analog to quantum communication bridge configured to covert physical layer digital signal representations from and/or to qubit states. The communication interface 410 may, for example, include an antenna (or multiple antennas) and supporting hardware and/or software for enabling communications with a wireless communication network (e.g., a wireless local area network, cellular network, and/or the like) and/or a communication modem or other hardware/software for supporting communication via cable, digital subscriber line (DSL), universal serial bus (USB), Ethernet or other methods.
In some example embodiments, the GPU/CPU 400 may include or otherwise control a controller 408. As such, the controller 408 may be embodied as various means, such as circuitry, hardware, a computer program product comprising computer readable program instructions stored on a computer readable medium (for example, the memory 404) and executed by a processing device (for example, the processor 406), or some combination thereof. The controller 408 may be capable of communication with one or more of the memory 404 or communication interface 410 to access, receive, and/or send data as may be needed to perform one or more of the functionalities of the controller 408 as described herein.
It will be understood that some embodiments of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams. It will be understood that each block included in the flowchart illustrations and/or block diagrams, and combinations of blocks included in the flowchart illustrations and/or block diagrams, may be implemented by one or more computer-executable program code portions. These computer-executable program code portions execute via the processor of the computer and/or other programmable data processing apparatus and create mechanisms for implementing the steps and/or functions represented by the flowchart(s) and/or block diagram block(s).
It will also be understood that the one or more computer-executable program code portions may be stored in a transitory or non-transitory computer-readable medium (e.g., a memory, and the like) that can direct a computer and/or other programmable data processing apparatus to function in a particular manner, such that the computer-executable program code portions stored in the computer-readable medium produce an article of manufacture, including instruction mechanisms that implement the steps and/or functions specified in the flowchart(s) and/or block diagram block(s).
The one or more computer-executable program code portions may also be loaded onto a computer and/or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer and/or other programmable apparatus. In some embodiments, a computer-implemented process is thus produced, such that the one or more computer-executable program code portions which execute on the computer and/or other programmable apparatus provide operational steps to implement the steps specified in the flowchart(s) and/or the functions specified in the block diagram block(s). Alternatively, computer-implemented steps may be combined with operator and/or human-implemented steps in order to carry out an embodiment of the present disclosure.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative, and not restrictive, and that this disclosure is not to be limited to the specific constructions and arrangements shown and described, as various other changes, combinations, omissions, modifications and substitutions, in addition to those set forth in the above paragraphs, are possible. Those skilled in the art will appreciate that various adaptations and modifications of the just described embodiments can be configured without departing from the scope and spirit of the present disclosure. Therefore, it is to be understood that, within the scope of the appended claims, the embodiments of the present disclosure may be practiced other than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 20220100727 | Sep 2022 | GR | national |
