Patent Application
20220407813
The technology of the disclosure relates generally to transactions over a communication interface, and specifically to using an implied sequence numbering for transactions in a processor-based system.
II. Background
Processor-based systems may conventionally include a plurality of individual components, whether on a monolithic die, on multiple dies which are integrated together in a package, or across multiple dies or packages on a platform or motherboard. In order to allow such individual components to communicate with one another, they may be coupled together with a communications interface. Such a communications interface may permit data to be transferred to and from individual components. One conventional interface for such data transmission is the Peripheral Component Interconnect Express bus (PCIe), which provides relatively high-speed serial communications between components of a processor-based system. Communications interfaces with these characteristics, such as PCIe, may conventionally provide a mechanism to handle errors that may occur during transmissions (in addition to defining various signaling protocols and layers associated with the interface). Further, such communications interfaces may support messages of varying lengths, and may further allow large messages to be divided up into some number of smaller packets of data which may be transmitted individually via the communications interface and then reassembled by the receiver in order to reconstruct the entire message.
In order to support messages of varying length, and particularly messages that may span multiple individual packets, each packet conventionally includes metadata related to the message for which the packet includes a portion. This metadata can include, but is not limited to, an indication of the length of the packet, a sequence number which identifies which packet in a multiple packet sequence a particular packet is, and data quality information (such as a CRC value, parity value, ECC value, or other error checking or correction information). The sequence number allows the receiver of the packet to both reassemble the original message (because the order of the multiple packets can be determined from the sequence numbers), and to provide a precise error indication to the transmitter when necessary (because it can identify a specific packet sequence number as being affected by an error). This error information may permit the transmitter to take corrective action, which may conventionally include replaying the transmission of the packet associated with the sequence number that was affected by an error. Thus, the conventional approach enables error checking and error correction by a transmitter and receiver. However, including an individual sequence number with every packet also consumes bandwidth on the communications interface, as the bits used by the sequence number could ordinarily be used for data transmission instead.
Aspects disclosed in the detailed description include apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based system. In exemplary aspects, the processor-based system includes a transmit circuit that is configured to generate a packet to be transmitted. The transmit circuit is configured to generate an implied sequence number for each entry to be transmitted as a packet. The transmit circuit is configured to generate a packet to be transmitted based on an entry, wherein the packet including the payload information and the transmit check value based on the implied sequence number and associated with the entry. In this manner, including an individual sequence number with every transmitted packet may be reduced or avoided to reduce or avoid consuming bandwidth on the communications interface, as the bits used by the sequence number could ordinarily be used for data transmission instead. A receiver circuit in the same or different processor-based is configured to receive the transmitted packet including the payload and the transmit check value, wherein the transmit check value is based on the transmit sequence number. The receive circuit is then configured to generate an expected check value based on the receive sequence number, and perform a comparison of the transmit check value and the expected check value.
In one exemplary aspect, a processor-based system is provided. The processor-based system comprises a transmit circuit. The transmit circuit comprises a replay buffer including a plurality of entries, each entry including payload information and associated with an implied sequence number. The transmit circuit also comprises a data quality check generation circuit configured to receive an implied sequence number associated with an entry of the replay buffer and to generate a transmit check value based on the implied sequence number. The transmit circuit is configured to generate a packet based on an entry of the replay buffer, the packet including the payload information and the transmit check value associated with the entry.
In one exemplary aspect, a processor-based system is provided. The processor-based system comprises a receive circuit configured to receive a packet over a communications interface, wherein the packet includes a transmit check value. The receive circuit comprises an implied sequence number tracking circuit configured to track a current implied sequence number associated with the packet. The receive circuit also comprises a data quality check circuit configured to receive the packet and the current implied sequence number, generate an expected check value based on the current implied sequence number, and compare the expected check value with the transmit check value received in the packet. The receive circuit also comprises a payload write circuit configured to write the payload information in the packet into a receive buffer if the comparison between the expected check value and the transmit check value received in the packet indicates a match. The receive circuit also comprises a non-acknowledge generation circuit configured to generate an error indication if the comparison between the expected check value and the transmit check value received in the packet does not indicate a match.
In another exemplary aspect, a processor-based system is provided. The processor-based system comprises a means for transmitting, wherein the means for transmitting comprises a means for storing a plurality of entries, each entry including payload information and associated with an implied sequence number, and a means for generating a data quality check configured to receive an implied sequence number associated with an entry of the means for storing a plurality of entries and to generate a transmit check value based on the implied sequence number. The means for transmitting further comprises a means for generating a packet based on an entry of the means for storing a plurality of entries, the packet including the payload information and the transmit check value associated with the entry.
In another exemplary aspect, a processor-based system is provided. The processor-based system comprises a means for receiving, wherein the means for receiving comprises a means for receiving a packet over a means for communication, the packet including a transmit check value. The means for receiving further comprises a means for tracking an implied sequence number associated with the packet, a means for checking data quality of the received packet and the current implied sequence number, a means for generating an expected check value based on the current implied sequence number, a means for comparing the expected check value with the transmit check value received in the packet, and a means for writing the payload information in the packet into a means for storing if the comparison between the expected check value and the transmit check value received in the packet indicates a match, and a means for generating a non-acknowledgement as an error indication if the comparison between the expected check value and the transmit check value received in the packet does not indicate a match.
In another exemplary aspect, a method of performing transactions using an implied sequence number is provided. The method comprises generating a transmit check value at a transmit circuit based on an implied sequence number. The method also comprises generating a packet including a payload and the transmit check value at the transmit circuit. The method also comprises transmitting the packet.
In another exemplary aspect, a method of performing transactions using an implied sequence number is provided. The method comprises receiving a packet including a payload and a transmit check value, the transmit check value based on a transmit sequence number. The method also comprises generating an expected check value based on a receive sequence number. The method also comprises performing a comparison of the transmit check value and the expected check value.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based system.
In this regard,
Those having skill in the art will recognize that, as described above, although the data check portion 180 is illustrated as a CRC-based data check, other data integrity checking information types may be used, so long as they can be combined with sequence number information by the transmitter in a way that allows the receiver to derive the sequence number information, and to perform any desired data integrity checking. Although the header portion 160 in
In this regard,
The receive circuit 250 may receive an input packet 290 (which in an illustrated aspect may correspond to the output packet 240 as transmitted by the transmit circuit 220) over the communications interface 205, and the input packet 290 may include length information 290a, payload 290b, and implied sequence number-based CRC information 290c. The receive circuit 250 includes a sequence number tracking circuit 270 and a CRC check circuit 280. At the beginning of a sequence of transactions, the sequence number tracking circuit 270 is initialized to a starting sequence number (which may correspond to a starting index number in the transmit circuit 220, such that the transmit circuit 220 and the receive circuit 250 have a same starting value upon which the implied sequence number-based CRC information 240c/290c, may be generated and compared). The sequence number tracking circuit 270 identifies when a new packet (such as input packet 290) has been received by the receive circuit 250, provides a current implied sequence number 270a to the CRC check circuit 280, and increments the current implied sequence number 270a to keep the receive circuit 250 synchronized with the transmit circuit 220 (i.e., the incremented current implied sequence number 270a will correspond to the next index number X for the subsequent packet that will be assembled and transmitted by the transmit circuit 220 to the receive circuit 250).
The CRC check circuit 280 receives the length information 290a, payload 290b, implied sequence number-based CRC information 290c, and the current implied sequence number 270a, and uses the above information to perform a comparison of the received implied sequence number-based CRC information 290c with a generated expected implied sequence number-based CRC value. The CRC check circuit 280 may generate the expected implied sequence number-based CRC value based on the current implied sequence number 270a, the length information 290a, and the payload 290b, as will be described further with reference to
The method then proceeds to block 320, by generating a packet including a payload and the transmit check value. For example, with respect to
The method may further proceed to block 330, by updating the transmit sequence number. For example, with respect to
The method continues in block 370, by performing a comparison of the transmit check value and the expected check value. For example, with respect to
The method may continue in block 375, by updating the receive sequence number. For example, with respect to
Those having skill in the art will appreciate that other aspects where the allocation of requests is controlled based on different parameters are within the scope of the teachings of the present disclosure. For example, in the case where an error indication is provided back to the transmit circuit 220 that the packet corresponding to the current implied sequence number 270a was not properly received, in one aspect the error indication may include a portion that directly identifies the sequence number of the packet (i.e., for replay requests, the sequence number may not necessarily be implied). In another aspect, the sequence number may not be included in the error indication to the transmit circuit 220, but instead only the implied sequence number-based CRC information 290c may be provided, and the transmit circuit 220 may perform a comparison of the error indication received from the receiver against all outstanding packets to determine which of the entries 211a-211e is associated with the error indication.
The exemplary system including a communications interface that implements implied sequence numbering according to aspects disclosed herein and discussed with reference to
In this regard,
Other initiator and target devices can be connected to the system bus 410. As illustrated in
The CPU(s) 405 may also be configured to access the display controller(s) 460 over the system bus 410 to control information sent to one or more displays 462. The display controller(s) 460 sends information to the display(s) 462 to be displayed via one or more video processors 461, which process the information to be displayed into a format suitable for the display(s) 462. The display(s) 462 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
Although only the processor 401 and the memory system 450 have been illustrated as including transmitter(s) and receiver(s) as described with reference to
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The initiator devices and target devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read. Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art, An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
