This application claims the priority benefit of Taiwan application serial no. 100122638, filed on Jun. 28, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
1. Field of the Invention
The present invention relates to a semiconductor device, and an operation method and an application circuit thereof, and more particularly to a semiconductor device applied in a battery-less electronic timer, and an operation method and an application circuit thereof.
2. Description of Related Art
In the Japanese Patent JP3959340, a solid-state aging device (SSAD) that includes a circuit for controlling expiration has been proposed as the integrated circuit of a battery-less electronic timer (IBLET). The fundamental idea of controlling expiration is to suppress the error in timing caused by anomalous charge loss, as shown in
In the initial state, as shown in
Since main reliability issue of time cell is an anomalous charge loss, which results in the degradation of the lifetime of the time cell, it can be regarded that the resultant lifetime is determined by the time cell without the anomalous charge loss as long as the number of parallel-connected time cells is large enough. Therefore, when a large number of time cells are connected in parallel, the lifetime shall be controllable.
In the prior art, there are basically two types of time cell structure and fabrication method thereof. One type of time cell is the single polysilicon time cell, which can be fabricated along with the CMOS fabrication line (U.S. Pat. No. 7,652,317, US Patent Application Publication US2008/0079057), as shown in
In a single polysilicon time cell structure, the N-type control gate NCG and the N-type source NS, the N-type drain ND on the surface of the P-type substrate PSUB are fabricated as diffusion layers. The shallow-trench-isolation (STI) 202 or the local oxidation of silicon (LOCOS) is disposed to electrically isolate the N-type control gate NCG from the N-type source NS and N-type drain ND. The fabrication of a typical shallow-trench isolation structure can be achieved by etching a shallow trench in the substrate between the N-type control gate NCG and the other diffusion layers (the N-type source NS and the N-type drain ND), followed by filling the shallow trench with an isolation material, such as silicon dioxide or other dielectric materials. The fabrication of a typical LOCOS structure can be achieved by depositing a mask, such as silicon nitride (Si3N4) on a blank silicon wafer, followed by patterning the mask via photolithography and forming a silicon oxide layer (SiO2) on the exposed silicon surface (exposed by an etching technique). This silicon oxide layer may serve to electrically isolate the N-type control gate NCG from the other diffusion layers (the N-type source NS and the N-type drain ND).
Major issue of anomalous charge loss of time cell, which is mentioned above, is trap located in insulating layer adopted in time cell. This trap sometimes becomes active to increase the leakage of electron through the insulating layer, and thereby causes the anomalous charge loss of time cell. (H. Watanabe, et. al., IEEE Trans. Elec. Dev. Vol. 58, issue 3, pp. 792-797.).
The present invention is directed to a semiconductor device, and an operation method and an application circuit thereof, in which the accuracy of a battery-less electronic timer using the semiconductor device is enhanced.
An exemplary embodiment of the present invention provides a semiconductor device including a first conductive-type semiconductor substrate, a gate dielectric layer, a floating gate, a first conductive type well, a second conductive type well, a second conductive type source diffusion layer, a second conductive type drain diffusion layer and a second conductive type control gate diffusion layer. The gate dielectric layer is formed on the first conductive type semiconductor substrate. The floating gate is formed on the gate dielectric layer. The second conductive type well is formed in the first conductive type semiconductor substrate. The first conductive type well is formed in the second conductive type well. The second conductive type source diffusion layer and the second conductive type drain diffusion layer are formed respectively at two sides of the floating gate in the first conductive type semiconductor substrate. The second conductive type source diffusion layer, the second conductive type drain diffusion layer and the floating gate are formed to compose a second conductive type transistor, wherein the second conductive type transistor is configured at the exterior of the second conductive type well. Additionally, the second conductive type control gate diffusion layer is formed in the first conductive type well.
According to an exemplary embodiment of the invention, the above semiconductor device further includes a source contact layer, a drain contact layer, a control gate contact layer, and at least a second well contact layer, a first well contact layer, and a substrate contact layer. The source contact layer is disposed on the second conductive type source diffusion layer. The drain contact layer is disposed on the second conductive type drain diffusion layer. The control gate contact layer is disposed on the second conductive type gate diffusion contact layer. The second well contact layer is disposed on the second conductive type well. The first well contact layer is disposed on the first conductive type well. The substrate contact layer is disposed on the first conductive type semiconductor substrate.
According to an exemplary embodiment of the invention, the second well contact layer is configured between the second conductive type transistor and the first conductive type well.
According to an exemplary embodiment of the invention, the overlapping area of the floating gate and the second conductive type control gate diffusion layer is greater than the overlapping area of the floating gate and the second conductive type transistor's channel area on the surface of the first conductive type semiconductor substrate between the source contact layer and the drain contact layer.
The present invention provides an operation method of a semiconductor device. To read the charge state of the semiconductor device, a sweep read bias on the control gate contact layer; grounding the source contact layer and the substrate contact layer; applying a positive bias to the drain contact layer, applying a negative bias to the first well contact layer; applying a positive bias to or grounding the second well contact layer. To program the device, a first bias is applied to the control gate contact layer, while the source contact layer, the drain contact layer, and the substrate contact layer are grounded; a second bias is applied to the first well contact layer and the second well contact layer or the first well contact layer and the second well contact layer are grounded. The first bias is greater than ground and the second bias is greater than ground or equal to the ground and smaller than or equal to the first bias. To erase the semiconductor device, a negative bias is applied to the control gate contact layer and the first well contact layer, a positive bias is applied to the source contact layer and the drain contact layer, the second well contact layer and the substrate contact layer are grounded.
The present invention also provides a semiconductor device including a first conductive type semiconductor substrate, a gate dielectric layer, a floating gate, a second conductive type well, a first conductive type well, a second conductive type source diffusion layer, a second conductive type drain diffusion layer, and a second conductive type control gate diffusion layer. The gate dielectric layer is formed on the first conductive type semiconductor substrate. The floating gate is formed on the gate dielectric layer. The second conductive type well is formed in the first conductive type semiconductor substrate. The first conductive type well is formed in the second conductive type well. The second conductive type complementary capacitor gate diffusion layer is formed in the first conductive type semiconductor substrate, outside the second conductive well. The second conductive type source diffusion layer and the second conductive type drain diffusion layer are respectively formed at two sides of the floating gate in the first conductive type semiconductor substrate. The second conductive type source diffusion layer, the second conductive type drain diffusion layer, and the floating gate are formed to compose a second conductive type transistor, wherein the second conductive type transistor is configured between the second conductive type well and the second conductive type complementary capacitor gate diffusion layer. Moreover, the second conductive type control gate diffusion layer is formed in the first conductive type well.
According to an exemplary embodiment of the invention, the above semiconductor device further includes a complementary capacitor gate contact layer, disposed on the second conductive type complementary capacitor gate diffusion layer.
The present invention provides an operation method of the semiconductor device. To read the charged state of the semiconductor device, a sweep bias is applied to the control gate and a positive bias is applied to the drain contact layer, while the source contact layer, the first well contact layer, the second well contact layer, the complementary capacitor gate contact layer and the substrate contact layer are grounded. To program the semiconductor device, a first bias is applied to the control gate contact layer and a second bias is applied to the source contact layer, the drain contact layer, the first well contact layer, and the second well contact layer, while the complementary capacitor gate contact layer and the substrate contact layer are grounded. Further, the first bias is greater than ground and the second bias is greater than ground and is less than the first bias. To erase the semiconductor device, a negative bias is applied to the control gate contact layer and the first well contact layer, while the source contact layer, the drain contact layer, the second well contact layer, and the substrate contact layer are grounded. Moreover, a second bias is applied to the complementary capacitor gate contact layer.
The invention provides a semiconductor device including a first conductive-type semiconductor substrate, a gate dielectric layer, a floating gate, a second conductive type well, a first conductive type well, a second conductive type source diffusion layer, a second conductive type drain diffusion layer, and a second conductive type control gate diffusion layer. The gate dielectric layer is formed on the first conductive type semiconductor substrate. The floating gate is formed on the gate dielectric layer. The second conductive type well is formed on the first conductive type semiconductor substrate. The first conductive type well is formed in the second conductive type well. The second conductive type complementary capacitor gate diffusion layer is formed in the first conductive type well. The second conductive type control gate diffusion layer is formed in the first conductive type semiconductor substrate and at the exterior of the second conductive type well. The second conductive type source diffusion layer and the second conductive type drain diffusion layer are respectively formed at two sides of the floating gate in the first conductive type semiconductor substrate, wherein the second conductive type source diffusion layer, the second conductive type drain diffusion layer, and the floating gate are formed to compose a second conductive type transistor. Further, the second conductive type transistor is configured between the second conductive type well and the second conductive type control gate diffusion layer.
The invention provides an operation method of the semiconductor device. To read the charged state of the semiconductor device, a sweep bias is applied to the control gate contact layer, a positive bias is applied to the drain contact layer, and the first well contact layer, the second well contact layer, the complementary capacitor gate contact layer, and the substrate contact layer are grounded. To program the semiconductor device, a positive bias is applied to the control gate contact layer, and a negative bias is applied to the first well contact layer and the complementary capacitor gate contact layer, while the source contact layer, the drain contact layer, the second well contact layer, and the substrate contact layer are grounded. To erase the semiconductor device, a first bias is applied to the complementary capacitor gate contact layer and a second bias is applied to the first well contact layer and the second well contact layer, while the control gate contact layer, the source contact layer, the drain contact layer, and the substrate contact layer are grounded. Further, the first bias is greater than ground and the second bias is greater than ground and smaller than the first bias.
The invention also provides a parallel chain circuit model including a plurality of the above semiconductor devices, wherein the source contact layer and the drain contact layer of each semiconductor device are respectively connected to the first terminal and the second terminal.
The invention also provides serial-connected parallel-chain circuits composed of a plurality of the above semiconductor devices, wherein these parallel-chain circuits are connected in serial.
The invention also provides a serial chain circuit model including a plurality of the above semiconductor devices serially connected together, wherein the drain contact layer of the first semiconductor device in the serial chain circuit model is electrically connected to the first terminal, while the source contact layer of the last semiconductor device in the serial chain circuit model is electrically connected to the second terminal.
The invention also provides parallel-connected serial-chain circuits composed of a plurality of the above semiconductor devices, wherein these serial-chain circuits are connected in parallel.
In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures are described in detail below.
Reference now is made to the accompanying drawings to describe the specific embodiments and examples of the invention. Whenever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Moreover, the semiconductor device 600 also includes a source contact layer 612A, a drain contact layer 614A, a control gate contact layer 616A, at least a second well contact layer 608A, a first well contact layer 610A and a substrate contact layer (not shown). The source contact layer 612A is disposed on the second conductive type source diffusion layer 612. The drain contact layer 614A is disposed on the second conductive type drain diffusion layer 614. The control gate contact layer 616A is disposed on the second conductive type control gate diffusion layer 616. The second well region contact layer 608A is disposed on the second conductive type well 608. The first well contact layer 610A is disposed on the first conductive type well 610. The substrate contact layer is disposed at the first conductive type semiconductor substrate.
Assuming the first conductive type is P-conductive type, the second conductive type is N-conductive type, the first conductive type and the second conductive type are respectively described as P-type and N-type in the following disclosure.
In the semiconductor device 600, the gate dielectric layer 604 is formed on the P-type semiconductor substrate 602, the floating gate 606 is formed on the gate dielectric layer 604, the N-type well 608 is formed in the P-type semiconductor substrate 602, the P-type well 610 is configured in the N-type well 608, and the N-type control gate diffusion layer 616 is formed in the P-type well 610. Moreover, the N-type source diffusion layer 612 and the N-type drain diffusion layer 614 are respectively formed in the P-type semiconductor layer 602 at two sides of the floating gate 606. The N-type source diffusion layer 612, the N-type drain diffusion layer 614, and the floating gate 606 together form an N-type transistor, and this N-type transistor is configured at the exterior of the N-type well 608.
During the operation of the semiconductor device 600, of voltage pulse is applied to each contact layer to perform the read, program and erase operations of the semiconductor device 600. By controlling the biases applied to each contact layer and adjusting the doping profiles in the P-type semiconductor substrate 602, the leakage current between the N-type control gate diffusion layer 616 and the N-type transistor can be reduced. The equivalent circuit of the semiconductor device 600 in this exemplary embodiment as shown in
More specifically, when the semiconductor device 600 in
As shown in Table 1 above, to read the threshold voltage shift of the semiconductor device 600, a sweep bias is applied to the control gate contact layer 616A, while a positive bias is applied to the drain contact layer 614A. A negative bias is applied to the first well contact layer 610A to prevent a forward bias between the P-type well 610 and the N-type well 608. Moreover, a positive bias or ground is applied to the second well contact layer 608A, while the source contact layer 612A and the substrate contact layer (not shown) are grounded.
To program the semiconductor device 600, a first bias is applied to the control gate contact layer 616A. Concurrently, a second bias or ground is applied to the first well contact layer 610A and the second well contact layer 608A, wherein the first bias is greater than ground, while the second bias is great than or equal to ground and smaller than or equal to the first bias. Further, the source contact layer 612A, the drain contact layer 614A and the substrate contact layer (not shown) are grounded. Since the control capacitance Cc is relatively larger than the gate capacitance Cg, electrons are injected from the P-type semiconductor substrate 602, the N-type source diffusion layer 612 and N-type drain diffusion layer 614 into the floating gate 606. Accordingly, the threshold voltage of the semiconductor device 600 is increased.
To erase the semiconductor device 600, a negative bias is applied to the control gate contact layer 616A and the first well contact layer 610A. Concurrently, a positive bias is applied to the source contact layer 612A and the drain contact layer 614A. Additionally, the second well contact layer 608A and the substrate contact layer are grounded. Accordingly, electrons are released from the floating gate 606 to the channel between the N-type source diffusion layer 612 and the N-type drain diffusion layer 614 to lower the threshold voltage of the semiconductor device 600.
As an example, the biases that are applied to the various contact layers in the semiconductor device 600 in the exemplary embodiment illustrated in
As shown in Table 2, to read the threshold voltage shift of the semiconductor device 600, a sweep read is performed by applying a voltage of −2 V to 2 V to the control gate contact layer 616A and 0.5 V is concurrently applied to the drain contact layer 614A. The biases applied to the source contact layer 612A, the second well contact layer 608A and the substrate contact layer are respectively 0 V. To program the semiconductor device 600, the control gate contact layer 616A is applied with 10V and the first well contact layer 610A and the second well contact layer 608A are respectively applied with 5V, while the bias of other contact layers are 0 V. Since the floating gate 606 is negatively charged by programming, the threshold voltage of the semiconductor device 600 increases. To erase the semiconductor device 600, −8V is applied to the control gate contact layer 616A and the first well contact layer 610A, while the second well contact layer 608A and the substrate contact layer are respectively 0 V. Further, a bias of 2V is applied to the source contact layer 612A and the drain contact layer 614A. In this case, electrons flow from the floating gate FG 606 to the N-type drain diffusion layer 614 and the N-type source diffusion layer 612, and the threshold voltage of the semiconductor device 600 is decreased. It is also preferable that a bias of 10 V is applied to source and drain contact layers (612A and 614A), while a bias of 8V is applied to second well contact layer 610A and substrate contact layer. The control gate contact layer 616A and the first well contact layer 610A are grounded.
It is worthy to note that, in some exemplary embodiments, the operation voltages in Table 2 for erasing the semiconductor device 600, the source contact layer 612A and the drain contact layer 614A are grounded (in other words, in the semiconductor device 600, only the control gate contact layer 616A and the first well contact layer 610A are applied with a negative bias, while the bias of other contact layers is 0V). Since the control capacitance Cc is greater than the gate capacitance Cg, electrons flow from the floating gate 606 to the P-type semiconductor substrate 602, the N-type diffusion layer 612 and the N-type drain diffusion layer 614. Accordingly, the floating gate 606 is positively charged to lower the threshold voltage of the semiconductor device 600.
Referring to
To resolve the problem of fluctuation of lifetime resulted from anomalous charge loss, a plurality of normally-off type battery-less electronic timers (which are semiconductor devices 600) may be connected in parallel. As shown in the parallel-chain circuit model in
As shown in
Specifically speaking, when the semiconductor device 1400 of the exemplary embodiment shown in
As shown in Table 3, to read the threshold voltage shift, a sweep voltage is applied to the control gate contact layer 616A, while a positive bias is concurrently applied to the drain contact layer 614A and the other contact layers are grounded.
To program the semiconductor device 1400, a first bias is applied to the control gate contact layer 616A. A second bias is concurrently applied to the source contact layer 612A, the drain contact layer 614A, the first well contact layer 610A and the second well contact layer 608A. Further, the complementary capacitor gate contact layer 1402A and the substrate contact layer are grounded. The first bias is greater than ground, while the second bias is greater than or equal to ground, and is smaller than or equal to the first bias. Since the control capacitance Cc is greater than the sum of the gate capacitance Cg and the complementary capacitor capacitance Ct (Cc>Cg+Ct), electrons flow from the N-type complementary capacitor gate diffusion layer 1402 to the floating gate 606 through the gate dielectric layer 604. The floating gate 606 is negatively charged and the threshold voltage of the semiconductor device 1400 is thereby increased.
To erase the semiconductor device 1400, a negative bias is applied to the control gate contact layer 616A and the first well contact layer 610A. Concurrently, a positive bias is applied to the complementary capacitor gate contact layer 1402A, while other contact layers are grounded. Accordingly, electrons flow from the floating gate 606 to the N-type complementary capacitor gate diffusion layer 1402 through the gate dielectric layer 604 to positively charge the floating gate 606. The threshold voltage of the semiconductor device 1400 is thereby decreased.
More specifically, the operation method of the semiconductor device 1600 of the exemplary embodiment as illustrated in
As shown in Table 4, to read the threshold voltage shift of the semiconductor device, a sweep bias is applied to the control contact layer 616A and a positive bias is applied to the drain contact layer 614A, while other contact layers are grounded.
To program the semiconductor device 1600, a positive bias is applied to the control gate contact layer 616A, and a negative bias is concurrently applied to the first well contact layer 610A and the complementary capacitor gate contact layer 1402A, respectively, while other contact layers are grounded. It is worthy to note that, since the control capacitance Cc is greater than the sum of the gate capacitance Cg and the tunnel capacitance Ct (Cc>Cg+Ct), electrons flow from the N-type complementary capacitor gate diffusion layer 1402 to the floating gate 606 through the gate dielectric layer 604 to negatively charge the floating gate 606. Accordingly, the threshold voltage of the semiconductor device 1400 is increased.
To erase the semiconductor device 1600, a first bias is applied to the complementary capacitor gate contact layer 1402A, and a second bias is concurrently applied to the first well contact layer 610A and the second well contact layer 608A, while the other contact layers are grounded. Further, the first bias is greater than ground, while the second bias is greater than or equal to ground, and less than or equal to the first bias. Accordingly, electrons flow from the floating gate 606 to the N-type complementary capacitor gate diffusion layer 1402 through the gate dielectric layer 604 to positively charge the floating gate 606. As a result, the threshold voltage of the semiconductor device 1400 is decreased.
It is worthy to note that, although the above illustrated exemplary embodiments herein refer to the operation methods and the application circuits of a semiconductor device with the first conductive type being the P-conductive type and the second conductive type being the N-conductive type, it is to be understood that these embodiments are presented by way of example and not by way of limitation. In other exemplary embodiments, the first conductive type is N-conductive type, while the second conductive type is the P-conductive type. Further, the shape of the floating gate disclosed herein is presented by way of example and not by way of limitation. It is to be appreciated that, as long as the equivalent capacitance generated by the control gate diffusion layer is greater than the other capacitance of which dielectric film electrons tunnel through, a floating gate of other shapes can be implemented in accordance with the invention. Additionally, the parallel chain circuit 900A, the serial connected parallel-chain circuit 1000A, the serial chain circuit 1200A, the parallel connected serial-chain circuit 1300A are constructed with the semiconductor device 600. However, it should be appreciated that the invention is not limited as such. Parallel chain circuits 900B-900D as shown in
In accordance to the exemplary embodiments disclosed herein, by applying a bias to the second conductive type well and the first conductive type well, and enhancing the dopant distribution in the first conductive type semiconductor substrate, leakage current from the second conductive type control gate diffusion layer to the second conductive type source diffusion layer and the second conductive type drain diffusion layer is mitigated. It is noteworthy to say that, in the semiconductor device of the exemplary embodiments disclosed herein, the isolation layers are precluded. Accordingly, in order to suppress the leakage current between the second conductive type control gate diffusion layer, the second conductive type source diffusion layer and the second conductive type drain diffusion layer, we introduced the first conductive type well and the second conductive type well. This substantially decreases the production cost of integrated battery-less electronic timer.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Number | Date | Country | Kind |
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100122638 | Jun 2011 | TW | national |