This application claims priority to Chinese Patent Application No. 201210413817.2 filed on Oct. 25, 2012.
Nowadays the FPGA has become “glue” for modern digital application systems and Digital Signal Processor (DSP) chip application systems due to a great amount of Flip-Flop (FF) disposed in the FPGA and many Input/output (I/O) pins of the FPGA. The programmability of the FPGA improves the interface capability of the DSP. The logical operation in the FPGA chip is saved in a certain storage medium in the form of a configuration file.
Now, the following scene often occurs in product or manufacturing platforms: among different products of a same series, the general architectures of systems are similar but some slight differences still exist therein. Therefore, to reduce the cost in hardware development and manufacturing, a common solution is to design hardware parts compatible with each other into one adapter which is used to accommodate general-purpose devices such as a CPU and an FPGA (i.e., join with different platforms through a slot). However, in this mode, both the hardware and the software of the adapter can use a same FPGA version, but the FPGA needs to use different images to match with corresponding platforms because the pin controlled by the FPGA will be different when being defined on different platforms. As a result, in order to avoid damage caused to the hardware due to different IO electrical signal levels or directions, it shall be particularly noted that different FPGA versions shall not be mixed for use. However, this significantly adds to the difficulty in updating and maintenance of the FPGA version as well as in such operations as storage and loading on the FPGA version board.
It may therefore be desirable to provide an FPGA application merging system for multiple platforms of a same series to solve the problem with the prior art that it is difficult to perform such operations as storage and loading on the FPGA board.
The present invention belongs to electronic digitization which generally relates to a Field Programmable Gate Array FPGA application merging system, and more particularly, to an FPGA application merging system for multiple platforms of a same series.
To achieve the aforesaid objective and other related objectives, examples of the present invention may provide a FPGA application merging system for multiple platforms of a same series, which is used in a testing system comprising an adapter and at least two platforms. The FPGA application merging system comprises:
at least two functional modules corresponding to the at least two platforms respectively;
an IO selector connected to the at least two functional modules respectively, and configured to select one of the at least two functional modules adaptively; and
an IO attribute controller connected to the IO selector, and configured to select an attribute of an IO of the FPGA application merging system in accordance with the selected one of the at least two functional modules, wherein each IO of the FPGA application merging system has a three-state attribute, i.e., an input state, an output state and a high impedance state.
In another example embodiment, the FPGA application merging system for multiple platforms of a same series further comprises an IO pin connected to the FPGA application merging system, and the IO pin is used to embed the FPGA application merging system into the adapter.
In another example embodiment, the IO attribute controller further comprises a programmable input output block (IOB).
In another example embodiment, each IO of a general-purpose (GPIO) IO ports of the FPGA application merging system to be used by the IO attribute controller has the three-state attribute, i.e., can be configured in real time into the input state, the output state, or the high impedance state.
In another example embodiment, the programmable IOB comprises the three-state logic control port, an output port and an input port.
In another example embodiment, when a signal level at the three-state logic control port is at a low level, the IO of the FPGA application merging system is at the output state; and when the signal level at the three-state logic control port is at a high level, the IO of the FPGA application merging system is at the high impedance state.
In another example embodiment, the FPGA application merging system utilizes a two-stage structure to control the IO of the FPGA application merging system, and the two-stage structure refers to the IO selector and the IO attribute controller.
In another example embodiment, the IO selector at a first stage of the two-stage structure maps an IO configuration of one of the at least two functional modules to the IO of the FPGA application merging system.
In another example embodiment, the IO attribute controller at a second stage of the two-stage structure configures the IO attribute of each IO of the FPGA application merging system in accordance with one of the at least two functional modules.
Some examples of the present invention may provide a Field Programmable Gate Array (FPGA) application merging system for multiple platforms of a same series, which is used in a testing or manufacturing system comprising an adapter and at least two platforms, the FPGA application merging system comprises at least two functional modules corresponding to the at least two platforms respectively; an Input/output (IO) selector connected to the at least two functional modules respectively, and configured to select one of the at least two functional modules adaptively; an IO attribute controller connected to the IO selector, and configured to select an attribute of an IO of the FPGA application merging system in accordance with the selected one of the at least two functional modules; and an IO pin connected to the FPGA application merging system, wherein each IO of the FPGA application merging system has a three-state attribute comprising an input state, an output state and a high impedance state, and the IO pin is used to embed the FPGA application merging system into the adapter.
Still other examples of the present invention may provide a Field Programmable Gate Array (FPGA) application merging system for multiple platforms of a same series, used in a testing or manufacturing system comprising an adapter and at least two platforms, the FPGA application merging system comprises at least two functional modules corresponding to the at least two platforms respectively; an Input/output (IO) selector connected to the at least two functional modules respectively, and configured to select one of the at least two functional modules adaptively; an IO attribute controller connected to the IO selector, and configured to select an attribute of an IO of the FPGA application merging system in accordance with the selected one of the at least two functional modules, the IO attribute controller further comprising a programmable input output block (IOB); and an IO pin connected to the FPGA application merging system, wherein each IO of the FPGA application merging system has a three-state attribute comprising an input state, an output state and a high impedance state, and the IO pin is used to embed the FPGA application merging system into the adapter, wherein the programmable IOB comprises a three-state logic control port, an output port and an input port, and wherein when a signal level at the three-state logic control port is at a low level, the IO of the FPGA application merging system is at the output state; and when the signal level at the three-state logic control port is at a high level, the IO of the FPGA application merging system is at the high impedance state.
As described above, the FPGA application merging system for multiple platforms of a same series in accordance with the present invention can significantly reduce the cost of the FPGA version in later development, maintenance, storage, upgrading and so on, mitigate the difficulty of storage, loading and other operations on the board, and significantly increase the operation efficiency.
Additional features and advantages of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings examples which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
In the drawings:
Hereinbelow, implementation of the present invention will be described with reference to specific embodiments, and people skilled in the art can readily appreciate other advantages and efficacies of the present invention based on what disclosed in this specification. The present invention may further be implemented or applied in other different embodiments, and details in this specification may also be modified or changed according to different viewpoints and applications without departing from the spirit of the present invention.
Refer to the attached drawings. It shall be appreciated that, the attached drawings in this embodiment are only intended to illustrate the basic concept of the present invention, so the attached drawings only have components related to the present invention shown therein but are not depicted according to the numbers, shapes and dimensions of components in actual implementation. In actual implementation of the present invention, the forms, numbers and proportions of the components may be changed arbitrarily, and arrangement of the components may also be more complex.
Hereinbelow, the present invention will be described in detail with reference to the attached drawings and embodiments thereof.
The FPGA application merging system for multiple platforms of a same series is used in a testing or manufacturing system comprising an adapter 1 and at least two platforms 2. The FPGA application merging system 11 for multiple platforms of a same series is embedded in the adapter 1. In an application scene of the FPGA application merging system 11 as shown in
The FPGA application merging system for multiple platforms of a same series in accordance with the present invention merges the FPGA designs using different platforms into a same image. When there is a need to develop multiple platforms in which a same FPGA is suitable for use, the operation efficiency may be increased significantly.
This embodiment provides an FPGA application merging system 11 for multiple platforms of a same series. As shown in
From the viewpoint of different platforms, after the FPGA application merging system for multiple platforms of a same series identifies a specific platform and activates a corresponding function to the platform, it adapts a single functional module to the current platform, as shown in
The FPGA application merging system for multiple platforms of a same series in accordance with this embodiment is relatively complex in early architecture design as compared to the conventional solution in which a single mirror corresponds to a single platform, but is not increased in workload as compared to the conventional solution in which a plurality of versions are designed respectively. After the early design, advantages of this system are increased significantly. When there is a need to achieve a new characteristic of this system, it is sufficient to modify a set of codes if this characteristic is shared by the individual platforms, and this can significantly reduce the workload. However, in the conventional solution, multiple sets of codes need to be transplanted, which is very likely to cause errors. When there is a need to modify a code during maintenance of this system, the workload can also be significantly reduced if the modified part is shared by the individual platforms. For loading on the board, this system only needs to allot a storage space to a set of images without the worry of damage caused to the hardware due to mix-up of storage versions, and this can significantly reduce the cost of the hardware. Moreover, this system is adapted by the FPGA without the need of intervening in the loading process by software. The benefits of this system may be shown more clearly in Table 1.
According to the above descriptions, the present invention effectively overcomes the various shortcomings in the prior art, and is of a high industrial value.
The embodiments described above are only provided to illustrate the principles and efficacy of the present invention but not to limit the present invention. Modifications or changes may be made by those skilled in the art without departing from the spirits and scope of the present invention. Therefore, all equivalent modifications and changes made by those of ordinary skill in the art without departing from the spirits and technical concepts of the present invention shall also be covered within the scope of the claims.
Number | Date | Country | Kind |
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201210413817.2 | Oct 2012 | CN | national |