Patent Application
20080059679
The above and other features and advantages the present invention will become more apparent by means of description of the preferred embodiment with reference to the accompanying drawings, wherein the same or similar elements are indicated by the same or similar reference numbers.
Since the data transfer on system bus A is initiated by system bus master logic 104, according to the preferred embodiment, system bus master logic 104 exchanges data with internal DMA engine 105. The internal DAM engine performs the data transfer independently, so as to reduce the workload of the system processor to the minimum. The introduction of internal DMA engine can significantly improve the data throughput.
When transferring data between the system bus and the SD bus, due to the difference between the data transfer rate on different buses, a data buffer is needed to accommodate the rate differences therebetween. In addition, when the system bus interface and the SD bus interface are in different clock domains, the synchronization of data, command and control signals between different clock domains is needed. To this end, a SD synchronizer 109 is provided between the internal DMA engine 105 and the SD bus 116. The SD synchronizer 109 includes a data buffer (not shown in the figures), which is used for data synchronization between different clock domains. The SD synchronizer 109 also includes synchronization logic for command and control signals, so as to realize the synchronization of command and control signals between different clock domains. According to another embodiment, when the system bus and the SD bus meet certain requirements, the SD synchronizer 109 can be simplified as including the data buffer only. The data buffer is shared between the slave mode and the host mode. The size of the shared part depends on the application requirement, and the data buffer is not necessarily used entirely in both modes.
In addition, the circuit 100 also has a SD transceiver 108 which comprises synchronizer control logic to ensure effective access to the SD synchronizer 109. SD transceiver 108 controls the address signals of the data buffer in the SD synchronizer 109, and, before delivering the data from the SD bus interface 115 to the data buffer, conducts protocol conversion for the data, so as to realize the data transmission/receiving between the two interface domains. Similarly, the SD transceiver 108 can also be simply implemented as a data buffer controller for controlling effective access to the data buffer. In the host mode and slave mode, a single data buffer controller can be used to control effective access to the data buffer so as to prevent read failure or write overflow. Alternatively, separate data buffer controllers can be used in host mode and slave mode for controlling effective access to the data buffer.
As explained above, according to the preferred embodiment of the present invention, the system bus master logic 104 and the internal DMA engine 105 are implemented as separate functional modules, and the data buffer and the data buffer controller are implemented in SD synchronizer 109 and SD transceiver 108 respectively. However, those skilled in the art can appreciate that, the present invention is not limited to this. For example, when only the simplest functions are needed, the synchronization between different clock domains and the performance criteria of data throughput may not be taken into account. Therefore, the system bus master logic, the DMA engine, the SD transceiver and the SD synchronizer can also be implemented by a single system bus logic module which involves only the simplest functions.
As shown in
The SD bus agent 114 includes three sub-modules: SD command agent 111, SD data agent 112 and SD clock generator/feeder 113. The SD command agent 111 and SD data agent 112 realize the signal sequences on the command line and the data line as per the requirements of SD specification.
SD Clock generator/feeder 113, depending upon the configuration of the circuit 100, drives a clock at given frequency on the SD bus interface 115 in the host mode, and feeds the clock on the SD bus interface 115 to the modules within the circuit 100 in the slave mode. The SD clock generator/feeder 113 performs division, gating, inversion and shaping of the clock on the SD bus interface 115.
From
The SD bus agent 114, on basis of the command and data signal received, interacts with SD state machine 106 and SD synchronizer 109 via data/command lines 201 and 202 respectively. Specifically, SD bus agent 114, based on the commands, the corresponding response signals and the status of data line, enables the SD state machine 106 to enter corresponding logic status and output control signal corresponding to the status. The command and data used for data processing are sent into SD synchronizer 109, SD synchronizer 109 performs synchronization processing on the command/response and data, which are then delivered to the upper level of the system via the system bus A and submitted to the driver layer.
As shown in
According to the preferred embodiment, whether the application circuit 100 works in the host mode or in the slave mode is configured before use through reading/writing the register bank 107 via system bus B by MCU on the SoC under the control of the driver in the above described manner. However, those skilled in the art can appreciate that the present invention is not limited to the software configuration by means of MCU on SoC, rather, there are alternative ways to carry out the configuration. Possible means include: a mechanical switch, corresponding to the host mode when being opened, and corresponding to the slave mode when being closed; an electronic exciter, e.g. an electronic button, wherein the circuit enters the host mode when being powered on, and switches to the slave mode when the electronic button is pressed, and switches back to the host mode when the electronic button is pressed again; wireless controlling means, e.g., infra controller, which switches to the slave mode when receiving a series of pulses, and switches back to the host mode when receiving a subsequent series of pulses; and other manners not limited to the above ones. Based on the configurable control signals, the host function or the slave function are activated correspondingly. It should be noted that, the configuration of host mode/slave mode can not only be made during the power on stage, but also can be made at any time as needed so as to allow dynamic selection of host function or slave function.
The SD state machine 106 in
The state machine in slave mode includes four possible implementations, which comprise those based on MMC protocol, SD memory card protocol, SDIO protocol, and SDCombo protocol incorporating both SD memory and SDIO. The specifications of these implementations are defined in the following standards:
The MultiMediaCard System Specification, Version 4.0, MMCA Technical Committee;
SD Specifications Part 1, Physical Layer Specification, Version 2.00 Draft, Nov. 9, 2005, Technical Committee, SD Card Association,
SD Specifications Part E1, SDIO Specification, Version 1.20 Draft Jul. 8, 2005, Technical Committee, SD Card Association.
The implementation of the host state machine is defined in the following standard: SD Specification Part A2, SD Host Controller Standard Specification, Version 2.00 Draft, Jul. 29 2005, Technical Committee, SD Card Association.
As shown in
Card state machine: Receive various commands and responses in different states, and change its state according to the commands or responses received.
Transceiver: Control safe access to the data buffer. Since the read and write accesses to the data buffer come from different clock domains, the transceiver needs to handle address synchronization.
DMA engine: For high speed data throughput, the DAM engine is often used on the system bus side, enabling effective data read/write. Command CRC generator & checker: Generate command CRC7 checksum, and check command CRC7 result.
Data CRC generator & checker: Generate data CRC16 checksum, and check data CRC16 result.
SD bus interface: Realize the physical connection between the internal logic modules and the external SD device.
Register bank: Provide programming interface for software control and polling.
Clock controller: Realize gating, division and inversion of clock, so as to convert the original clock source for internal use. For simple device design, whether the SD memory card or SD bus bridge, the clock controller can be omitted.
Interrupt generator: According to the requirements of the host system, some statuses must be acknowledged and reported. This is usually performed by the interrupt mechanism. The interrupt generator can also wake up the host system depending upon the system low power strategy. For SD memory card, the interrupt mechanism is not needed.
As shown in
Host state machine: Receive various commands and responses in different states, and change its state according to the commands or responses received, card interrupt, and the change of its internal working status such as the completion of data transfer.
Transceiver: Control safe access to the data buffer. Since the read and write accesses to the data buffer often come from different clock domains, the transceiver needs to handle address synchronization.
DMA engine: For high speed data throughput, the DAM engine is often used on the system bus side, enabling effective data read/write.
Command agent: Generate command CRC7 checksum and check command CRC7 result, and perform bottom level electrical processing such as serial-parallel conversion, generate and check the starting bit/ending bit of the command signal line, and monitor the signal line conflict.
Data agent: Generate data CRC16 checksum and check data CRC16 result, and perform bottom level electrical processing such as serial-parallel conversion, generate and check the starting bit/ending bit of the data signal line, monitor the signal line conflict, and generate read-wait, busy signals.
SD bus interface: An analog function part for reliable connection between the SD functional modules and SD card, including pads, internal pull-up resister, etc.
Register bank: Provide programming interface for software control and polling.
Clock controller: Realize gating, division, inversion of clock and other functions, so as to output clock drive bus signal at given frequency in the host mode. Since the clock must be turned off during data buffer danger, the clock control module is necessary.
System bus interface: An interface for handling system bus transactions. The system bus may adopt any industrial standards or corporation private standard, such as AHB, Freescale IP bus, etc.
Interrupt generator: According to the requirements of the host system, some statuses must be acknowledged and reported. This is usually performed by the interrupt mechanism. The interrupt generator can also wake up the host system depending upon the system low power strategy. For SD memory card, the interrupt mechanism is not needed.
In addition, the host state machine may also include the card state sequence. This is an optional implementation, since the hardware part may not care what the current card state is—instead, it is to be handled by the driver. However, the SD host controller may include this module and send card command sequence, especially in the case where the master logic is implemented by pure hardware circuit.
As shown in
OTG state machine: Work in the host mode or the slave mode depending on the configuration. It includes card state sequence, which is necessary for slave device function, but the host can share the card state sequence to provide more smart control. The OTG state machine changes its state according to the various commands or responses received in different states and relevant control signals on the data line.
Synchronizer: For synchronizing various interactive signals between the system bus clock domain and SD bus clock domain. It includes a data buffer for compensating different data transfer rates between the two sides. Since SD slave device needs larger buffer size, the buffer here is usually larger than the buffer in the host controller. Thus, the sharing of the buffer will bring significant advantages.
Transceiver: Generate control signals on the data line, such as the read-wait control signal in host mode, and “busy”>indication signal in the slave mode, and so on. It is also used to automatically send commands in the host mode, e.g., to automatically send CMD12. The transceiver also includes control logic for the data buffer so as to ensure effective access to the data buffer.
DMA engine: For high speed host SD controller and bus bridge (whose speed may exceed 400 Mbps), the DAM engine is widely used on the system bus side.
Command agent: Generate command CRC7 checksum and check command CRC7 result, and perform bottom level electrical processing such as serial-parallel conversion, generate and check the starting bit/ending bit of the command signal line, and monitor the signal line conflict.
Data agent: Generate data CRC16 checksum and check data CRC16 result, and perform bottom level electrical processing such as serial-parallel conversion, generate and check the starting bit/ending bit of the data signal line, monitor the signal line conflict, and generate read-wait and busy signals.
Clock controller: For the host part, the clock controller is necessary. However, the slave device can share this module to provide more features such as power save and internal frequency division.
Register bank: Provide programming interface for software control and polling.
SD bus interface: Since the SD bus is an external bus outside the system, the SD bus interface is used to realize electrical analog (in contrast to digital logic) function.
Interrupt generator: According to the requirements of the host system, some statuses must be acknowledged and reported. This is usually performed by the interrupt mechanism. The interrupt generator can also wake up the host system depending upon the system low power strategy.
Memory controller interface (
In summary, the advantage of the SDCombo controller lies in the sharing of all the possible functional modules, including system bus interface or memory controller interface, DMA engine, data buffer, buffer controller, SD state machine, clock controller, data & command CRC generator/checker, the combined register bank for realizing programming integrity and SD bus interface.
Some optional shared modules, including interrupt generator, provide enhanced features. Since SD and MMC standards are still under development and tend to support more advanced transfer policies such as wider data bus, higher speed, support for new device like CE-ATA, and more efficient data transfer (which is normally backwardly compatible), the modules supporting these new functions can also be shared between the host and the slave device. For example, the advanced DMA supporting the descriptor chain table has been proposed in the host controller specification draft, but this DMA can also be used in slave devices which are more efficient.
The preferred embodiment of the present invention has bee descried in connection with SoC, i.e., the chip system comprising MCU, with reference to the drawings. However, those skilled in the art can appreciate that this is only for purpose of illustration but shall not be regarded as limitation to the present invention. Also, as mentioned above, in the context of the present application, terms like “SD bus interface” are used to explain the principle and exemplary implementations of the present invention for sake of simplicity, and MMC/SD/SDIO interfaces are not always mentioned. Those skilled in the art can appreciate that, this does not mean that the present invention can only apply to the interfaces compliant with SD protocol. Moreover, in the present application, concepts like “SD compatible protocol” are used to cover the MMC protocol, SD protocol, SDIO protocol, high speed MMC protocol, high speed SD protocol, high speed SDIO protocol, CE-ATA interface protocol, and future protocols compatible with these protocols.
It will be apparent to those skilled in the art that various changes and modifications can be made to the present invention without departing its spirit and scope. The protection scope of the present invention is only defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200610126706.8 | Sep 2006 | CN | national |
