Patent Application
20080155166
The present invention relates to disk drives, and in particular to an integrated circuit used to control temporary storage of data in semiconductor memory (buffer) on a disk drive.
Hard disk controllers (HDC) in disk drives typically include a buffer controller for controlling a buffer, which stores data such as user data, disk drive variables tables, code for control and/or servo processor execution and defect management information. One of the buffer controller responsibilities includes management of caching algorithms. This involves searching for a cache hit or miss for each command, and allocation of segments of the buffer for different commands or sets of commands.
In known hard disk controllers, the buffer controller, the buffer data and its management are controlled by the main control processor of the disk drive. These tasks take time away, or even prevent, the main control processor from performing its other duties. It is also known to employ a finite state machine device for controlling the buffer functions. As known in the art, a finite state machine is a model of behavior of states, transitions, and actions. State machine devices, while generally fast, lack flexibility, because they are programmed or constructed to interact with the buffer only in accordance with the state of the art knowledge and understanding of disk caching algorithms. They cannot be readily reprogrammed to adapt to changes in the caching algorithms.
The present invention relates to a buffer manager for controlling a buffer in a disk drive having a main control processor for performing functions relating to transfer of data between a host and disk media. The buffer manager includes a processor for managing caching algorithms with respect to the buffer, memory in communication with the processor for storing instructions executed by the processor in performing the caching algorithms, and a storage unit for storing data used by the processor in performing the caching algorithms.
Broadly stated, the present invention relates to an application specific processor (ASP) for controlling the buffer manager of a disk drive. In prior art disk drives, the buffer manager control is handled by the main control processor (MCP). The ASP of the present invention relieves the MCP from buffer manager controlling functions, thus allowing the MCP to focus on other functions. The ASP of the present invention can be reprogrammed to suit the changing conditions in the cache algorithms for handling data access in the buffer. This feature adds flexibility to the control of the buffer, unlike other known buffer manager controllers such as finite state machine devices which cannot be reprogrammed once implemented.
Turning now to
The disk drive 10 further includes a main control processor (MCP) 20, a buffer 22 and a memory 24. The MCP 20 is provided for overall control of the disk drive 10 including control and management of mechanical positioning of heads and rotational media (motor controls) in the HDA 16, control and setup of the read/write channel 14 and host interface, for example. The buffer 22 is preferably implemented in a DRAM or other memory devices such as FLASH or SRAM, and stores data used by the MCP 20 and the HDC 12 such as user data, disk drive variables tables, code for servo processor execution and defect management information. The memory 24 is a nonvolatile storage device such as FLASH memory or a ROM. The memory 24 stores programs and tables used in accomplishing the above-mentioned MCP 20 responsibilities, including control and setup of read channel and storing codes to be executed by the MCP.
The HDA 16, although not shown, includes one or more disks, a spindle motor for rotating the disk(s), a read/write head(s) for reading data from and writing data on the disk(s), and a head actuator for positioning the head(s) on the disk(s). The read/write channel 14 is provided for translation of digital data from the HDC 12 to a format capable of being either written to, or read from the disk(s) in the HDA 16. In a disk write operation, the read/write channel 14 sends signals to a write head and a preamp to cause magnetic transitions to be “written” to the disks. For a disk read operation, the read/write channel 14 decodes the signals from a read head and the preamp generated by passing over the magnetic or optical domains written to the disks. The transitions are detected and processed in a manner that allows them to be converted into a data format usable by the HDC 12 and the host device 18.
Referring to
The HDC 12 also includes a disk formatter 30 for transferring data from the buffer 22 (shown in
The error correcting code (ECC) circuit 32 is provided for testing the accuracy of data as it passes in and out of the disk formatter 30. Disk drive data is generally very faint in signal size, and therefore, some errors are made in retrieval of data from the disk media. Many of these errors are corrected by the use of the ECC circuit 32.
A buffer manager 34 is used to interface between the HIF 26 and the buffer 22, or between the disk formatter 30 and the buffer. The HIF 26 and the disk formatter 30 make requests of the buffer manager 34 to either accept data and write it to the buffer 22, or to retrieve data from the buffer. Other components of the HDC 12 may also have interfaces to the buffer manager 34 to be able to store and retrieve data from the buffer 22, including the ECC circuit 32. The buffer manager 34 responsibilities include management of caching algorithms, which involves searching for a cache hit or miss for each command, and allocation of segments of the buffer 22 for different commands or sets of commands.
As shown in
In accordance with one embodiment of the present invention, the buffer manager 34 also includes an ASP 44 for controlling the buffer manager 34. The ASP 40 is preferably a microprocessor and includes a central processing unit (CPU) 46 for enabling the designed functions of the ASP, primarily cache algorithms including table look up for cache hits/misses, allocation of space in the buffer 22 for each command, and updating of the cache tables 40 to reflect the allocation of buffer space. The ASP 44 further includes an instruction memory 48 that contains instructions executed by the CPU 46, and a local data/variable storage unit 50 for storing data used by the CPU 46 in performing its functions. One advantage of the present microprocessor-based buffer manager 34 is that the ASP 44 can be reprogrammed as necessary to make adjustments to the cache algorithms.
In operation, the ASP 44 enables caching algorithms, which include translation of incoming disk commands from the host device 18. For a read command, the caching algorithms include searching the cache tables 40 to determine if all, or any portion of the data is contained in the buffer 22. For a cache hit, the data is transferred as soon as practicable to the host device 18. For a cache hit that contains only a part of the requested data, or a cache miss, the MCP 20 and the servo controller 28 are informed of the need to read data from the disk(s) in the HDA 16.
For a disk write command, the ASP 44 allocates a space in the segments 42 of the buffer 22 and updates the cache tables 40. The ASP 44 then notifies the MCP 20 and the servo controller 28 of the data available to be written to the disk(s).
Referring now to
If the command from the host device 18 is a disk write, the ASP 44 searches the cache tables 40 in the buffer 22 (which contain information as to what data is in the buffer segments 42), and determines which buffer segment will be allocated to accept and store the host write command data (block 54). If there is space to accept the host write data (block 56), the registers 38 used to control the transfer of data between the host device 18 and buffer 22 or between the disk and buffer, are programmed or setup by the ASP 44 to transfer host data to the location of the buffer allocated by the cacheing algorithms (block 58). The data is then transferred to the determined buffer segments 42 (block 60). Preferably, a small state machine device (not shown) is provided to use the registers 38 to interface with the buffer 22 in transferring the data. This state machine device is specific to the buffer 22 and is transparent to the buffer manager 34.
Once the data is transferred to the buffer segments 42, the ASP 44 updates the cache tables 40 in the buffer 22 to reflect the new state of the buffer segments (block 62). The ASP 44 then notifies the MCP 20 of the completion of the data transfer (block 64).
Going back to decision block 56, if there is no space available in the buffer 22, the MCP 20 is notified of this by the ASP 44 (block 64). The MCP 20 then communicates this information to the HIF 26, and delays transmission of host write data until there is space available.
If the command from the host device 18 is a disk read (block 52), the ASP 44 searches the cache tables 40 in the buffer 22 for the data requested by the host read command (block 66).
If the cache tables 40 show that the data requested by the command is contained in the buffer 22 (a “full hit”) (block 68), a similar process described above in decision blocks 58-64 occurs. More specifically, the hardware registers 38 used to control the transfer of data between the host device 18 and buffer 22 or between the disk and buffer, are programmed by the ASP 44 (block 58), and the data is transferred from the buffer to the host device 18 (block 60). Once the data is transferred, the ASP 44 updates the cache tables 40 in the buffer 22 to reflect the new state of the buffer (block 62). The ASP 44 then notifies the MCP 20 of the completion of the data transfer (block 64).
On the other hand, if the search in the cache tables 40 (block 66) does not result in a full hit (block 68), the ASP 44 determines whether the search is a partial hit, i.e., only a part of the data requested by the host read command is contained in the buffer memory 22, or a “no hit,” i.e., no data requested by the host read command is contained in the buffer (block 70). The result of the search, i.e., a partial hit or a no hit, is communicated to the MCP 20 (block 64).
The MCP 20 receives notifications of the completion of data transfers, the need for more space, the need to retrieve data from the disk (when read search result in a no hit) or the need to retrieve the remainder of the data to satisfy the host read command (when the read search results in a partial hit). If the notification received by the MCP 20 is a partial hit, the process described in decision blocks 58-64 is repeated to transfer the partial data to the host device 18 (block 70). Otherwise, the process returns to decision block 50, where the ASP 44 again waits to receive a command.
While various embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.
Various features of the invention are set forth in the appended claims.
