Patent Application
20180083434
The present disclosure relates to apparatuses, systems, and algorithmic methods for extracting and detecting of the signatures of potential arc faults in an AFCI (Arc Fault Circuit Interrupter), and subsequently determining the presence of an arc fault condition using combination decision logic. Further, the present disclosure relates to an innovative arc fault signature processing and detection of a combination or standalone parameters of a time-domain characteristic and multi-pulse arc signatures. Further, this disclosure pertains to a periodic automatic self-testing procedure for generating such signatures, a force triggering mechanism for self or manual trip testing, and triggering solutions to provide a fast and easy mechanical trip procedure. Further, this disclosure pertains to detection of end-of-life (EOL) conditions for an AFCI apparatus, and the consequent commencement of a non-reversible EOL state.
Conventional earth current leakage circuit breakers and over-current fuses are commonly deployed to prevent injuries to people and property from dangerous conditions resulting from, for example, current leakages or severe current arcs. Although such devices detect the occurrence of some electrical faults to prevent harm to persons and property, even when such conventional devices are employed, certain electrical faults are not detected. For example, as conventional devices lack intelligent characteristic and physical fault signature identification, certain current arc occurrences might not be detected: This presents potential fire hazards.
A current arc is typically caused by a current surging over separated or poorly contacting electrical surfaces within electrical equipment, for example, in its power cord or in an electrical device itself; or within damaged electrical wiring, such as, within the walls of a building. Current arc electrical faults may be defined as current through ionized gas between the two (e.g., supply-side and load-side) separated or poorly contacting electrical surfaces. Such current arcs are often characterized by sparking and extremely high heat, and as a result can cause electrical fires. For example, electrical fires may start when the heat and/or sparking of a current arc causes insulating material or construction material in the vicinity of the electrical fault to combust. Current arc-caused electrical fires may damage property or even endanger human life.
Unfortunately, conventional circuit breakers, fuses, or Ground Fault Circuit Interrupter (GFCI) protection devices typically cannot detect—and consequently halt—current arc electrical faults, unless a current arc produces sufficient current leakage to the electrical ground to be detected by a GFCI and/or results in a sufficient current imbalance to be detected by leakage current coil circuit. Typically, an arc fault does not involve current leaking to a ground conductor or any conducting devices to the ground; it is therefore unlikely to result in a substantial current imbalance between the supply and the load.
Underwriters Laboratories (UL), an American Worldwide Safety Consulting and Certification Organization, characterizes arc faults into two fundamental types, series arc faults and parallel arc faults. Parallel arcing typically refers to arcing that occurs between two conducting wires, or between a conductor and the ground. That is, the electrical fault may be in parallel with the electrical load. The instantaneous current of a parallel arc may be limited by, for example, the impedance of the voltage source, the properties of the wiring, and the nature of surfaces where the arc occurs. When such a parallel arc occurs, a conventional circuit breaker may trip very quickly, reducing the likely of damage caused by heating of the conducting wire or fire damage at the arc occurrence point. However, there are instances where a parallel arc may destroy faulted components and thereby create a large parallel arc voltage. Under such circumstances, the arc fault current may be below the tripping point of conventional current protection devices. Thus, such a dangerous parallel arc may avoid detection, and ultimately cause an electrical fire or other dangerous situation.
Series arcing typically refers to arcing that occurs between an electrical supply and an electrical load. That is, the electrical fault may be in series with the electrical load. This may be caused by, for example, corrosion in a pin-socket or a loose connection in contacting surfaces. For example, a series arc may be initially characterized by a voltage drop of, for example, a magnitude of several hundred mV across a poorly contacting connection, which may gradually heat up, oxidize, and/or pyrolize the materials or structure surrounding the electrical fault. If the series arc fault is permitted to persist, its voltage drop may increase to a magnitude of a few volts, consequently resulting a more dramatic increase in temperature, which may cause a release of smoke from surrounding polymer insulation and/or a fire. Generally, the current of a series arc is typically limited to a moderate value by the impedance of the electrical load of the circuit. As such, the peak current of a series arc might typically never exceed the design load current of an appliance providing an electric load, making the detection of a series arc fault particularly difficult. Thus, while the amount of power generated by series arc fault is typically less than that of a parallel arc fault, the detection of series arc faults poses additional challenges.
Therefore, there is a need to be able to identify and detect potential current arc electrical faults, and subsequently interrupt the connecting circuit to prevent potential current arc fire hazards. An apparatus that addresses arc faults may be referred to as an Arc Fault Circuit Interrupter (AFCI). Despite the existence of conventional AFCIs, there remains room for improvement in the technology. In order to accurately identify, detect, and halt dangerous arc faults, there remains a need to automatically classify potential arc current patterns and cause a circuit tripping mechanism to terminate the supply of electrical current when appropriate. Additionally, there remains a need for a tripping mechanism to support ensure a proper, flexible trip operation in time desired. There further remains a need for such a tripping mechanism to provide automatic and/or manual testing functionality to ensure that the AFCI and/or other electrical protection devices work properly.
It may be desirable that a successful detection of an arc fault conduction activates a tripping mechanism to enable a tripped state, wherein an AFCI apparatus is placed in an off or non-conductive state. It may also be desirable that an AFCI apparatus may detect an end-of-life (EOL) condition and consequently engage a permanent EOL state, where an AFCI is tripped and no further reset operation is possible.
The present disclosure provides a description of apparatuses, systems, and methods to address the perceived needs and desires described above.
In one example, an AFCI is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist.
In another example, the AFCI may further include a relay module configured to trip the arc fault circuit interrupter in response to the first trigger signal, and a reset button module configured to place the tripped arc fault circuit interrupter back into an operating condition.
In yet another example, the AFCI may further include a force trigger testing mechanism configured to trip the arc fault circuit interrupter, and a test button configured to activate the force trigger testing mechanism.
In yet another example, the plurality of current arc signature detection blocks may include a time domain signature block configured to generate a time-domain signature and the plurality of corresponding current arc signatures may include the time-domain signature. The processor may be further configured to determine that the arc fault does not exist if a duty cycle of the time-domain signature is below a predetermined duty-cycle threshold.
In yet another example, the plurality of current arc signature detection blocks may include a multi-pulse detection block configured to generate a pulse signature and the plurality of corresponding current arc signatures may include the pulse signature. The processor may be further configured to determine that the arc fault does not exist if the pulse signature is not characterized by a multi-pulse phenomenon for a pulse assessment period. The pulse assessment period may extend for at least one AC period.
In yet another example, the plurality of current arc signature detection blocks may include an RMS voltage/current measurement block configured to generate a RMS current signature and the plurality of corresponding current arc signatures may include the RMS current signature. The processor may be further configured to determine that the arc fault does not exist if the RMS current signature does not exceed a predetermined RMS current amplitude threshold for an RMS assessment period. The RMS assessment period may extend for at least two AC periods.
In yet another example, the RMS voltage/current measurement block may be further configured to generate a RMS voltage signature. If the processor determines that the arc fault exists, the processor is further configured to determine that the arc fault is a parallel arc fault if the amplitude of the voltage signature is above a predetermined RMS voltage amplitude threshold and determine that the arc fault is a series arc fault if the amplitude of the voltage signature is below the predetermined RMS voltage amplitude threshold.
In yet another example, the plurality of current arc signature detection blocks may include a time domain signature block configured to generate a time-domain signature, a multi-pulse detection block configured to generate a pulse signature, and an RMS voltage/current measurement block configured to generate a RMS current signature. The plurality of corresponding current arc signatures may include time-domain signature, the pulse signature, and the RMS current signature.
In yet another example, the processor may be configured to determine that an arc fault exists if there conditions are met. These conditions are (1) that a duty cycle of the time-domain signature is below a predetermined duty-cycle threshold, (2) that the RMS current signature exceeds a predetermined RMS current amplitude threshold for an RMS assessment period; and (3) that the pulse signature is characterized by a multi-pulse phenomenon for a pulse assessment period.
In yet another example, the duty cycle of the time-domain signature may be assessed after the pulse signature is assessed.
In yet another example, the processor may be further configured to administer a self-test at start-up and cyclically on a self-test interval to determine if the arc fault circuit interrupter is in an end-of-life condition. The processor may be configured to generate the first trigger signal and a second trigger signal if the arc fault circuit interrupter is in the end-of-life condition. The self-test interval may be between 1 and 3 hours.
In yet another example, the AFCI may further include a relay module and a safety lock coil module. The relay module may be configured to trip the AFCI in response to the first trigger signal. The lock coil module may be configured to place a tripped AFCI in an end-of-life state in response to the second trigger signal.
In yet another example, the AFCI may further include a reset button module configured to place the AFCI back into an operating condition if the AFCI is tripped and not in the end-of-life state.
In yet another example, the AFCI may further include a force trigger testing mechanism and a test button. The force trigger testing mechanism may be configured to trip the arc fault circuit interrupter. The test button may be configured to activate the force trigger testing mechanism.
In yet another example, the processor may be further configured to administer a self-test to determine if the arc fault circuit interrupter is in an end-of-life condition by (1) providing an arc simulation signal to the multi-pulse detection block, (2) assessing the pulse signature corresponding the arc simulation signal, and (3) determining that the arc fault circuit interrupter is in an end-of-life condition if the pulse signature corresponding the arc simulation signal is not characterized by a multi-pulse phenomenon for a pulse assessment period. The processor may be further configured to generate the first trigger signal and a second trigger signal if the arc fault circuit interrupter is in the end-of-life condition.
In yet another example, the AFCI may further include an LED. The processor may be further configured to monitor the operating conditions on a monitoring interval to determine if there is an abnormal operating condition, and provide a signal to the LED if the abnormal operating condition is determined to exist. The monitoring interval may be between 10 and 15 minutes.
In yet another example, the AFCI may further include a leakage detection circuit configured to output a leakage detection signal to the processor. The processor may be further configured to generate the first trigger signal if the leakage detection signal is received.
In one example, a method for detecting an arc fault is provided. A plurality of current arc signatures may be received. Each of the current arc signatures may be assessed to determine whether the arc fault exists. If the arc fault is determined to exist a trigger signal may be generated.
In another example, a time-domain signature may be received. It may be determined that an arc fault does not exist if a duty cycle of the time-domain signature is below a predetermined duty-cycle threshold.
In another example, a pulse signature may be received. It may be determined that an arc fault does not exist if the pulse signature is not characterized by a multi-pulse phenomenon for a pulse assessment period.
In yet another example, an RMS current signature may be received. It may be determined that an arc fault does not exist if the RMS current signature does not exceed a predetermined RMS current amplitude threshold for an RMS assessment period.
In yet another example, an RMS voltage signature may be received. If an arc fault has been determined to exist, it may be determined that the arc fault is a parallel arc fault if the amplitude of the voltage signature is above a predetermined RMS voltage amplitude threshold and it may be determined that the arc fault is a series arc fault if the amplitude of the voltage signature is below the predetermined RMS voltage amplitude threshold.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain embodiments of the present disclosure and together with the description, serve to explain the principles of this disclosure.
Reference will now be made in detail to the present exemplary embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. While the description includes exemplary embodiments, other embodiments are possible, and changes may be made to the embodiments described without departing from the spirit and scope of the invention. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and their equivalents.
MCU 205 may, in some embodiments, accomplish the functions described herein by executing a computer program stored on a non-transitory computer readable storage medium. Such computer readable storage medium may be included within MCU 205, external to MCU 205, or partially within and partially external to MCU 205.
The arc fault detection and circuit interruption operation of exemplary AFCI circuit 200 is described below.
With reference to
First rectification bridge 217 may generate a single-sided current waveform from the LC coil, which may preferably be used in generating the time-domain signature.
A time-domain signature may be captured by time-domain signature detection block 212 by converting the single-sided current waveform into a rectangular waveform, for example by identifying the shoulder of the single-sided current waveform.
During operation, MCU 215 may calculate an average duty cycle of the rectangular waveform at point I_ZC for a predefined running window for arc signature processing, for example 4.5-5 periods of the AC power supply signal as to comply with UL specifications. Beyond a predetermined error threshold, a difference between the average duty cycle for the running window and that of a predetermined normal average duty cycle (e.g., 50%) may serve as a factor that indicates arc fault occurrence.
With reference to
When an arc fault exists, there would be an abnormal introduction of multi-pulse situation, and such multi-pulse condition would continue more than two pulse periods (corresponding to one period of the AC current) or even longer. The presence of such a prolonged multi-pulse signature, as evaluated by MCU 215, is a strong indicator of the existence of an arc fault.
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In another example, it may be determined that a series arc exists where (a) the RMS current signature exceeds a preprogrammed threshold, such as above 5 A, and (b) the time-domain signature has a duty cycle above a detection threshold, such as above 60%, for (c) a duration of at least eight half cycles.
Such preprogrammed thresholds may be determined by laboratory tests. For example, the threshold values that govern arc fault assessment may be adjustable and, in some embodiments, may be calibrated to reflect each batch of components used to assemble a particular manufacturing run of AFCI devices. For example, such batch-specific calibration may be necessary to assure that improper arc fault assessments (including false alarms) are kept to a minimum and/or to comply with various desired industrial certifications.
When appropriate, for example, when an arc fault is detected, MCU 215, may provide a signal via TRIG, as depicted in
With reference to
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As shown in
Simultaneously, or subsequently, MCU 215 may provide another trigger signal, TRIG. As shown in
As in step 101, MCU 215 may perform a self-test of AFCI circuit 200 upon power up. Primarily, this may comprise sending an arc simulation signal to MCU_SIMULATION, to assure that the pulse signal response is appropriate. If MCU 215 identifies the presence of an arc fault in response to the arc simulation signal, the self-test may be considered passed. MCU 215 may then indicate that the AFCI circuit 200 is normally operating by energizing, for example, a sold green LED indicator that is preferably visible on the face of the AFCI device. If the test is passed, the process may proceed to step 110. However, if the AFCI circuit 200 fails the internal self-test, the AFCI outlet 100 has been determined to have reached its end of life and may proceed to step 190.
As in step 190, MCU 215 delivers a triggering pulse or activation signal, e.g., TRIG1, to trigger the relay contact and trip the AFCI, as well as a second triggering pulse or activation signal, e.g., TRIG, to place the tripped AFCI in an EOL state via safety lock coil module 25, as described above with respect to
As in step 110, MCU 215 may assess the RMS current signature. If, for example, the RMS current signature is above a detection threshold, for example, 5 A, it may be determined that a series arc is possibly occurring. In some embodiments, as shown in step 111, when an above-threshold RMS current is detected in a first half cycle (of the AC current), MCU 215 may set a flag to internally indicate that monitoring of the RMS current should continue for the measurement period. Such a measurement period may be, for example, eight half-cycles. The process may proceed to step 120. If however, the RMS current signature is not above a detection threshold, it may be determined that no arc condition is occurring, and the process may proceed to step 160.
As in step 120, MCU 215 may assess the pulse signature. If, for example, there is a multi-pulse signature for more than one AC period, it may be determined that an arc is likely occurring. If so, the process may proceed to step 130. If however, the pulse signature is not a multi-pulse signature for more than one period, it may be determined that no arc condition is occurring, and the process may proceed to step 160.
As in step 130, MCU 215 may assess the time-domain signature. If, for example, the time-domain signature provides a duty cycle above a detection threshold, for example, 60%, it may be determined that an arc is occurring. However, at this step, MCU 215 may also cross-reference the time-domain signature with pre-supplied values that maybe indicative of electrical phenomena other than arcing, such as, switching a power supply, or using a dimmer switch. If the time-domain signature is determined to be indicative of an arc occurrence, the process may proceed to step 140. If not, the process may proceed to step 160.
As in step 140, MCU 215 may assess the RMS current signatures over multiple half-cycles, comparing them with threshold values to confirm that the RMS current signature is indicative of an arc occurrence. For example, a high RMS current signature could indicate an inrush of current resulting from electrical equipment being plugged into the AFCI or the like. In such a case—but not in the case of an arc—the RMS current signature will decrease over successive half cycles. Thus, in preferred embodiments, MCU 215 may confirm the presence of an arc where an above-threshold RMS current signature is found on the second or third period of AC current since the flag was set. If the RMS current signatures are confirmed to indicate of an arc, the process may proceed to step 180. If not, the process may proceed to step 160.
As in step 160, MCU 215 may monitor for a leakage current signal. If there is a leakage current signal, then MCU 215 may energize the alert red LED indicator and send a trigger signal, e.g., TRIG1, to trip the AFCI device, as in step 180. In the absence of a leakage current signal, the process proceeds to step 170.
As in step 170, MCU 215 may determine whether it is time to monitor operating characteristics of the AFCI device. In preferred embodiments, such monitoring may occur on a 10-15 minute interval. The monitoring interval may be programmed into MCU 215. If it is time for monitoring, the process proceeds to step 171; otherwise the process proceeds to step 171.
As in step 171, MCU 215 may monitor various operating conditions of the AFCI device, such as input voltage and input current, as well as other pre-defined operating criteria or environmental conditions. In the event of an abnormal operating condition detected during the monitoring process, MCU 215 may indicate such abnormality by, e.g., blinking the alert red LED indicator. This may, in turn, inform a user of the presence of an abnormal operating condition, and, if the blinking persists, that it may be advisable to investigate and repair or replace, e.g., the wiring, power supply, or even the AFCI outlet 100 itself. The process may proceed to step 175.
As in step 175, MCU 215 may determine whether it is time for an automatic, periodic self-test. In preferred embodiments, a periodic self-test will occur on a 2.5 hour interval, or may be between 1 and 3 hours. The self-test interval may be programmed into MCU 215. It may follow UL or other industrial specifications or regulatory requirements. If it is time for a self-test, the process proceeds back to step 101. If not, the process cycles back to continue at step 110.
As in step 180, upon a determination that there is a leakage current or arc fault, MCU 215 delivers a triggering pulse or activation signal, e.g., TRIG1, to trigger the relay contact. As described below, with reference to
In some embodiments, AFCI 100 may additional fail-safes to prevent AFCI 100 from providing if power operation if MCU 215 suffers a malfunction. Because the arc fault detection and self-testing described herein may only be reliable with a properly functioning MCU 215, it may be advantageous for AFCI 100 to detect an MCU 215 malfunction, cease providing power, and/or notify a user of the malfunction. To accomplish this, AFCI 100 may further include a simple failsafe circuit that would, as a default, maintain the AFCI in a tripped state and/or provide a continuous alert signal.
In the preceding specification, various preferred embodiments have been described with reference to the accompanying drawings. It will, however, be evident that various other modifications and changes may be made thereto, and additional embodiments may also be implemented, without departing from the broader scope of the invention as set forth in the claims that follow.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.
