Architecture for processing fingerprint images

Abstract

Embodiments of an architecture for processing gray-level images is disclosed.

Description

BACKGROUND

[0002] This disclosure is related to classification and feature extraction.

[0003] Feature extraction is a current area of research and development in digital image processing and computer vision, particularly in areas of development involving feature based pattern recognition. Many image recognition, image detection, and biometrics applications, for example, have been developed based on techniques of feature extraction and pattern recognition. Feature extraction in fingerprint images has unique aspects compared to general purpose image processing applications at least in part due to its special topological characteristics. Most of the approaches proposed in the literature transform a fingerprint image into a binary image based at least in part on convolution of the image with a filter coupled with certain variants of thresholding. However, this approach has several disadvantages, such as computational intensity and the inability to robustly address noisy images. Moreover, most of the methods in the literature are slow, complicated, and difficult to implement in hardware. A need, therefore, exists for other processing techniques and architectures to support such techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. The claimed subject matter, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference of the following detailed description when read with the accompanying drawings in which:

[0005] FIG. 1 is a schematic diagram showing an portion of an embodiment of a processing element (PE) that may be used to classify a pixel;

[0006] FIG. 2 is a schematic diagram showing additional portions of the embodiment of a processing element of FIG. 1;

[0007] FIG. 3 is a schematic diagram showing another portion of the embodiment of FIG. 1 in more detail; and

[0008] FIG. 4 is a schematic diagram showing a particular embodiment which combines several PE embodiments of FIG. 1, the PE embodiments combined in this particular embodiment to process a 4×5 image.

DETAILED DESCRIPTION

[0009] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail in order so as not to obscure the claimed subject matter.

[0010] The claimed subject matter relates to implementing an on-chip VLSI implementation of pixel classification using the topological features. In one embodiment, features such as crest, valley, plateau and undecided, as disclosed in previously referenced U.S. patent application Ser. No. ______ (attorney docket 042390.P12797), are employed, although, of course, the claimed subject matter is not limited in scope to employing the approach disclosed therein. Any one of a number of approaches to pixel classification are capable of being implemented that fall within the scope of the claimed subject matter.

[0011] Nonetheless, in the aforementioned approach, a first pass over a image-pixel matrix resolves pixels to seven classes, namely CR, VA, PL, CV, VP, CP and UN, as described in the aforementioned application. Of the seven classes, CR (crest), VA (valley), PL (plateau) are final classes in a described embodiment of the aforementioned application.

[0012] For this particular embodiment of an architecture for processing images, a processing element 10 (PE) to classify a pixel, such as into the above seven classes, is shown in FIG. 1. An image-pixel matrix of ‘m’ rows and ‘n’ columns may, for example, employ in this embodiment ‘m’ copies of the PE, although the claimed subject matter is not limited in scope in this respect. In this embodiment, the pixels in several columns are ‘fired’ during a clock pulse. Thus, in this embodiment, columns are fed in a pipeline fashion into the PEs.

[0013] Consider, for example, a pixel at the (i, j)th location. Processing element PEi, in this embodiment, has three (3) input lines Ri−1, Ri and Ri+1, corresponding to rows i−1, i and i+1. To classify a pixel at (i, j), employing the approach previously described, pixels in its 3×3 neighborhood are accessed. The pixels at location having indices i−1, i and i+1 may be obtained from input lines Ri−1, Ri and Ri+1 respectively. Also note that pixels at locations having the same ‘j’ indices are fired during the same clock, e.g., (i−1, j), (i, j) and (i+1, j) are fired during the same clock pulse or instant, say, for example, tj; then (i−1, j−1), (i, j−1) and (i+1, j−1) are fired during time or pulse tj−1 and (i−1, j+1), (i, j+1) and (i+1, j+1) would be fired during time or pulse tj+1.

[0014] The following table shows the pixels employed to calculate a, b, c, d, e, f, g and h, which are employed to classify a particular pixel into one of the seven classes of the aforementioned patent application, as well as the clock pulse at which it would be available.

	TABLE 1
			Time at			Time at
			which		Input Line	which
		Input line at	it is		at which	it is
	Pixels	which it is	avail-	Pixels	it is	avail-
	Needed	available	able	Needed	available	able
a	i, j	Ri	tj	i − 1, j	Ri−1	tj
b	i, j	Ri	tj	i + 1, j	Ri+1	tj
c	i, j	Ri	tj	i − 1, j − 1	Ri−1	tj − 1
d	i, j	Ri	tj	i + 1, j + 1	Ri+1	tj + 1
e	i, j	Ri	tj	i, j − 1	Ri	tj − 1
f	i, j	Ri	tj	i, j + 1	Ri	tj + 1
g	i, j	Ri	tj	i + 1, j − 1	Ri+1	tj − 1
h	i, j	Ri	tj	i − 1, j + 1	Ri−1	tj − 1

[0015] For example, as shown, a, b may be evaluated at the tjth clock pulse. To calculate c, e and g at the tjth clock pulse, the data at input lines Ri, Ri−1, and Ri+1 at (tj−1)th clock pulse and Ri at tjth clock pulse is employed. To accomplish this, data at input line may be delayed for one clock. D flip-flops 20, D1, D2, and D3, as shown in FIG. 1, accomplishes this for this embodiment. For calculating h, d and f, the data at input lines Ri, Ri−1 and Ri+1 are employed on the tj+1th clock pulse and Ri at tjth clock pulse. Therefore, D flip-flop D2 holds back the data at input line Ri in this embodiment.

[0016] The comparator block 30, Ci, has five(5) 8-bit magnitude comparators, for a, b, c, e and g, in this embodiment. At the clock pulse tj, Ci calculates a, b, c, e and g for the pixel at location (i, j) of the image pixel matrix. Comparator block 40, Ci+1, has three(3) 8-bit magnitude comparators, for d, h and f, in this embodiment. Ci+1 calculates d, h and f for the pixel at location (i, j) at the (tj+1)th clock pulse. Note that at clock pulse (tj+1), Ci calculates a, b, c, e and g corresponding to the pixel at location (i, j+1) of the pixel-matrix; Ci+1 calculates d, h and f corresponding to the pixel at location (i, j−1) at the clock pulse tj.

[0017] In this particular embodiment h, d and f are available one clock pulse after the availability of a, b, c, e and g. Therefore, a, b, c, e and g are delayed for a clock pulse, here by a bank 50 of D flip-flops, D4. Likewise, in this embodiment a bus-width of three binary signal values is employed for a, b, c, d, e, f, g and h. Specifically, the output signals of the magnitude comparators in this embodiment includes ‘+’, ‘−’ or ‘0’. Of course, in this embodiment, one line of the comparator circuit goes high.

[0018] The output signals for a, b, c, d, e, f, g and h are then fed into four(4) combinational circuits 60, P1, P2, P3 and P4 in this embodiment. These circuits combine c with d, a with b, g with h, and e with f, respectively. The combinational circuits P1 to P4 shown in FIG. 3 in more detail, for this particular embodiment, implement a table shown in FIG. 3 of the aforementioned patent application ______, attorney docket 042390.P12797), although, again, the claimed subject matter is not limited in scope in this respect. In this embodiment, along any of the directions (a, b), (c, d), (e, f) or (g, h), a crest, valley, plateau, or undecided classification may result. So, out of the four (4) output lines, a line being 1-bit wide in this embodiment, one line may go high indicating the presence of a crest, valley, plateau or an undecided classification.

[0019] This embodiment also employs four (4) adders, 70. The CR, VA, PL and UN 1-bit output lines here, as shown in FIG. 1, are fed respectively to Crest-adder, Valley-adder, Plateau-adder and Undecided-adder (also indicated hereinafter as AdderC, AdderV, AdderP, and AdderU). With four (4) directions, three(3) bits are employed in this embodiment to represent the sum of the adders to capture the situation where the same classification occurs for each direction. The output signals from the adders are fed into a Look-up Table(LUT1) 90 implementing the classification scheme depicted by the table in FIG. 4 in aforementioned application ______ (attorney docket 042390.P12797). This may, of course, be implemented any one of a number of ways, including using combinational circuitry. The claimed subject matter is not limited in scope to a particular implementation technique.

[0020] Circuit block 80, CK1, as shown in FIGS. 1 and 2, has seven (7) output lines CR, VA, PL, CV, VP, CP and UN. According to the Look-up Table or combinational circuit implementation of the classification scheme one of the seven lines goes high.

[0021] This embodiment also includes the capability to calculate the average gray-value of the crest, valley and plateau pixels to classify CV, VP, CP and UN types of pixels in a second pass, as illustrated in FIG. 2. As any one of the seven (7) output lines from the circuit block CK1 goes high, output lines CR, VA or PL are used to enable adders AdderC, AdderV and AdderP, respectively. The input lines, Ri's, are fed into adders AdderC, AdderV and AdderP. Based on the enable signal to the adders, one of the adders, such as AdderC, AdderV and AdderP, is selected and the addition is done. The counters, such as CounterC, CounterV and CounterP, count the number of enable signals to the respective adders, thereby, giving the number of crests, valleys and plateau pixels present in the image-pixel matrix. Thus, AdderC and CounterC, for example, has the sum of the gray level values of the crest pixels in that particular row and the number of such crests in that row, respectively.

[0022] In this embodiment, after the entire image pixel matrix has been ‘fired,’ the values from the AdderCs are added and the values from the CounterCs are added. The sum from the adders is divided by the sum of the values of the counters to get the average crest gray level value. A similar operation may be performed for valley and plateau pixels.

[0023] After the first pass, the m x n pixels present in the image pixel matrix are classified into seven classes. These pixels may be stored in a temporary storage for further processing in the second pass. Look-up Table (LUT2) 120 is used to decode the seven(7) output lines to a pre-specified value, as set in the LUT2, to reflect the classifications the pixels may acquire.

[0024] Thus, this embodiment may be employed to implement a VLSI architecture for computation of topological features for gray-level images. For example, FIG. 4 illustrates an embodiment for processing a 4×5 image using several of the PE embodiments previously described. These topological features may be used to extract a binary image from a gray-scale image. For example, as described in aforementioned patent application ______ (attorney docket 042390.P12797), this binary image may then be used for fingerprint analysis, as described, for example, in aforementioned patent application ______ (attorney docket 042390.P12798), although, again, this is just one example and the claimed subject matter is not limited in scope to employing the approaches in either of these applications. Furthermore, such an embodiment may be applied to other situations as well, such as to perform edge detection of general image processing applications, such as may be incorporated in Computer Vision, Pattern Recognition and other image processing architectures.

[0025] It will, of course, be understood that, although particular embodiments have just been described, the claimed subject matter is not limited in scope to a particular embodiment or implementation. For example, one embodiment may be in hardware, whereas another embodiment may be in software. Likewise, an embodiment may be in firmware, or any combination of hardware, software, or firmware, for example. Likewise, although the claimed subject matter is not limited in scope in this respect, one embodiment may comprise an article, such as a storage medium. Such a storage medium, such as, for example, a CD-ROM, or a disk, may have stored thereon instructions, which when executed by a system, such as a computer system or platform, or an imaging or fingerprint image system, for example, may result in an embodiment of a method in accordance with the claimed subject matter being executed, such as an embodiment of a method of providing a binary fingerprint image, for example, as previously to described. For example, an image processing platform or an image processing system may include an image processing unit, an image input/output device and/or memory.

[0026] While certain features of the claimed subject matter have been illustrated and described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the claimed subject matter.

Claims

1. An apparatus comprising: a processing unit; said processing unit having the capability to evaluate a gradient of the gray-level in a neighborhood of pixels immediately surrounding a pixel.

2. The apparatus of claim 8, wherein said processing unit includes three input lines.

3. The apparatus of claim 9, wherein said processing unit includes the capability to delay the gray-level values of selected pixels in the neighborhood to compute the gradient of the gray-level.

4. The apparatus of claim 8, wherein the neighborhood comprises a three-by-three neighborhood.

5. The apparatus of claim 1, wherein said processing unit includes the capability to classify the surrounded pixel based, at least in part, on the gradients of the gray-level in the immediately surrounding neighborhood.

6. The apparatus of claim 5, wherein said processing unit includes the capability to classify the surrounded pixel into one of a limited number of classifications based, at least in part, on the gradients of the gray-level in the immediately surrounding neighborhood.

7. The apparatus of claim 6, wherein the limited number of classifications comprise: crest, valley, plateau, and undecided.

8. The apparatus of claim 7, wherein said processing unit further includes the capability to further classify any undecided pixels as crest, valley, or plateau based, at least in part, on the pixels in the immediately surrounding neighborhood not classified as undecided.

9. The apparatus of claim 1, wherein a plurality of m processing units are coupled together to process an image having m rows and n columns.

10. The apparatus of claim 9, wherein the plurality of m processing units are integrated on an integrated circuit chip.

11. The apparatus of claim 10, wherein the integrated circuit chip is incorporated in an image processing system.

12. An apparatus comprising: a plurality of input lines to apply gray-level pixel signal values to a configuration of comparators and digital delay latches, said comparators and digital delay latches being coupled so as to compute in operation whether the gradient of the gray-levels in a neighborhood immediately surrounding a selected pixel is positive, negative or substantially zero.

13. The apparatus of claim 12, wherein the plurality of input lines comprises three lines.

14. The apparatus of claim 13, wherein the digital delay latches comprise flip-flops.

15. The apparatus of claim 12, wherein said configuration includes three digital delay latches.

16. The apparatus of claim 12, wherein said configuration includes two comparator blocks, each block having multiple comparators.

17. The apparatus of claim 16, wherein one of said blocks comprises three comparators and another of said blocks comprises five comparators.

18. The apparatus of claim 12, wherein said input lines are coupled to said configuration so as to apply pixel signal values in the same column and immediately adjacent rows to said configuration at substantially the same time.