Claims
- 1. An apparatus comprising:a plurality of input lines to apply gray-level pixel signal values to a configuration of comparators and digital delay latches, said comparators and digital delay latches being coupled so as to compute in operation whether the gradient of the gray-levels in a neighborhood immediately surrounding a selected pixel is positive, negative or substantially zero, wherein said configuration includes two comparator blocks, each block having multiple comparators.
- 2. The apparatus of claim 1, wherein the plurality of input lines comprises three lines.
- 3. The apparatus of claim 2, wherein the digital delay latches comprise flip-flops.
- 4. The apparatus of claim 1, wherein said configuration includes three digital delay latches.
- 5. The apparatus of claim 1, wherein one of said blocks comprises three comparators and another of said blocks comprises five comparators.
- 6. An apparatus, comprising:a plurality of input lines to apply gray-level pixel signal values to a configuration of comparators and digital delay latches, said comparators and digital delay latches being coupled so as to compute in operation whether the gradient of the gray-levels in a neighborhood immediately surrounding a selected pixel is positive, negative or substantially zero, wherein said input lines are coupled to said configuration so as to apply pixel signal values in the same column and immediately adjacent rows to said configuration at substantially the same time.
- 7. The apparatus of claim 6, wherein the plurality of input lines comprises three lines.
- 8. The apparatus of claim 6, wherein the digital delay latches comprise flip-flops.
- 9. The apparatus of claim 6, wherein said configuration includes three digital delay latches.
- 10. The apparatus of claim 6, wherein said configuration includes two comparator blocks, each block having multiple comparators.
- 11. The apparatus of claim 10, wherein one of said blocks comprises three comparators and another of said blocks comprises five comparators.
RELATED APPLICATIONS
This patent application is related to concurrently filed U.S. patent application Ser. No. 09/952,248, titled “Method and Apparatus to Provide a Binary Fingerprint Image,” filed Sep. 13, 2001, by Acharya et al., and to concurrently filed U.S. patent application Ser. No. 09/952,249, titled “Method and Apparatus to Reduce False Minutiae from a Binary Fingerprint Image,” filed on Sep. 13, 2001, by Acharya et al., both assigned to the assignee of the presently claimed subject matter and herein incorporated by reference.
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