Area Efficient, Programmable-Gain Amplifier

Abstract

A reconfigurable network arrangement of resistors and switches is constructed so that it can be coupled to one or more operational amplifiers and selectively programmed so as to set the gain of the resulting amplifier. The configuration of the network arrangement of resistors and switches to include resistors that can be connected in the feedback path in series and in parallel with each other is such as to provide a wider selection of gain settings, without the need to increase the physical area of the switches on a integrated circuit arrangement.

Description

FIELD

The following disclosure relates generally to an area-efficient gain programming network for amplifiers and to a programmable-gain amplifier that can be provided by combining the network with an amplifier, and more specifically to a low-noise, low distortion programmable-gain amplifier with gain settings that can be varied in arbitrarily-chosen discrete steps, and that can be implemented using a relatively small number of electronic switch elements in an integrated circuit.

BACKGROUND

One prior art implementation of a low-distortion, programmable-gain amplifier is shown in FIG. 1. An input signal, which may be AC or DC, is applied to Vin. The output signal appears at V_OUT. In this illustrated arrangement the high-gain operational amplifier A₁ is configured as a non-inverting amplifier. This configuration is preferred for low-noise applications over the inverting configuration since the feedback network can be made low impedance to minimize its thermal noise contribution without compromising the amplifier input impedance, which may be set independently via resistor R_IN. The feedback network around operational amplifier A₁ is tapped at multiple points by electronic switch elements S₁ through S_N. Each switching element is typically constructed to include complementary metal-oxide semiconductor (CMOS) devices and can be independently turned on or off depending on the desired gain. Control signals (C₁ through C_N) provided at a control input are used to select the desired gain by turning on the appropriate switch S₁ through S_N corresponding to the desired gain. Such an approach has the benefit that the variations in on-resistance of electronic switches S₁ through S_N due to changes in input voltage do not affect the linearity of the output signal since no signal current flows through these switches. This minimizes distortion, so long as one and only one of electronic switches S₁ through S_N is turned on at any one moment of time.

However, the on-resistance of each of these switches does contribute thermal noise to the total input noise of the amplifier. One way to decrease the on-resistance of CMOS electronic switches (and thus to reduce the amplifier's input noise) is to increase the physical area of the CMOS devices which make up the switches. In an integrated circuit, however, an increase in the area of a switch results in an increased die area. Since the approach illustrated in FIG. 1 requires one switch for each desired gain setting, and since each switch requires at least some die area, the necessary area can be a significant issue.

SUMMARY

In accordance with one aspect of the invention, a reconfigurable network arrangement is provided for use with at least one operational amplifier. The reconfigurable network arrangement comprises a plurality of resistors and a plurality switches constructed so that the resistors can be coupled to one or more operational amplifiers and selectively programmed so as to form a feedback path so as to selectively set the gain of the amplifier, the plurality of resistors and plurality of switches being arranged so that the resistors can be selectively connected in the feedback path in series and in parallel with each other so as to provide a selection of gain settings, while using fewer switches than would be required for the same number of gain settings in an all-series arrangement.

In accordance with another aspect, a reconfigurable network for use with at least one operational amplifier is provided. The reconfigurable network comprises: a feedback path arrangement configured to be connected to the operational amplifier so as to provide a reconfigurable feedback path between an input and an output of the operational amplifier so that the gain of the operational amplifier can be programmed at any one of a plurality of gain settings. The feedback path arrangement comprises: a first plurality of resistors connected in series so as to provide a resistor string; a first plurality of switches constructed and arranged so as to selectively connect one or more junctions between resistors of the first plurality to one of the operational amplifier's input terminals; a second plurality of resistors; and a second plurality of switches constructed and arranged so as to selectively connect each of the second plurality of resistors into the feedback path in parallel with one another; wherein the reconfigurable feedback path is configured to be coupled to the operational amplifier as a function of the one or more resistors of the first and second plurality connected in the feedback path wherein the reconfigurable feedback path connected to the operational amplifier is a function of the one or more resistors of the first and second plurality connected in the feedback path.

In accordance with yet another aspect, an amplifier circuit comprises: at least one operational amplifier; and a reconfigurable network arrangement for use with the operational amplifier, the reconfigurable network arrangement including: a plurality of resistors and a plurality switches constructed so that the resistors can be coupled to one or more operational amplifiers and selectively programmed so as to form a feedback path so as to selectively set the gain of the amplifier, the plurality of resistors and plurality of switches being arranged so that the resistors can be selectively connected in the feedback path in series and in parallel with each other so as to provide a selection of gain settings.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is made to the attached drawings, wherein elements having the same reference character designations represent like elements throughout, and wherein:

FIG. 1 is a partial schematic, partial block diagram of a prior art programmable gain amplifier using a reconfigurable network arrangement;

FIG. 2 is a partial schematic, partial block diagram of one embodiment of a programmable gain amplifier with one configuration of the employing the teachings described herein;

FIG. 3 is a partial schematic, partial block diagram of an example of a simplified version of the programmable gain amplifier shown in FIG. 2 for illustrative purposes; and

FIG. 4 is a partial schematic, partial block diagram of an example of an instrumentation amplifier employing the teachings described herein.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 2 is a schematic representation of one embodiment of the reconfigurable network arrangement connected to provide a programmable gain for an operational amplifier A₁. High-gain operational amplifier A₁ is configured as a non-inverting amplifier and arranged for single ended operation. Input voltage V_IN is applied to the non-inverting input of non-inverting amplifier A₁. The network arrangement includes a plurality of separately operable switches, all arranged so that when selectively turned on, the switches define the voltage division ratio in the feedback path of the operational amplifier A₁ between its output and inverting input. The switches are individually and selectively operable so that the gain can be set as a function of which of the resistors RF1˜RFM are included in the feedback path and by which point on the string of R1˜RN+1 is selected, which in turn is determined by which of the switches are closed. Resistor R_IN substantially sets the amplifier input impedance. A first set of resistors R₁ through R_N+1 are each connected in series with each other, between the output of the operational amplifier and system ground (or a reference node). Each node between adjacent resistors is connected through a corresponding switch S_C1 through S_CN to the inverting input. The resistors R₁ through R_N+1 therefore comprise a tapped resistor string that provides feedback via a series of resistances defined by R₁ to R_N+1. Thus, closing switch S_C1 to the on state results in a voltage division ratio in the feedback path equal to (R2+R3+ . . . Rn+Rn+1)/(R1+R2+R3+ . . . Rn+Rn+1). Closing switch S_C2 to the on-state results in a voltage division ratio in the feedback path equal to (R3+ . . . Rn+Rn+1)/(R1+R2+R3+ . . . Rn+Rn+1) and so forth. Thus, discrete voltage dividers can be selected by selectively closing one of the electronic switches S₁ through S_N while leaving the others switches in that series open. Control signals C_C1 through C_CN respectively control the opening and closing of the corresponding switches S₁ through S_N so that the control signal are used to select a series of individual closed-loop gain settings by turning on individual electronic switches S₁ through S_N, and connecting a single point along the tapped resistor string to non-inverting amplifier A₁'s inverting input. Of course, without departing from the spirit of the invention, the control signals C_C1 through C_CN may be arranged, as more fully described in Co-pending Application, to allow slow transitions from one state to another, during which transitions more than one tap on the voltage divider may be connected simultaneously to the non-inverting amplifier A₁'s inverting input. The control signals can also be provided by a controller suitably configured to provide the appropriate control settings as a function of the application.

The network arrangement of resistors is also configured so that additional resistors R_F1 through R_FM may each be connected in parallel with resistor R₁ in the feedback arrangement regardless of which of the switches S_C1 through S_CN is closed. Resistors R_F1-R_FM are connected in series with the corresponding switches S_F1 through S_FM and parallel to the resistor R₁. By closing one or more of the switches S_F1 through S_FM, one or more of the resistors R_F1 through R_FM are connected in parallel to the resistor R₁, thereby modifying the closed-loop gain when they are connected in parallel with resistor R₁. Control signals C_F1 through C_FM determine the state of switches S_F1 through S_FM respectively, selectively turning them on so as to connect none, some, or all of those resistors R_F1 through R_FM (for which the corresponding switches S_F have been turned on) in parallel with resistor R₁.

The control signals can be generated automatically, as for example in response to a control circuit, or manually, as for example a user defined input.

To examine the operation of the programmable-gain amplifier in more detail, it is helpful to define the sum of the resistances of resistors R₂ through R_N+1 as R_STRING. It is further useful to define a variable k denoting the fraction of the total resistance R_STRING that is connected between the inverting input of A₁ and ground (or a reference node) when a single one of electronic switches S₁ through S_N is turned on. Thus, there will be (1−k)*R_STRING connected between R₁ and the inverting input of A₁, and k*R_STRING connected between the inverting input of A₁ and the reference node or ground. Finally, it useful to define a resistance R_P equal to the parallel combination of R₁ and any resistors (R_F1 through R_FM) connected in parallel with it those electronic switches S_F1 through S_FM that are turned on. For example, if switches S_F1 and S_F2 are turned on, then R_P=R₁∥R_F1∥R_F2.

FIG. 3 illustrates an example of the circuit configuration of FIG. 2 at a single gain setting using the definitions above. Utilizing these definitions, for any one of electronic switches S_C1 through S_CN being on, and any combination of switches S_F1 through S_FM being on, and assuming that the open-loop gain of A₁ is much greater than the desired closed-loop gain, the closed loop gain, A_CL, of operational amplifier A₁ can be expressed to be:

$\begin{array}{cc}\begin{array}{c}{A}_{\mathrm{CL}}=\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}\\ =1+\frac{R_P+\left(1-k\right)R_{\mathrm{STRING}}}{{\mathrm{kR}}_{\mathrm{STRING}}}\\ =\frac{{\mathrm{kR}}_{\mathrm{STRING}}+\left(1-k\right)R_{\mathrm{STRING}}+R_P}{{\mathrm{kR}}_{\mathrm{STRING}}}\end{array}\mathrm{and}& \left(1\right)\\ A_{\mathrm{CL}}=\frac{R_{\mathrm{STRING}}+R_P}{{\mathrm{kR}}_{\mathrm{STRING}}}=\left(\frac{1}{k}\right)\left(\frac{R_{\mathrm{STRING}}+R_P}{R_{\mathrm{STRING}}}\right).& \left(2\right)\end{array}$

It should be noted that there are two independent factors controlling the closed-loop gain of operational amplifier A₁. The first, 1/k, is a function of which of electronic switches S_C1 through S_CN are turned on. The second term, (R_STRING+R_P)/R_STRING, is a function of which of electronic switches S_F1 through S_FM are turned on. There are N possible values available for the variable k, corresponding to the N electronic switches S_C1 through S_CN being turned on one at a time. There are 2^M possible values of R_P corresponding to the various combinations of switches S_F1 through S_FM being turned on. However, not all of these possible combinations are independent of one another. Since one of the advantages of the disclosed arrangement is to allow a set of arbitrarily-chosen gain settings to be implemented, the choices of values for R_P is ideally limited to independent combinations, thus reducing the possible number of values of R_P to M+1. Thus, the circuit in FIG. 2 allows N*(M+1) independent gain settings while requiring N+M switches. This is in contrast to the prior art circuit in FIG. 1, which allows only N gain settings with N switches.

It is clear that the arrangement in FIG. 2 requires fewer switches for a given number of gain settings than the circuit of FIG. 1. However, since signal current flows in electronic switches S_F1 through S_FM, (unlike switches S_C1 through S_CN) they are potential sources of distortion due to variation in on-resistance with signal voltage. This distortion can be mitigated with the appropriate choices of the combination of switches S_F1 through S_FM used to implement the gain settings. In particular, the values of R_F1 through R_FM are chosen such that the desired gain settings are achieved by successively turning on an additional switch for the next lower gain setting out of the M+1 range of settings. In this case, for a given setting of the gain switches S_C1 through S_CN, the highest gain setting is with all of the switches S_F1 through S_FM off, and the resulting value of R_P is equal to R₁. The next lowest gain setting is with one of the switches, S_F1, on, and the resulting value of R_P is equal to R₁∥R_F1. The next lowest setting is with two of the switches, S_F1 and S_F2, on, and the resulting value of R_P is equal to R₁∥R_F1∥R_F2. This pattern is continued such that the lowest gain setting possible for a given setting of switches S_C1 through S_CN is with all of the switches S_F1 through S_FM turned on. Such an approach results in a sharing of signal currents between the multiple switches that are turned on, minimizing the distortion contribution of any one. In an example of one embodiment, R_P is designed to vary over a range of approximately 2.5 to 1, and none of the resistors R_F1 through R_FM are less than ten times the value of resistor R1. This ensures that none of the switches S_F1 through S_FM conducts more than one tenth of the signal current conducted by R₁. The distortion contribution of switches S_F1 through S_FM can also be minimized by appropriate modulation of the control signals C_F1 through C_FM, as described in a Co-pending Application.

In one implementation, resistors R_F1 through R_FM are chosen to implement a 1 dB decrease (a factor of 0.8913) in closed loop gain as each one is turned on. Resistors R₁ through R_N+1 are chosen so that each tap along the string of these resistors implements an 8 dB change in gain, such that the variable k changes by a factor 2.512 at each tap along the resistor string R_STRING formed by resistors R₁ through R_N+1. In such an exemplary implementation, 7 resistors (R_F1 through R_F7) are required to implement eight 1 dB steps, and the value of R_P will vary over an 8 dB range from R₁ to R₁/2.512.

Operational amplifier A₁ may be of a voltage-feedback type or a current-feedback type. For programmable-gain amplifiers in which the gain varies over a wide range, the current-feedback type is advantageous because the closed-loop bandwidth can be made to be substantially independent of the closed-loop gain, in contrast to the voltage-feedback type, where the closed-loop bandwidth is typically inversely proportional to the closed-loop gain. However, as is well-known in the art, the closed loop bandwidth of a current-feedback operational amplifier is inversely proportional to the value of the resistance between the amplifier output and its inverting input. Further, a given amplifier will typically require a minimum value of resistance between these terminals in order to maintain stability. Accordingly, when using a current-feedback operational amplifier, the minimum value of the resistance between the amplifier output and inverting input, equal to R₁ in parallel with all of the resistors R_F1 through R_FM, is an important aspect of the design. If one defines this resistance as R_PMIN, one may express the minimum gain of the programmable-gain amplifier, when k=1 (with switch S_F1 on) and R_P=R_PMIN, as:

$\begin{array}{cc}{A}_{\mathrm{CLMIN}}=\frac{R_{\mathrm{STRING}}+R_{\mathrm{PMIN}}}{R_{\mathrm{STRING}}}& \left(3\right)\end{array}$

Therefore, choosing the minimum desired gain and the value of R_PMIN will determine the resistance of R_STRING (the sum of resistors R₂ through R_N+1), since:

$\begin{array}{cc}{R}_{\mathrm{STRING}}=\frac{R_{\mathrm{PMIN}}}{A_{\mathrm{CLMIN}}-1}& \left(4\right)\end{array}$

Since, for any desired closed-loop gain setting, the value of R_P is:

R _P =R _STRING(kA_CL−1)  (5)

one may then find the remaining M values of R_P. From these M+1 values of R_P, it is straightforward to calculate the M resistor values R_F1 through R_FM. The highest value for R_P will equal R₁. The next highest value, defined here as R_P1, will be made up of R₁ in parallel with R_F1, so R_F1 must be:

$\begin{array}{cc}{R}_{F1}=\frac{R_{P1}*R_1}{R_1-R_{P1}}& \left(6\right)\end{array}$

The values for resistors R_F2 through R_FM may be calculated in a similar fashion.

With the values of resistors R1 and R_F1 through R_FM defined, the values for k may be calculated. For the highest gain setting for each value of k (with S_F1 through S_FM off), k may be calculated as:

$\begin{array}{cc}k=\frac{R_{\mathrm{STRING}}+R_1}{A_{\mathrm{CL}}*R_{\mathrm{STRING}}}& \left(7\right)\end{array}$

From the individual values of k for each coarse gain setting, the values of R₂ through R_N+1 may be calculated. For example, defining the value of k when switch S_C2 is on as k₂, we can calculate the value of resistor R₂ as:

R ₂=(1−k₂)R_STRING·  (8)

Similarly, defining the value of k when switch S_C3 is on as k₃, the value of resistor R₃ will be:

R ₃ =R ₂−(1−k₃)R_STRING  (9)

The remaining values for resistors R₄ through R_N may be calculated in a similar fashion, while the value of resistor R_N+1 will be the difference between R_STRING and the sum of resistors R₁ through R_N.

While the FIGS. 2 and 3 embodiment is shown as a reconfigurable network arrangement connected to a high-gain operational amplifier configured as a non-inverting amplifier, the teachings disclosed herein can be applied to a high-gain operational amplifier configured as an inverting amplifier. Furthermore, it is possible to deviate from the reconfigurable network arrangement of FIGS. 2 and 3 by moving the resistor network represented by Rp to a position between the reference node and the resistor kR_STRINGm. Further, while the amplifier is described as a single ended configuration, the operation amplifier can be as arranged in a differential mode. For example, as a further embodiment, one can extend the gain setting approach described to an amplifier topology known in the art as an instrumentation amplifier. Illustrated in FIG. 4, is a simplified schematic employing this approach to the input circuitry of an instrumentation amplifier formed by the two operational amplifiers A1 and A2. In this case, the input voltage is applied between terminals V_IN+ and V_IN−. The output voltage is available between terminals V_OUT+ and V_OUT−. The closed-loop gain for differential input voltages will be identical to the closed loop gain described previously for the single-ended programmable-gain amplifier. The closed-loop gain for common-mode input voltages will be unity as long as opamps A₁ and A₂ have sufficient open loop common-mode rejection.

Thus, the reconfigurable network arrangement forms an area-efficient gain programming network for amplifiers. When employed with an amplifier, the combination forms a programmable-gain amplifier whose gain can be controlled by controlling the operation of the various switches, and more specifically to a low-noise, low-distortion programmable-gain amplifier with gain settings that can be varied in arbitrarily-chosen discrete steps, and that can be implemented using a relatively small number of electronic switch elements in an integrated circuit.

It should be appreciated that a reconfigurable network arrangement of the type described can be formed with one or more operational amplifiers on a single integrated chip, or arranged separately from the operational amplifier as two or more separate parts. Further, while all of the embodiments of the reconfigurable feedback arrangement have been described as including one or more plurality of resistors, in implementing the circuits impedance devices can be used to establish the resistance values.

Those skilled in the art will recognize that changes can be made to the general approach described. For example, the gains chosen may be different than those cited for the embodiment mentioned above. The amplifier used may be implemented using different active devices and various topologies. The switches used may also vary in their implementation. In addition, while the illustrated embodiments are shown in FIGS. 2-4 as inverting amplifiers providing negative feedback, it is possible to employ the reconfigurable feedback with a non-inverting amplifier for positive feedback should an application for such an arrangement be required.

Thus, a new and improved area efficient, programmable-gain amplifier is provided in accordance with the present disclosure. The exemplary embodiments described in this specification have been presented by way of illustration rather than limitation, and various modifications, combinations and substitutions may be effected by those skilled in the art without departure either in spirit or scope from this disclosure in its broader aspects and as set forth in the appended claims.

The new and improved reconfigurable network arrangement when coupled to an operational amplifier provides an area efficient, programmable-gain amplifier. All elements thereof, are contained within the scope of at least one of the following claims. No elements of the presently disclosed system and method are meant to be disclaimed, nor are they intended to necessarily restrict the interpretation of the claims. In these claims, reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference, and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”

Claims

1. A reconfigurable network arrangement for use with at least one operational amplifier, including a plurality of resistors and a plurality switches constructed so that the resistors can be coupled to one or more operational amplifiers and selectively programmed so as to form a feedback path so as to selectively set the gain of the amplifier, the plurality of resistors and plurality of switches being arranged so that the resistors can be selectively connected in the feedback path in series and in parallel with each other so as to provide a selection of gain settings.

2. A reconfigurable network arrangement according to claim 1, wherein the plurality of resistors and plurality of switches include a first plurality of resistors connected in series so as to provide a resistor string;a first plurality of switches constructed and arranged so that one or more junctions between resistors of the first plurality can be connected to one of the operational amplifier's input terminals;a second plurality of resistors; anda second plurality of switches constructed and arranged so each of the second plurality of resistors can be selectively connected into the feedback path in parallel with one another;wherein the reconfigurable feedback path is configured to be coupled to the operational amplifier as a function of the one or more resistors of the first and second plurality connected in the feedback path.

3. A reconfigurable network according to claim 2, wherein the second plurality of switches are constructed and arranged so as to selectively connect each of the second plurality of resistors into the feedback path so that resistors of the second plurality connected in the feedback path will be connected in parallel with at least one of the resistors of the first plurality.

4. A reconfigurable network according to claim 2, wherein the resistor string is constructed and arranged so that it can be connected between the output of the amplifier and a reference node, and is configured as a voltage divider, wherein the state of the first plurality of switches determines where the voltage divider is tapped with respect to the feedback path arrangement.

5. A reconfigurable network according to claim 2, wherein the first plurality of resistors are arranged as a resistor string including a plurality of tapping points, and each of the first plurality of switches selectively taps a corresponding substantially one of the tapping points of the resistor string so as to define the voltage division ratio in the feedback path.

6. A reconfigurable network according to clam 2, wherein the second plurality of resistors are configured as a bank of resistors arranged so that each is connectable between the output of the amplifier and substantially one tap on the resistor string depending on the state of a corresponding switch of the second plurality.

7. A reconfigurable network according to claim 2, further including a controller for controlling the operation of each of the switches.

8. A reconfigurable network according to claim 2, one of the resistors (R1) of the resistor string can be connected between the output of the operational amplifier and the other resistors in the resistor string, such that the gain of the amplifier is defined as:

9. A reconfigurable network according to claim 8, wherein the closed loop gain is a function of the product of 1/k and (RSTRING+RP).

10. A reconfigurable network according to claim 8, wherein the first plurality of resistors includes N+1 resistors, the second plurality of resistors includes M resistors, k has a value between 0 and 1, and RP has possible values of 2M, wherein M is an integer.

11. A reconfigurable network according to claim 8, wherein each of the second plurality of resistors is successively connected in parallel with the resistor R1 of the first plurality such that the value of Rp for any gain setting is always determined as a function of the maximum number of parallel resistors connected in parallel with resistor R1.

12. A reconfigurable network according to claim 8, wherein each of the second plurality of resistors has a resistance at least ten times greater than the resistance of resistor R1 of the first plurality.

13. A reconfigurable network according to claim 1, wherein the feedback path arrangement is configured to be connected to the operational amplifier so as to provide a reconfigurable feedback path between the output and the non-inverting input of the operational amplifier.

14. A reconfigurable network according to claim 2, wherein the feedback path arrangement is configured to be connected to the operational amplifier so as to provide a reconfigurable feedback path between the output and the inverting input of the operational amplifier.

15. A reconfigurable network according to claim 2, wherein the feedback path arrangement is further configured to be connected to a second operational amplifier so as to provide a second reconfigurable feedback path between an input and an output of the second operational amplifier so that the closed-loop differential gains of both operational amplifiers can be programmed at any one of a plurality of gain settings, the feedback path arrangement further comprising: a third plurality of resistors connected in series so as to provide a second resistor string;a third plurality of switches constructed and arranged so that one or more junctions can be selectively connected between resistors of the third plurality to one of the second operational amplifier's input terminals;a fourth plurality of resistors; anda fourth plurality of switches constructed and arranged so that each of the fourth plurality of resistors can be selectively connected into the second feedback path;wherein the selected gain setting is a function of the first and second feedback paths established as a function of the one or more resistors of the third and fourth plurality connected in the second feedback path.

16. A reconfigurable network according to claim 15, wherein the fourth plurality of switches are constructed and arranged so as to selectively connect each of the fourth plurality of resistors into the feedback path so that resistors of the fourth plurality connected in the feedback path will be connected in parallel with at least one of the resistors of the third plurality.

17. A reconfigurable network according to claim 15, wherein the resistor string is constructed and arranged so that it can be connected between the output of the amplifier and a reference node, and is configured as a voltage divider, wherein the state of the third plurality of switches determines where the voltage divider is tapped with respect to the feedback path arrangement.

18. A reconfigurable network according to claim 15, wherein the third plurality of resistors is arranged as a resistor string including a plurality of tapping points, and each of the third plurality of switches selectively taps a corresponding substantially one of the tapping points of the resistor string so as to define the voltage division ratio in the feedback path.

19. A reconfigurable network according to clam 15, wherein the fourth plurality of resistors are configured as a bank of resistors arranged so that each is connectable between the output of the amplifier and one tap on the resistor string depending on the state of a corresponding switch of the fourth plurality.

20. A reconfigurable network according to claim 2, further including a controller for controlling the operation of each of the switches.

21. A reconfigurable network according to claim 2, in which one of the resistors (R1) of the resistor string is configured to be connected between the output of the second operational amplifier and the other resistors in the resistor string, so that the gain of the amplifier is defined as:

22. A reconfigurable network according to claim 21, wherein the closed loop gain is a function of the product of 1/k and (RSTRING+RP).

23. A reconfigurable network according to claim 21, wherein the first plurality of resistors includes N+1 resistors, the second plurality of resistors includes M resistors, k has a value between 0 and 1, and RP has possible values of 2M, wherein M is an integer.

24. A reconfigurable network according to claim 2, wherein the first plurality of switches includes N switches; and the second plurality of switches includes M switches, wherein the amplifier is programmable to any one of N*(M+1) states.

25. A reconfigurable network according to claim 2, wherein the values of the resistors of the second plurality of resistors are set so that each provides substantially a 1 dB change in closed loop gain when connected in the feedback path.

26. A reconfigurable network according to claim 2, wherein the values of the resistors of the first plurality of resistors are set so that each provides substantially an 8 dB change in gain of the amplifier.

27. A reconfigurable network according to claim 1, wherein the feedback path arrangement is configured to be connected to the second operational amplifier so as to provide a reconfigurable feedback path between the output and the non-inverting input of the second operational amplifier.

28. A reconfigurable network according to claim 1, wherein the feedback path arrangement is configured to be connected to the second operational amplifier so as to provide a reconfigurable feedback path between the output and the inverting input of the second operational amplifier.

29. A reconfigurable network according to claim 28, wherein the gain setting determined by the reconfigurable feedback network determines the differential gain of the resulting amplifier when the first and second operational amplifiers are connected as a differential pair.

30. A reconfigurable network according to claim 28, wherein the feedback path arrangement is configured to be connected to the first and second operational amplifiers so as to provide the respective first and second reconfigurable feedback paths between the inverting inputs and corresponding outputs of the respective operational amplifiers.

31. A reconfigurable network according to claim 1, wherein the feedback path arrangement is configured to be connected to a voltage-feedback type amplifier.

32. A reconfigurable network according to claim 1, wherein the feedback path arrangement is configured to be connected to a current-feedback type amplifier.

33. A reconfigurable network for use with at least one operational amplifier, comprising: a feedback path arrangement configured to be connected to the operational amplifier so as to provide a reconfigurable feedback path between an input and an output of the operational amplifier so that the gain of the operational amplifier can be programmed at any one of a plurality of gain settings, the feedback path arrangement comprising: a first plurality of resistors connected in series so as to provide a resistor string;a first plurality of switches constructed and arranged so as to selectively connect one or more junctions between resistors of the first plurality to one of the operational amplifier's input terminals;a second plurality of resistors; anda second plurality of switches constructed and arranged so as to selectively connect each of the second plurality of resistors into the feedback path in parallel with one another;wherein the reconfigurable feedback path is configured to be coupled to the operational amplifier as a function of the one or more resistors of the first and second plurality connected in the feedback path.

34. A reconfigurable network according to claim 33, wherein the second plurality of switches are constructed and arranged so as to selectively connect each of the second plurality of resistors into the feedback path so that resistors of the second plurality connected in the feedback path will be connected in parallel with at least one of the resistors of the first plurality.

35. A reconfigurable network according to claim 33, wherein the resistor string is constructed and arranged so that it can be connected between the output of the amplifier and a reference node, and is configured as a voltage divider, wherein the state of the first plurality of switches determines where the voltage divider is tapped with respect to the feedback path arrangement.

36. A reconfigurable network according to claim 33, wherein the first plurality of resistors are arranged as a resistor string including a plurality of tapping points, and each of the first plurality of switches selectively taps a corresponding substantially one of the tapping points of the resistor string so as to define the voltage division ratio in the feedback path.

37. A reconfigurable network according to clam 33, wherein the second plurality of resistors are configured as a bank of resistors arranged so that each is connectable between the output of the amplifier and substantially one tap on the resistor string depending on the state of a corresponding switch of the second plurality.

38. A reconfigurable network according to claim 33, further including a controller for controlling the operation of each of the switches.

39. A reconfigurable network according to claim 33, one of the resistors (R1) of the resistor string can be connected between the output of the operational amplifier and the other resistors in the resistor string, such that the gain of the amplifier is defined as:

40. A reconfigurable network according to claim 39, wherein the closed loop gain is a function of the product of 1/k and (RSTRING+RP).

41. A reconfigurable network according to claim 39, wherein the first plurality of resistors includes N+1 resistors, the second plurality of resistors includes M resistors, k has a value between 0 and 1, and RP has possible values of 2M, wherein M is an integer.

42. A reconfigurable network according to claim 39, wherein each of the second plurality of resistors is successively connected in parallel with the resistor R1 of the first plurality such that the value of Rp for any gain setting is always determined by the maximum possible number of parallel resistors.

43. A reconfigurable network according to claim 39, wherein each of the second plurality of resistors has a resistance at least ten times greater than a resistance of resistor R1 of the first plurality.

44. A reconfigurable network according to claim 33, wherein the feedback path arrangement is configured to be connected to the operational amplifier so as to provide a reconfigurable feedback path between the output and the non-inverting input of the operational amplifier.

45. A reconfigurable network according to claim 33, wherein the feedback path arrangement is configured to be connected to the operational amplifier so as to provide a reconfigurable feedback path between the output and the inverting input of the operational amplifier.

46. A reconfigurable network according to claim 33, wherein the feedback path arrangement is further configured to be connected to a second operational amplifier so as to provide a second reconfigurable feedback path between an input and an output of the second operational amplifier so that the gain of the second operational amplifier can be programmed at any one of a plurality of gain settings, the feedback path arrangement further comprising: a third plurality of resistors connected in series so as to provide a second resistor string;a third plurality of switches constructed and arranged so that one or more junctions can be selectively connected between resistors of the third plurality to one of the second operational amplifier's input terminals;a fourth plurality of resistors; anda fourth plurality of switches constructed and arranged so that each of the fourth plurality of resistors can be selectively connected into the second feedback path;wherein the selected gain setting is a function of the first and second feedback paths established as a function of the one or more resistors of the third and fourth plurality connected in the second feedback path.

47. A reconfigurable network according to claim 46, wherein the fourth plurality of switches are constructed and arranged so as to selectively connect each of the fourth plurality of resistors into the feedback path so that resistors of the fourth plurality connected in the feedback path will be connected in parallel with at least one of the resistors of the third plurality.

48. A reconfigurable network according to claim 46, wherein the resistor string is constructed and arranged so that it can be connected between the output of the amplifier and a reference node, and is configured as a voltage divider, wherein the state of the third plurality of switches determines where the voltage divider is tapped with respect to the feedback path arrangement.

49. A reconfigurable network according to claim 46, wherein the third plurality of resistors are arranged as a resistor string including a plurality of tapping points, and each of the third plurality of switches selectively taps a corresponding substantially one of the tapping points of the resistor string so as to define the voltage division ratio in the feedback path.

50. A reconfigurable network according to clam 46, wherein the fourth plurality of resistors are configured as a bank of resistors arranged so that each is connectable between the output of the amplifier and one tap on the resistor string depending on the state of a corresponding switch of the fourth plurality.

51. A reconfigurable network according to claim 33, further including a controller for controlling the operation of each of the switches.

52. A reconfigurable network according to claim 33, wherein one of the resistors (R1) of the resistor string is configured to be connected between the output of the second operational amplifier and the other resistors in the resistor string, so that the gain of the amplifier is defined as:

53. A reconfigurable network according to claim 52, wherein the closed loop gain is a function of the product of 1/k and (RSTRING+RP).

54. A reconfigurable network according to claim 52, wherein the first plurality of resistors includes N+1 resistors, the second plurality of resistors includes M resistors, k has a value between 0 and 1, and RP has possible values of 2M, wherein M is an integer.

55. A reconfigurable network according to claim 33, wherein the first plurality of switches includes N switches; and the second plurality of switches includes M switches, wherein the amplifier is programmable to any one of N*(M+1) states.

56. A reconfigurable network according to claim 33, wherein the values of the resistors of the second plurality of resistors are set so that each provides substantially a 1 dB change in closed loop gain when connected in the feedback path.

57. A reconfigurable network according to claim 33, wherein the values of the resistors of the first plurality of resistors are set so that each provides substantially an 8 dB change in the gain of the amplifier.

58. A reconfigurable network according to claim 33, wherein the feedback path arrangement is configured to be connected to the second operational amplifier so as to provide a reconfigurable feedback path between the output and the non-inverting input of the second operational amplifier.

59. A reconfigurable network according to claim 33, wherein the feedback path arrangement is configured to be connected to the second operational amplifier so as to provide a reconfigurable feedback path between the output and the inverting input of the second operational amplifier.

60. A reconfigurable network according to claim 59, wherein the gain setting determined by the reconfigurable feedback network determines the differential gain of the resulting amplifier and the common mode gain is always unity when the first and second operational amplifiers are connected as a differential pair.

61. A reconfigurable network according to claim 59, wherein the feedback path arrangement is configured to be connected to the first and second operational amplifiers so as to provide the respective first and second reconfigurable feedback paths between the inverting inputs and corresponding outputs of the respective operational amplifiers.

62. A reconfigurable network according to claim 33, wherein the feedback path arrangement configured to be connected to a voltage-feedback type amplifier.

63. A reconfigurable network according to claim 33, wherein the feedback path arrangement configured to be connected to a current-feedback type amplifier.

64. An amplifier circuit comprising: at least one operational amplifier; anda reconfigurable network arrangement for use with the operational amplifier, the reconfigurable network arrangement including: a plurality of resistors and a plurality switches constructed so that the resistors can be coupled to one or more operational amplifiers and selectively programmed so as to form a feedback path so as to selectively set the gain of the amplifier, the plurality of resistors and plurality of switches being arranged so that the resistors can be selectively connected in the feedback path in series and in parallel with each other so as to provide a selection of gain settings.