Wu,I-W., Lewis, A., and Chiang, A., "Effects of Solid Phase Crystallization and LDD Doping on Leakage Current Distributions in Poly-Si TFTs with Multiple Gate Structures," Japan Display '92, SID, 1992, pp. 455-458. |
Hack, M., Wu, I-W., Lewis, A.G., and King, T.J., "Numerical Simulations of On and Off State Characteristics of Poly-Silicon Thin Film Transistors," Proceedings, 51st Annual Device Research Conference, Santa Barbara, Calif., Jun. 21-23, 1993. |
Wu, I-W., "Polycrystalline Silicon Thin Film Transistors for Liquid Crystal Displays," Solid State Phenomena, Scitec Publications, Switzerland, 1994, pp. 553-564. |
Wu, I-W., "Cell Design Considerations for High-Aperture-Ratio Direct-View and Projection Polysilicon TFT-LCDs," 95 SID Digest, May 1995, pp. 19-22. |
Wu, I-W., Stuber, S., Tsai, C.C., Yao, W., Lewis, A., Fulks, R., Chiang, A., and Thompson, M., "Processing and Device Performance of Low-Temperature CMOS Poly-TFTs on 18.4-in.-Diagonal Substrates for AMLCD Application," SID 92 Digest, 1992, pp. 615-618. |
Kaneko, E., "Novel Key Technologies Used to Fabricate Very-Large-Area TFT-LCD Panels," SID 95 Digest,pp. 150-153. |
Wu, I-W., "Low Temperature Poly-Si Technology for AM-LCDs," AM-LCD 95: 1995 International Workshop on Active-Matrix Liquid-Crystal Displays, Osaka, Japan, Aug. 24-25, 1995, pp. 7-10. |
Lewis, A., and Wu, I-W., "Polysilicon TFTs for Active Matrix Liquid Crystal Displays," IEICE Transactions, vol. J76-C-II, No. 5, May, 1993, p. 211-226. |
Strum, J.C., Wu, I.-W., and Hack, M., "Leakage Current Modeling of Series-Connected Thin Film Transistors," IEEE Transactions and Electron Devices, vol. 42, No. 8, Aug. 1995, pp. 1561-1563. |
Wu, I-Wei, "High-definition displays and technology trends in TFT-LCDs," Journal of the SID, Feb. 1, 1994, pp. 1-14. |
U.S. Patent Application No. 08/277,719 entitled "Reduced Leakage Current Multiple Gate Thin Film Transistors", filed on Jul. 20, 1994. |
U.S. Patent Application No. 08/560,724 entitled "Forming Array Having Multiple Channel Structures with Continuously Doped Interchannel Regions", filed on Nov. 20, 1995. |
U.S. Patent Application No. 08/572,357 entitled "Array with Metal Scan Lines Controlling Semiconductor Gate Lines", filed on Dec. 15, 1995. |
U.S. Patent Application No. 08/367,984 entitled "Circuitry with Gate Line Crossing Semiconductor Line at Two or More Channels", filed on Jan. 3, 195. |