Patent Application
20240222396
This application claims the benefit of priority of China Patent Application No. 202211737090.3 filed on Dec. 30, 2022, the contents of which are incorporated by reference as if fully set forth herein in their entirety.
The present application relates to the technical field of design and manufacturing of display panels, and especially relates to an array substrate and a manufacturing method thereof, and a display panel.
With continuous development of manufacturing technologies of display panels, people put forward higher requirements for various performances of the display panels and devices.
In prior arts, when a display panel is being prepared, it is necessary to prepare an array substrate which is corresponding to the display panel and includes a plurality of thin film transistors in the array substrate, so as to ensure a normal use of the display panel. Structures of the thin film transistors which are commonly used generally include functional film layers such as a source electrode, a drain electrode, a gate, and a semiconductor layer. When the functional film layers is being prepared, for example, when the semiconductor layer is being prepared, semiconductor materials which are commonly used are inorganic semiconductor materials. The inorganic semiconductor materials also require different etching processes for processing. Meanwhile, in manufacturing processes, Many times of deposition of different film layers and photomask processing are required to finally form desired structures. However, there are too many process steps, and there are certain deviations in many different processing steps, which reduce consistency of films. Thus, production costs are increased, and it is not conducive to further improve comprehensive performance of thin film transistor array substrates.
In summary, for the thin film transistors prepared in the prior arts, the manufacturing processes of the thin film transistors are complicated, which requires many times of the deposition of film layers and etching processing. Production costs are much high, and it is not conducive to improve comprehensive performance of the array substrate.
An object of the present application is to provide an array substrate and a manufacturing method thereof, and a display panel, so as to effectively improve problems that manufacturing processes of thin film transistors in existing display panel are complex and comprehensive performance of the thin film transistors are not ideal.
In order to solve technical problems mentioned above, the present application provides an array substrate, the array substrate includes:
a substrate;
a source electrode and a drain electrode disposed on the substrate, the drain electrode is disposed at one side of the source electrode;
a semiconductor layer disposed between the source electrode and the drain electrode, and the semiconductor layer overlaps with a portion of the source electrode and a portion of the drain electrode; and
a channel defining layer, the channel defining layer is correspondingly disposed on the source electrode and the drain electrode, and is disposed around the semiconductor layer.
According to an embodiment of the present application, the film thickness of the channel defining layer is greater than or equal to the film thickness of the semiconductor layer.
According to an embodiment of the present application, the channel defining layer is provided with a printing opening, and the semiconductor layer is correspondingly disposed in the printing opening, and is in contact with the channel defining layer, the source electrode, and the drain electrode which are corresponding to the printing opening.
According to an embodiment of the present application, the source electrode and the drain electrode are correspondingly disposed at two sides of the printing opening, and a portion of the source electrode and a portion of the drain electrode extend into the printing opening.
According to an embodiment of the present application, each of the source electrode and the drain electrode comprises an extension portion, the extension portion of the source electrode and the extension portion of the drain electrode both extend into the printing opening, and at least a portion of the semiconductor layer overlaps with the extension portion of the source electrode and the extension portion of the drain electrode.
According to an embodiment of the present application, the length of the extension portion of the source electrode is the same as the length of the extension portion of the drain electrode, and an overlapping area between the semiconductor layer and the extension portion of the source electrode is the same as overlapping area between the semiconductor layer and the extension portion of the drain electrode.
According to an embodiment of the present application, the length of the extension portion of the source electrode and the length of the extension portion of the drain electrode are greater than or equal to 2.5 millimetre.
According to an embodiment of the present application, the width of the source electrode and the width of the drain electrode are less than the width of the semiconductor layer.
According to a second aspect of embodiments of the present application, a display panel is provided, and the display panel includes the array substrate in embodiments of the present application.
According to a third aspect of embodiments of the present application, a manufacturing method of an array substrate is provided, the manufacturing method of the array substrate includes following steps:
preparing a substrate, and depositing a gate on the substrate;
depositing a gate insulating layer on the gate, and preparing a source/drain metal layer on the gate insulating layer;
preparing a channel defining layer on the source/drain metal layer, etching the source/drain metal layer and the channel defining layer to form a printing opening;
printing a semiconductor layer in the printing opening, and drying the semiconductor layer; and
preparing a passivation layer on the semiconductor layer.
In terms of beneficial effects of embodiments of the present application, compared with prior arts, embodiments of the present application provide the array substrate and the manufacturing method thereof, and the display panel. The array substrate includes the substrate, the source electrode, the drain electrode, the semiconductor layer and the channel defining layer. The semiconductor layer is disposed between the source electrode and the drain electrode, and partially overlaps with the source electrode and the drain electrode. The channel defining layer is disposed around the semiconductor layer and is correspondingly disposed on the source electrode and the drain electrode. When the semiconductor layer is being prepared, the semiconductor layer is directly printed in the printing opening defined in the channel defining layer. The channel defining layer prevents the semiconductor layer from overflowing, and the semiconductor layer is further dried, so that the array substrate is finally formed. In the embodiments of the present application, the semiconductor layer is directly prepared by printing, thereby effectively simplifying preparation processes of film layers in the array substrate and improving comprehensive performance of the display panel.
In order to more clearly illustrate embodiments or the technical solutions of the present application, the accompanying figures of the present application required for illustrating embodiments or the technical solutions of the present application will be described in brief. Obviously, the accompanying figures described below are only part of the embodiments of the present application, from which those skilled in the art can derive further figures without making any inventive efforts.
Technical solutions of the present application are described below in conjunction with drawings in embodiments of the present application. The following disclosure provides different embodiments or examples to realize different structures of the present application. To simplify the present application, components and arrangements of specific examples are described below. In addition, various examples of specific processes and materials provided by the present application make it that those skilled in the art can realize applications of other technologies. All other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.
In description of the present application, It should be understood that orientations or position relationships indicated by terms such as “center”, “longitudinal”, “transverse”, “length”, “width”, “thickness”, “up”, “down”, “front”. “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, etc. are based on orientations or position relationships shown in the drawings, which are only for convenience of describing the present application and simplifying the description, and does not indicate or imply that a device or an element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be interpreted as a limitation of the present application. In addition, terms such “first” and “second” are only used for description, and cannot be interpreted as indicating or implying relative importance or implying a number of technical features indicated.
With continuous development of manufacturing technologies of display panels and array substrates, people put forward higher requirements for performance and display effect of the display panels.
In a process of manufacturing the array substrate, a plurality of thin film transistors are usually formed in the array substrate. Active layers and other functional layers in the thin film transistors play important roles in terms of performance of the thin film transistors. In existing preparation processes, when the active layers of the thin film transistor are being prepared, deposition or evaporation are usually carried out to form the active layers. Then, many times of photomask processing are performed to prepare the active layers after deposition or evaporation. Therefore, processing procedures are more complicated, and production costs are high, and it is not conducive to further improve comprehensive performance of the display panels.
In embodiments of the present application, an array substrate and a display panel or a display device that is corresponding to the array substrate are provided. When an active layer in the array substrate is being prepared, the active layer is prepared by directly printing an organic semiconductor layer. Thus, preparation processes are effectively simplified, production costs are reduced, and comprehensive performance of the display panel are effectively improved.
As shown in
In embodiments of the present application, the functional film layers include a gate 111, a source electrode 110, a drain electrode 107, a semiconductor layer 188, and a channel defining layer 106. Specifically, the buffer layer 102 is disposed on the substrate 101. The substrate 101 may be provided with a flexible or rigid film layer, and film layers are supported by the substrate 101. In embodiments of the present application, the substrate 101 may be provided with a glass substrate. Meanwhile, the buffer layer 102 may be provided with a flexible or rigid film layer. Film materials of the substrate 101 and the buffer layer 102 can be selected according to different products.
Specifically, the gate 111 is disposed on the buffer layer 102, and the gate insulating layer 103 is disposed on the buffer layer 102. Meanwhile, the gate insulating layer 103 completely covers and protects the gate 111.
In embodiments of the present application, a source/drain metal layer is disposed on the gate insulating layer 103. The source/drain metal layer includes the source electrode 110 and the drain electrode 107. The source electrode 110 and the drain electrode 107 are both disposed on the gate insulating layer 103. For example, the source electrode 110 and the drain electrode 107 are disposed on two corresponding positions of the gate insulating layer 103, respectively.
Meanwhile, the semiconductor layer 188 is disposed on the gate insulating layer 103, and the semiconductor layer 188 is electrically connected to the source electrode 110 and the drain electrode 107 at the same time. For example, one end of the semiconductor layer 188 is electrically connected to the source electrode 110, another end of the semiconductor layer 188 is electrically connected to the drain electrode 107. In embodiments of the present application, the semiconductor layer 188 is prepared directly by printing an organic semiconductor material with ink, thereby effectively simplifying preparation processes of the semiconductor layer and reducing production costs.
In embodiments of the present application, in the array substrate, a channel defining layer 106 is further included, the channel defining layer 106 is disposed on the source/drain metal layer. Specifically, the channel defining layer 106 is disposed on the source electrode 110 and the drain electrode 107, and the channel defining layer 106 is disposed around the semiconductor layer 188.
Specifically, the channel defining layer 106 further includes a printing opening 222. The semiconductor layer 188 is correspondingly disposed in the printing opening 222. At the time of preparation, the organic semiconductor material is printed directly in the printing opening 222, and finally a desired film structure is obtained.
In embodiments of the present application, when the semiconductor layer 188 is provided, the thickness of the semiconductor layer 188 may be set to a same thickness at different regions. Or, according to actual requirements, the thickness of the semiconductor layer 188 adjacent to the source electrode 110 and the drain electrode 107 is greater than the thickness of the semiconductor layer 188 in the middle of the printing opening 222. There is no specific limitation here.
As shown in
Herein, the figure identified by “a” and the figure identified by “b” in
In the embodiments of the present application, as the printing opening 222 can be adjusted according to different product specifications, when a printing is carried out to form a layer, the thickness of the semiconductor layer can be adjusted by increasing or decreasing a volume of ink including an organic semiconductor material according to the requirements of different products. As a result, a purpose of saving materials is achieved. Meanwhile, as the area of the printing opening 222 can be adjusted, devices with different aperture ratios can also be prepared in the present application.
Meanwhile, in embodiments of the present application, the width of the source electrode 110 and the width of the drain electrode 107 may be less than the width of the semiconductor layer 188. In this way, better connection effect and better connection reliability between the source electrode 110, the drain electrode 107 and the semiconductor layer 188 are ensured.
Further, in conjunction with the film layer structures in
Meanwhile, in the printing opening 222, the semiconductor layer 188 overlaps with the source electrode 110 and drain electrode 107, and is in contact with an inner sidewall of the channel defining layer 106.
In embodiments of the present application, when a source/drain metal layer structure is provided, the source electrode 110 and the drain electrode 107 are correspondingly disposed at two sides of the printing opening 222, and a portion of the source electrode 110 and a portion of the drain electrode 107 extend into the printing opening 222.
Specifically, the source electrode 110 includes a first extension portion 1101, and the drain electrode 107 includes a second extension portion 1071. The first extension portion 1101 and the second extension portion 1071 are both disposed in the printing opening 222.
Meanwhile, both ends of the semiconductor layer 188 are connected to the first extension portion 1101 and the second extension portion 1071, respectively. For example, a portion of the semiconductor layer 188 is disposed on the first extension portion 1101, and a portion of the semiconductor layer 188 is disposed on and overlaps with the second extension portion 1071.
In embodiments of the present application, the extension length of the first extension portion 1101 may be the same as the extension length of the second extension portion 1071. Optionally, an overlapping area between the semiconductor layer 188 and the first extension portion 1101 may be the same as an overlapping area between the semiconductor layer 188 and the second extension portion 1071. Thus, same contact areas between different films are ensured, and stability and consistency of performance of the thin film transistor are ensured.
Specifically, the extension length of the first extension portion 1101 and the extension length of the second extension portion 1071 may be set to be greater than or equal to 2.5 millimeters. Meanwhile, the thickness of the semiconductor layer 188 may be set to be greater than 100 nanometers. For example, the thickness of the semiconductor layer 188 may be set to be 100 nanometers, 150 nanometers or the like. Optionally, the length of the first extension portion 1101 and the length of the second extension portion 1071 are set to be 2.5 millimeters, 3 millimeters, 5 millimeters or 7 millimeters. Or, the length of the first extension portion 1101 and the length of the second extension portion 1071 are set according to different product specifications. Thus, connecting effect between different films is ensured, and reliability of the devices is ensured.
In embodiments of the present application, when the array substrate is being prepared, the passivation layer 104 is disposed on the gate insulating layer 103, and the passivation layer 104 completely covers the channel defining layer 106 and the semiconductor layer 188. Meanwhile, the passivation layer 104 also covers portions of the source electrode 110 and the drain electrode 107. Thus, each of the film layers is encapsulated and protected.
Further, in embodiments of the present application, the array substrate is further provided with a via hole 223 disposed outside the channel defining layer 106. Meanwhile, the via hole 223 goes through the passivation layer 104 and exposes a portion of the drain electrode 107. In the embodiments of the present application, the via hole 223 is correspondingly disposed at a position above the drain electrode 107.
Further, the array substrate in the embodiments of the present application further includes a pixel electrode layer 105, and the pixel electrode layer 105 is disposed above the passivation layer 104. The pixel electrode layer 105 is disposed at one side of the drain electrode 107. Meanwhile, the pixel electrode layer 105 is electrically connected to the drain electrode 107 through the via hole 223. When the thin film transistor operates normally, a control signal is transmitted through the thin film transistor and the pixel electrode layer 105 to ensure a normal operation of the display panel.
In embodiments of the present application, a manufacturing method of an array substrate is provided. As shown in
S101: preparing a substrate, and depositing a gate on the substrate;
S102: depositing a gate insulating layer on the gate, and preparing a source/drain metal layer on the gate insulating layer;
S103: preparing a channel defining layer on the source/drain metal layer, etching the source/drain metal layer and the channel defining layer to form a printing opening;
S104: printing a semiconductor layer in the printing opening, and drying the semiconductor layer; and
S105: preparing a passivation layer on the semiconductor layer.
Specifically, in conjunction with
Referring to a structure in
Referring to film layers structures in
After the source/drain metal layer 122 is deposited and dried, then a channel defining layer 106 is deposited on the source/drain metal layer 122, and the channel defining layer 106 is cured into a film. In embodiments of the present application, the channel defining layer 106 may be provided with an inorganic film layer, such as SiNx or the like. Or, the channel defining layer 106 may include organic materials according to requirements of different products, which is not repeated here.
After preparation of the channel defining layer 106 is completed, an etching process is performed using a half-mask process. Specifically, the channel defining layer 106 is subjected to a half-mask etching process. After the half-mask etching process is completed, the channel defining layer 106 includes a step 123, and at a position corresponding to the gate 111, the channel defining layer 106 is further provided with a printing opening 222 by etching, the printing opening 222 exposes a surface of the source/drain metal layer 122.
Referring to
Further, Referring to
Meanwhile, when the portion of the channel defining layer 106 adjacent to the printing opening 222 is being etched, the channel defining layer 106 on the drain electrode 107 is also etched. At this step, the step 123 is mainly etched so that a portion of the drain electrode 107 is exposed.
Referring to
Further, referring to
Referring to
Referring to
In embodiments of the present application, the thickness of the passivation layer 104 can be set according to different product requirements. After the passivation layer 104 is prepared, a portion of the passivation layer 104 above the drain electrode 107 is etched to form a via hole 223. After an etching of the passivation layer 104 is completed, a surface of the drain electrode 107 is exposed, so that the drain electrode 107 can be electrically connected to other film layers.
Specifically, a pixel electrode layer 105 is deposited on the passivation layer 104. The pixel electrode layer 105 is disposed on a side of the drain electrode 107, and the pixel electrode layer 105 is electrically connected to the drain electrode 107 through the via hole 223, and a control signal is transmitted by the pixel electrode layer 105.
In the embodiments of the present application, the film layer structures and preparation processes of the array substrate are improved. When the semiconductor layer in the array substrate is being prepared, the semiconductor layer is prepared by printing and forming a film. When the printing is being carried out, the channel defining layer is provided, the channel defining layer can effectively prevent a printing ink from overflowing, thus printing effect of the printing ink is ensured. Therefore, the preparation processes of the array substrate are effectively simplified, the production costs of the array substrate are reduced, and the comprehensive performance of the array substrate is effectively improved.
Further, embodiments of the present application further provide a display panel and a display device. Specifically, the display panel includes the array substrate provided in the embodiments of the present application. When the display panel in the embodiments of the present application is being prepared, the semiconductor layer of the array substrate corresponding to the display panel is prepared by printing and forming a film. Preparation processes are simple, and production costs is low, thereby effectively simplifying film layer processes of the display panel, and improving comprehensive performance of the display panel.
In embodiments of the present application, the display panel and the display device may be mobile phones, computers, electronic papers, and display devices, etc., which are products or components that have display functions and driving functions of thin-film transistor, or have functions such as touch control, etc.
In summary, the array substrate and the manufacturing method thereof, and the display panel provided by the embodiment of the present application are described in detail above. This article uses specific cases for describing the principles and the embodiments of the present application, and the description of the embodiments mentioned above is only for helping to understand the method and the core idea of the present application. Although the present application is disclosed above with preferred embodiments, the preferred embodiments are not intended to limit the present application. Those skilled in the art can make various changes and embellishments without departing from the spirit and scope of the present application. Therefore, the scope of the present application is based on the scope defined by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211737090.3 | Dec 2022 | CN | national |
