Patent Application
20210132455
The present application claims priority to and the benefit of Chinese Patent Application No. 201911053760.8 filed Oct. 31, 2019, which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technologies, and in particular to an array substrate and a method of manufacturing the same, a liquid crystal display panel, a display device and a method of driving the same.
A thin film transistor liquid crystal display (TFT-LCD) occupies a dominant position in the current display field due to its advantages of light weight, small thickness, low power consumption, stable performance and relatively low cost. At present, the liquid crystal display continues to develop in a direction of large-size. As the size of the display panel increases, demand for the yield of the display panel is getting higher and higher.
In an aspect, an array substrate is provided, the array substrate includes: a first base; gate lines disposed above the first base and extending in a first direction, the gate lines being configured to provide scanning signals; data lines disposed above the first base and extending in the first direction, the data lines being configured to provide data voltage signals; and common electrode lines disposed above the first base and extending in a second direction intersected with the first direction, the common electrode lines being configured to provide common voltage signals. The gate lines, the data lines and the common electrode lines are insulated from one another, orthographic projections of the gate lines and the data lines on the first base do not overlap, and the gate lines and/or the data lines define the plurality of sub-pixel regions together with the common electrode lines.
In some embodiments, the array substrate further includes thin film transistors and pixel electrodes that are disposed above the first base, each sub-pixel region having at least one thin film transistor and a pixel electrode therein. Each thin film transistor includes a gate, an active pattern, a source and a drain. Sources of all thin film transistors in each column of sub-pixel regions arranged in the first direction are electrically connected to a corresponding data line, gates of all thin film transistors in the column of sub-pixel regions are electrically connected to a respective one of the gate line, and a drain of each thin film transistor in the column of sub-pixel regions is electrically connected to a corresponding pixel electrode.
In some embodiments, the pixel electrodes are disposed in a same layer and made of a same material as the common electrode lines.
In some embodiments, the gate lines and the data lines are arranged alternately in the second direction. The gate lines and the data lines are divided into a plurality of groups, each group includes a gate line and a data line most proximate to the gate line in the gate lines; and a gate line and a data line most proximate to each other in two adjacent groups define a sub-pixel region together with two adjacent common electrode lines.
In some embodiments, the gate lines are arranged at intervals in the second direction, and the gate lines are divided into a plurality of gate line groups, each gate line group includes two gate lines most proximate to each other in the gate lines. One of the data lines is disposed between the two gate lines in the gate line group; and in two adjacent gate line groups, a gate line in one gate line group most proximate to another gate line group, a gate line in the another gate line group most proximate to the one gate line group define two sub-pixel regions together with two adjacent common electrode lines.
In some embodiments, the gate is disposed between the active pattern and the first base as a bottom gate. The thin film transistor further includes a top gate disposed at a side of the source and the drain away from the first base, and the top gate is electrically connected to the bottom gate.
In some embodiments, a portion of a gate line connected to the thin film transistor serves as the top gate of the thin film transistor.
In some embodiments, an orthographic projection of the active pattern on the first base is within a range of an orthographic projection of the bottom gate on the first base. The orthographic projection of the active pattern on the first base is within a range of an orthographic projection of the portion of the gate line connected to the thin film transistor on the first base.
In some embodiments, each thin film transistor is configured in a way that a channel of the thin film transistor is U-shaped.
In some embodiments, the at least one thin film transistor includes two thin film transistors.
In some embodiments, the array substrate further includes common electrodes. At least one common electrode corresponds to each row of sub-pixel regions arranged in the second direction, and the at least one common electrode is electrically connected to a corresponding common electrode line.
In some embodiments, each common electrode is disposed in a respective one of the plurality of sub-pixel regions; or, at least two common electrodes correspond to each row of sub-pixel regions.
In another aspect, a liquid crystal display panel is provided, the liquid crystal display panel includes the array substrate.
In some embodiments, the liquid crystal display panel further includes an opposite substrate and a liquid crystal layer. The opposite substrate includes a second base and a plurality of post spacers disposed at a side of the second base proximate to the array substrate, an orthographic projection of each post spacer on the array substrate is within a region between a gate line and a data line most proximate to each other in the gate lines and the data lines. The liquid crystal layer is disposed between the array substrate and the opposite substrate.
In yet another aspect, a display device is provided. The display device includes the liquid crystal display panel, a gate driving circuit, a source driving circuit and a common electrode driving circuit. The gate driving circuit is connected to the gate lines, the gate driving circuit is configured to output scanning signals to the gate lines. The source driving circuit is connected to the data lines, the source driving circuit is configured to output data voltage signals to the gate lines. The common electrode driving circuit is connected to the common electrode lines, the common electrode driving circuit is configured to output common voltage signals to the common electrode lines.
In yet another aspect, a method of manufacturing the array substrate is provided. The method includes: forming the gate lines, the data lines and the common electrode lines above the first base. The gate lines and the data lines extend in the first direction and the common electrode lines extend in the second direction; the gate lines, the data lines and the common electrode lines are insulated from one another; orthographic projections of the gate lines and the data lines on the first base do not overlap; the gate lines and/or the data lines define the plurality of sub-pixel regions together with the common electrode lines.
In some embodiments, the method further includes: forming thin film transistors and pixel electrodes above the first base. Each sub-pixel region having at least one thin film transistor and a pixel electrode connected to the at least one thin film transistor therein, each thin film transistor includes a gate, an active pattern, a source and a drain: and all pixel electrodes and the common electrode lines are formed by a same patterning process; the source and the drain of the thin film transistor and the data lines are formed by a same patterning process.
In some embodiments, forming the at least one thin film transistor and the pixel electrode in each sub pixel region, includes: forming at least one gate on the first base by a first patterning process; forming a gate insulating layer on the first base on which the at least one gate have been formed; forming an active pattern corresponding to each gate on the gate insulating layer by a second patterning process; forming a source and a drain on the active pattern by a third patterning process; forming a first insulating layer on the source and the drain by a fourth patterning process, the first insulating layer including at least one first via hole at a position corresponding to the drain; forming the pixel electrode on the first insulating layer by a fifth patterning process, the pixel electrode being electrically connected to the drain by the at least one first via hole; forming a second insulating layer on the pixel electrode by a sixth patterning process, the at least one second via hole extending through the second insulating layer, the first insulating layer and the gate insulating layer being formed; and forming the gate lines on the second insulating layer by a seventh patterning process, each gate line corresponding to a respective one column of a plurality of columns of sub-pixel regions, a gate line corresponding to the sub-pixel region being electrically connected to the gate by the at least one second via hole, orthographic projections of the gate and the gate line on the first base being overlapped.
In yet another aspect, a method of driving the display device is provided, the method includes: in an image frame: outputting, by the gate driving circuit, scanning signals sequentially to the gate lines; outputting, by the source driving circuit, data signals to the data lines; and outputting, by the common electrode driving circuit, a common voltage to each of the common electrode lines.
In order to describe technical solutions in embodiments of the present disclosure more clearly, the accompanying drawings to be used in the description of embodiments of the present disclosure will be introduced briefly below. Obviously, the accompanying drawings to be described below are merely some embodiments of the present disclosure, and a person of ordinary skill in the art may obtain other drawings according to these drawings. In addition, the drawings to be described below may be regarded as schematic diagrams, and are not limitations on an actual size of a product, an actual process of a method and an actual timing of signals that the embodiments of the present disclosure relate to.
The technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings. Obviously, the embodiments to be described are merely some embodiments of the present disclosure rather than all embodiments. All other embodiments obtained by a person of ordinary skill in the art on the basis of the embodiments of the present disclosure are within the protection scope of the present disclosure.
It will be understood that in the description of the present disclosure, orientations or positional relationships indicated by terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, etc. are based on orientations or positional relationships shown in the drawings, merely to facilitate and simplify the description of the present disclosure, but not to indicate or imply that the referred devices or elements must have a particular orientation, or must be constructed or operated in a particular orientation. Therefore, they should not be construed as limitations to the present disclosure.
Unless the context requires otherwise, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” in the description and the claims are construed as open and inclusive, i.e., “inclusive, but not limited to”. In the description of the specification, the terms such as “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to same embodiment(s) or example(s). In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner.
Below, the terms “first” and “second” are only used for describing purpose, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or a plurality of the features. In the description of embodiments of the present disclosure, “a plurality of” means two or more unless otherwise defined.
In the description of some embodiments, the terms such as “connected” and its extensions may be used. For example, the term “connected” may be used in description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. However, the term “connected” may also mean that two or more components are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
The expression “A and/or B” includes the following combinations: only A, only B, and A and B.
Some embodiments of the present disclosure provide a liquid crystal display device. As shown in
The circuit board 5 is configured to provide signals required for display to the liquid crystal display panel 3. For example, the circuit board 5 is a printed circuit board assembly (PCBA), and the PCBA includes a printed circuit board (PCB) and timing controller (TCON), power management integrated circuit (PMIC) other integrated circuit (IC) or circuits, etc.
For example, a longitudinal section of the framework 1 is U-shaped, and as shown in
As shown in
The backlight 41 includes, for example, light-emitting diodes (LEDs). As shown in
As shown in
As shown in
In related art, in the array substrate, gate lines and data lines are generally arranged crosswise to define sub-pixel regions. However, in this arrangement manner, the gate lines and the data lines have overlapped regions therebetween, and a large parasitic capacitance usually exists between a gate line and a data line in their overlapped region, thereby increasing a probability of poor display such as flicker in the display device and affecting the display effect of the display device.
However, in some embodiments of the present disclosure, as shown in
The gate lines 311, the data lines 312 and the common electrode lines 313 are insulated from one another. In this case, the gate lines 311 are insulated from each other, the data lines 312 are insulated from each other, and the common electrode lines 313 are insulated from each other.
The gate lines 311 and/or the data lines 312 define a plurality of sub-pixel regions P′ together with the common electrode lines 313. A region where each sub-pixel P is located is a sub-pixel region P′. For example, the gate lines 311 and the common electrode lines 313 define a plurality of sub-pixel regions P. For another example, the data lines 312 and the common electrode lines 313 define a plurality of sub-pixel regions P′. For another example, the gate lines 311 and the data lines 312 define a plurality of sub-pixel regions P′ together with the common electrode lines 313.
In the embodiments of the present disclosure, since the gate lines 311 are parallel to the data lines 312, and the orthographic projections of the gate lines 311 and the data lines 312 on the first base 310 do not overlap, there is no overlapped region between the gate lines 311 and the data lines 312, thereby avoiding high parasitic capacitance existing between the gate lines 311 and the data lines 312.
In some examples, the width of the common electrode line 313 is less than that of the gate line 311. In this way, the overlapped region of the common electrode line 313 and the gate line 311 has a small area, resulting in a low parasitic capacitance. Thus, a probability of poor display such as flicker of the display device may be reduced, and the display effect may be improved.
In some examples, as shown in
In some other examples, as shown in
In some embodiments, as shown in
The description “in a same layer” means that in a process of forming the pixel electrodes 315 and the common electrode lines 313, a layer is formed by a same film forming process such as coating, inkjet printing, etc., and then a layer structure with specific patterns is formed by using a same mask and by performing a single patterning process. According to different specific patterns, the single patterning process may include multiple exposure, developing or etching processes. The specific patterns in the layer structure may be continuous or discontinuous and the specific patterns may be at different heights or may have different thicknesses.
In some embodiments, as shown in
As shown in
As shown in
For example, as shown in
For example, as shown in
For example, as shown in
As shown in
By setting the thin film transistor 314 as a double-gate thin film transistor, the time taken to turn on or off the thin film transistor 314 may be reduced, and the response speed of the thin film transistor 314 may be improved.
In some examples, as shown in
On this basis, in some examples, as shown in
In some examples, the orthographic projection of the active pattern 3142 on the first base 310 is within a range of an orthographic projection of the portion of the gate line 311 connected to the thin film transistor 314 on the first base 310.
In this way, the bottom gate 3141a may block light incident onto the active pattern 3142 from the backlight module 4, and the gate line 311 may block light incident onto the active pattern 3142 from the outside, thereby reducing the effect of light on the leakage current in the channel of the thin film transistor 314, and improving the stability of the thin film transistor 314. Meanwhile, the gate line 311 may replace a black matrix in the opposite substrate 40, and function to block the light-leaking. Therefore, there is no need to additionally provide a mask for forming the black matrix in the whole manufacturing process of the liquid crystal display panel 3, thereby reducing the cost.
In some examples, as shown in
The thin film transistor 314 having a U-shaped channel has a high width-to-length ratio, and the thin film transistor 314 having such a structure may be applied in a gate driving circuit.
As shown in
For example, as shown in
In some embodiments, the common electrode 316 is disposed at a side of the pixel electrode 315 away from the first base 310.
It may be known from the above description that the common electrodes 316 are disposed at intervals and the common electrodes 316 in different rows of sub-pixels P are insulated from each other. It will be noted that the common electrodes 316 may also be disposed in the opposite substrate 40 rather than the array substrate 30.
In an example where the first direction is a vertical direction and the second direction is a horizontal direction, the working principle of the liquid crystal display panel 3 including the array substrate 30 will be described below.
In an image frame, the gate lines 311 sequentially output scanning signals. When any gate line 311 outputs a scanning signal, thin film transistors 314 in a column of sub-pixels P connected to the gate line 311 are turned on. After the thin film transistors 314 in the column of sub-pixels P are turned on, a data line 312 connected to the thin film transistors 314 in the column of sub-pixels P outputs a data voltage, so as to provide the data voltage to the pixel electrodes 315 in the column of sub-pixels P. Meanwhile, each common electrode line 313 outputs a common voltage to at least one common electrode 316 connected to the common electrode line 313. For each sub-pixel P, the deflection angle of liquid crystal molecules in the region where the sub-pixel P is located is controlled by the voltages of the pixel electrode 315 and the corresponding common electrode 316, so that the sub-pixel P may display different grayscales.
That is, for a same column of sub-pixels P, the voltage of all pixel electrodes 315 in the column of sub-pixels P is the same. In addition, in the column of sub-pixels P, the voltage of each common electrode 316 is input independently. The voltages of the common electrodes 316 corresponding to the column of sub-pixels P may be the same, may be not exactly the same, or may be different completely.
In the array substrate 30 provided in some embodiments of the present disclosure, in the second direction, at least one common electrode 316 corresponding to each row of sub-pixel regions P′ is electrically connected to a corresponding common electrode line 313, which may ensure the normal operation of the liquid crystal display panel 3 including the array substrate 30.
In addition, the gate lines 311 are parallel to the data lines 312, regions where the gate lines 311 and the data lines 312 are located have a thickness greater than that of regions between the gate lines 311 and the data lines 312 in the array substrate 30.
In some embodiments, as shown in
In this way, an end of each post spacer 510 away from the second base 410 may be stuck in the region between the gate line 311 and data line 312 most proximate to each other on the array substrate 30. Therefore, the post spacer 510 may be prevented from sliding toward the sub-pixel region P′ when the liquid crystal display panel 3 is stressed excessively in its thickness direction. Since there is no need to provide any post spacer in the regions where the gate lines 311 are located, the width of each gate line may be made smaller, thereby increasing the aperture ratio of pixels.
As shown in
The gate driving circuit 6 is connected to the gate lines 311. The gate driving circuit 6 may be directly disposed in the array substrate 30 by using technology of a gate driver on array (GOA), or the gate driving circuit 6 may be an integrated circuit (IC) bonded on the array substrate 30 or on a flexible printed circuit connected to the array substrate 30.
The source driving circuit 7 is connected to the data lines 312. The source driving circuit 7 may be an IC bonded on the array substrate 30 or on the flexible printed circuit connected to the array substrate 30.
The common electrode driving circuit 8 is connected to the common electrode lines 313. The common electrode driving circuit 8 is configured to output common voltages to the common electrode lines 313. The common electrode driving circuit 8 may be an IC bonded on the flexible printed circuit connected to the array substrate 30.
Some embodiments of the present disclosure provide a method of manufacturing the array substrate 30, the method includes the following steps.
As shown in
In this case, the thin film transistors 314 in a same column of sub-pixel regions P′ arranged in the first direction are connected to a same gate line 311 and a same data line 312, and at least one common electrode 316 corresponding to a same row of sub-pixel regions P′ arranged in the second direction is connected to a same common electrode line 313.
On this basis, the method of manufacturing the array substrate 30 further includes: as shown in
For each column of sub-pixel region P′ arranged in the first direction, sources 3143 of all thin film transistors 314 in the column of sub-pixel regions P′ are electrically connected to a corresponding data line 312, gates 3141 of all thin film transistors 314 in the column of sub-pixel regions P′ are electrically connected to a respective one of gate lines 311, and a drain 3144 of each thin film transistor 314 in the column of sub-pixel regions P′ is electrically connected to a corresponding pixel electrode 315.
In some examples, all the pixel electrodes 315 and the common electrode lines 313 are formed by a same patterning process. The source 3143 and the drain 3144 of the thin film transistor 314 and the data lines 312 are formed by a same patterning process. Each of the two patterning process includes depositing, coating photoresist, exposing by a mask, developing and etching. In this way, the manufacturing process of the array substrate 30 may be simplified.
For the advantages of the method of manufacturing the array substrate 30 provided in some embodiments of the present disclosure, reference may be made to the advantages of the array substrate 30 described above.
In some embodiments, as shown in
In S10, as shown in
In S11, as shown in
In S12, as shown in
In S13, as shown in
In S14, as shown in
In S15, as shown in
In S16, as shown in
In S17 as shown in
Each of the first patterning process to the seventh patterning process may include depositing, coating photoresist, exposing by a mask, developing and etching. Of course, in a case where a material of the first insulating layer 3147 is a photosensitive resin (for example, photoresist), the fourth patterning process merely includes coating photoresist, exposing by a mask, and developing. In a case where a material of the second insulating layer 3148 is a photosensitive resin (for example, photoresist), the sixth patterning process merely includes coating photoresist, exposing by a mask, and developing.
As shown in
By setting the thin film transistor 314 as a double-gate thin film transistor, the time taken to turn on or off the thin film transistor 314 may be reduced, and the response speed of the thin film transistor 314 may be improved. Since the portion of the gate line 311 also serves as the top gate 3141b of the at least one thin film transistor 314 connected to the gate line 311, the top gate 3141b does not need to be formed separately, and the manufacturing process is simplified. Meanwhile, the gate line 311 may block light incident onto the active pattern 3142 from the outside, thus, the effect of light on the leakage current in the channel of the thin film transistor 314 may be reduced, and the stability of the thin film transistor 314 may be improved. In addition, the gate line 311 may replace a black matrix in the opposite substrate 40, and function to block the light-leaking. Therefore, there is no need to additionally provide a mask for forming the black matrix in the whole manufacturing process of the liquid crystal display panel 3, thereby reducing the cost.
Optionally, in the thin film transistor 314, in the thickness direction of the first base 310, an orthographic projection of the active pattern 3142 on the first base 310 is within a range of an orthographic projection of the bottom gate 3141a on the first base 310.
The orthographic projection of the active pattern 3142 on the first base 310 is within the range of an orthographic projection of the portion of the gate line 311 connected to the thin film transistor 314 on the first base 310.
On this basis, the bottom gate 3141a may block light incident onto the active pattern 3142 from the backlight module 4, and the gate line 311 may block light incident onto the active pattern 3142 from the outside, thereby reducing the effect of light incident onto the array substrate 30 on the leakage current in the channel of the thin film transistor 314, and improving the stability of the thin film transistor 314.
Some embodiments of the present disclosure provide a method of driving the display device. The method is used for driving the display device provided in the embodiments of the present disclosure. As shown in
In S20, the gate driving circuit sequentially outputs scanning signals to the gate lines 311.
In S21, the source driving circuit 7 outputs data signals to the data lines 312.
In S22, the common electrode driving circuit 8 outputs a common voltage to each of the common electrode lines 313.
The common electrode driving circuit 8 is controlled by an independent IC chip. The common electrode lines 313 are insulated from each other, and thus the common voltages on the common electrode lines 313 may be different.
In an example where the first direction is the vertical direction and the second direction is the horizontal direction, the working principle of the liquid crystal display panel 3 in the display device provided in the embodiments of the present disclosure will be described below.
In an image frame, when the gate driving circuit 6 outputs a scanning signal to any gate line 311, the thin film transistors 314 in a column of sub-pixels P connected to the gate line 311 are turned on. After the thin film transistors 314 in the column of sub-pixels P are turned on, the source driving circuit 7 outputs a data signal to a data line 312 connected to the sources 3143 of the thin film transistors 314 in the column of sub-pixels P, so as to provide a data voltage corresponding to the data signal to the pixel electrodes 315 in the column of sub pixels P. Meanwhile, the common electrode driving circuit 8 outputs a common voltage to each of the common electrode lines 313. For each sub-pixel P, the deflection angle of liquid crystal molecules in the region where the sub-pixel P is located is controlled by the voltages of the pixel electrode 315 and the corresponding common electrode 316, so that the sub-pixel P may display different grayscales.
The foregoing descriptions are merely specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art could readily conceive of changes or replacements within the technical scope of the present disclosure, which shall all be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201911053760.8 | Oct 2019 | CN | national |
