Patent Application
20250133825
The present disclosure relates to the field of the display technology, in particular to an array substrate and a touch display device comprising the array substrate.
Touch and display driver integration (TDDI) technology has been widely used in products such as mobile phones, tablet computers, desktop displays. With the equal quality trend of products becoming more and more serious, narrow borders, as one of the core competitiveness of products, can effectively enhance the added value of products. The layout of the fan-out area of TDDI products will directly affect the size of the bottom border of the products. How to reduce the bottom border through reasonable layout of the fan-out area is particularly important.
According to an aspect of the disclosure, an array substrate is provided, which comprises a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a fan-out area and a signal input area, and the fan-out area being between the display area and the signal input area, wherein the display area is provided with a plurality of display data lines and a plurality of touch data lines, the fan-out area is provided with a plurality of display data fan-out lines and a plurality of touch data fan-out lines, each display data fan-out line is connected with a corresponding display data line, and each touch data fan-out line is connected with a corresponding touch data line; and wherein the fan-out area comprises a first part and a second part which are adjacently distributed in a direction from the display area to the signal input area, in the first part of the fan-out area, each display data fan-out line comprises a first display data fan-out line segment connected with a corresponding display data line, each touch data fan-out line comprises a first touch data fan-out line segment connected with a corresponding touch data line, the first display data fan-out line segment is in a first conductive layer, and the first touch data fan-out line segment is in a second conductive layer electrically insulated from the first conductive layer.
In some embodiments, wherein in the display area, the plurality of display data lines and the plurality of touch data lines are in the second conductive layer.
In some embodiments, the array substrate further comprises a substrate, wherein the first conductive layer is arranged on the substrate, the second conductive layer is on a side of the first conductive layer facing away from the substrate, and the array substrate further comprises a first insulating layer between the first conductive layer and the second conductive layer, and a second insulating layer covering the second conductive layer and the first insulating layer, wherein each first display data fan-out line segment in the first conductive layer is electrically connected to a corresponding display data line in the second conductive layer through a fifth connecting part, one end of the fifth connecting part is connected with the first display data fan-out line segment through at least one ninth via hole penetrating the first insulating layer and the second insulating layer, and the other end of the fifth connecting part is connected with the display data line through at least one tenth via hole penetrating the second insulating layer, and wherein each first touch data fan-out line segment in the second conductive layer is integrally connected with a corresponding touch data line in a same layer.
In some embodiments, wherein each first display data fan-out line segment in the first conductive layer comprises a ninth widening portion, the corresponding display data line in the second conductive layer comprises a tenth widening portion, an orthographic projection of the at least one ninth via hole on the substrate is within an orthographic projection of the ninth widening portion on the substrate, and an orthographic projection of the at least one tenth via hole on the substrate is within an orthographic projection of the tenth widening portion on the substrate.
In some embodiments, wherein in the second part of the fan-out area, each display data fan-out line comprises a second display data fan-out line segment electrically connected with the first display data fan-out line segment, each touch data fan-out line comprises a second touch data fan-out line segment electrically connected with the first touch data fan-out line segment, the second part of the fan-out area comprises a first wiring area, a plurality of first wiring groups are arranged in the first wiring area, each first wiring group comprises a plurality of second display data fan-out line segments and at least one second touch data fan-out line segment, wherein the at least one second touch data fan-out line segment is in the second conductive layer, some of the plurality of second display data fan-out line segments are in the first conductive layer, and others of the plurality of second display data fan-out line segments are in the second conductive layer.
In some embodiments, wherein the second display data fan-out line segment or the second touch data fan-out line segment in the second conductive layer overlaps or is alternately arranged with the corresponding second display data fan-out line segment in the first conductive layer.
In some embodiments, the array substrate further comprises a substrate, wherein the first conductive layer is arranged on the substrate, and the second conductive layer is on a side of the first conductive layer facing away from the substrate, and the array substrate further comprises a first insulating layer between the first conductive layer and the second conductive layer, and a second insulating layer covering the second conductive layer and the first insulating layer, wherein each second display data fan-out line segment in the second conductive layer is electrically connected to a corresponding first display data fan-out line segment in the first conductive layer through a first connecting part, one end of the first connecting part is connected with the second display data fan-out line segment through at least one first via hole penetrating the second insulating layer, and the other end of the first connecting part is connected with the first display data fan-out line segment through at least one second via hole penetrating the first insulating layer and the second insulating layer.
In some embodiments, wherein each second display data fan-out line segment in the second conductive layer comprises a first widening portion, a corresponding first display data fan-out line segment in the first conductive layer comprises a second widening portion, an orthographic projection of the at least one first via hole on the substrate is within an orthographic projection of the first widening portion on the substrate, and an orthographic projection of the at least one second via hole on the substrate is within an orthographic projection of the second widening portion on the substrate.
In some embodiments, wherein each second display data fan-out line segment in the first conductive layer is electrically connected to a corresponding first display data fan-out line segment in the first conductive layer through a second connecting part, one end of the second connecting part is connected with the second display data fan-out line segment through at least one third via hole penetrating the first insulating layer and the second insulating layer, and the other end of the second connecting part is connected with the first display data fan-out line segment through at least one fourth via hole penetrating the first insulating layer and the second insulating layer.
In some embodiments, wherein each second display data fan-out line segment in the first conductive layer comprises a third widening portion, the corresponding first display data fan-out line segment in the first conductive layer comprises a fourth widening portion, an orthographic projection of the at least one third via hole on the substrate is within an orthographic projection of the third widening portion on the substrate, and an orthographic projection of the at least one fourth via hole on the substrate is within an orthographic projection of the fourth widening portion on the substrate.
In some embodiments, wherein the second part of the fan-out area further comprises a second wiring area arranged adjacent to the first wiring area, a plurality of second wiring groups are arranged in the second wiring area, and each second wiring group comprises at least two second touch data fan-out line segments.
In some embodiments, wherein two second touch data fan-out line segments in each second wiring group are in the second conductive layer.
In some embodiments, wherein each second touch data fan-out line segment is integrally connected with a corresponding first touch data fan-out line segment in a same layer.
In some embodiments, wherein two second touch data fan-out line segments of each second wiring group are overlapped or alternately arranged in the first conductive layer and the second conductive layer.
In some embodiments, wherein each second touch data fan-out line segment in the first conductive layer is electrically connected to a corresponding first touch data fan-out line segment in the second conductive layer through a third connecting part, one end of the third connecting part is connected with the second touch data fan-out line segment through at least one fifth via hole penetrating the first insulating layer and the second insulating layer, and the other end of the third connecting part is connected with the first touch data fan-out line segment through at least one sixth via hole penetrating the second insulating layer.
In some embodiments, wherein each second touch data fan-out line segment in the first conductive layer comprises a fifth widening portion, the corresponding first touch data fan-out line segment in the second conductive layer comprises a sixth widening portion, an orthographic projection of the at least one fifth via hole on the substrate is within an orthographic projection of the fifth widening portion on the substrate, and an orthographic projection of the at least one sixth via hole on the substrate is within an orthographic projection of the sixth widening portion on the substrate.
In some embodiments, wherein each second touch data fan-out line segment in the second conductive layer is electrically connected to a corresponding first touch data fan-out line segment in the second conductive layer through a fourth connecting part, one end of the fourth connecting part is connected with the second touch data fan-out line segment through at least one seventh via hole penetrating the second insulating layer, and the other end of the fourth connecting part is connected with the first touch data fan-out line segment through at least one eighth via hole penetrating the second insulating layer.
In some embodiments, wherein each second touch data fan-out line segment in the second conductive layer comprises a seventh widening portion, the corresponding first touch data fan-out line segment in the second conductive layer comprises an eighth widening portion, an orthographic projection of the at least one seventh via hole on the substrate is within an orthographic projection of the seventh widening portion on the substrate, and an orthographic projection of the at least one eighth via hole on the substrate is within an orthographic projection of the eighth widening portion on the substrate.
In some embodiments, the array substrate further comprises a common electrode, wherein the first connecting part, the second connecting part, the third connecting part, the fourth connecting part and the fifth connecting part are made in a same process as the common electrode.
In some embodiments, the array substrate further comprises a pixel electrode, wherein the first connecting part, the second connecting part, the third connecting part, the fourth connecting part and the fifth connecting part are made in a same process as the pixel electrode.
In some embodiments, wherein a plurality of display signal input lines and a plurality of touch signal input lines are arranged in the signal input area, each display signal input line is connected with a corresponding display data fan-out line, and each touch signal input line is connected with a corresponding touch data fan-out line.
In some embodiments, wherein each display signal input line is integrally connected with the second display data fan-out line segment of the corresponding display data fan-out line in a same layer, and each touch signal input line is integrally connected with the second touch data fan-out line segment of the corresponding touch data fan-out line in a same layer.
In some embodiments, wherein each display signal input line comprises a first bonding terminal, each touch signal input line comprises a second bonding terminal, and orthographic projections of each first bonding terminal and each second bonding terminal on the substrate do not overlap each other.
In some embodiments, wherein the first conductive layer is a gate layer and the second conductive layer is a source-drain layer.
According to another aspect of the present disclosure, a touch display device is provided, which comprises any of the aforementioned array substrates and a control chip, wherein pins of the control chip are connected with corresponding first bonding terminals and second bonding terminals in the signal input area.
In order to more clearly illustrate the technical solutions in embodiments of the disclosure, the drawings needed to be used in the description of the embodiments will be introduced briefly in the following. Obviously, the drawings in the following description are only some embodiments of the disclosure, and for those of ordinary skills in the art, other drawings may be obtained according to these drawings under the premise of not paying out creative work.
In order to make the objectives, technical solutions, and advantages of the present disclosure more clear, the present disclosure will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person having ordinary skill in the art without making creative efforts fall within the protection scope of the present disclosure.
It can be understood that the drawings in the embodiment of the present disclosure are only used to schematically show the connection relationship between various components, and the dimensions of various components in the drawings are not drawn to scale, and their relative position relationship does not necessarily correspond to the actual position. In the drawings, the proportions of some regions and layers may be exaggerated for clarity.
With the continuous development of display technology, in order to make users get better visual experience, higher requirements are put forward for the screen ratio of display devices, which requires the display devices to have narrower borders. In conventional TDDI products, touch signal lines and display signal lines are usually arranged in separate conductive layers. Since the number of display signal lines is usually more than that of touch signal lines, the bottom border of conventional TDDI products is determined by the wiring space of display signal lines, and the display signal lines arranged in a single layer lead to a large bottom border.
An embodiment of the present disclosure provides an array substrate, and
It should be noted that in the drawings of this application, different conductive layers are schematically represented by different filling patterns, in which the darker color pattern represents the first conductive layer and the lighter color pattern represents the second conductive layer. Only a part of the wiring structure is schematically shown in
Although the first conductive layer is below the second conductive layer in
According to the array substrate provided by the embodiment of the application, in the first part of fan-out area, all the first display data fan-out line segments are in the first conductive layer, and all the first touch data fan-out line segments are in the second conductive layer. This ensures that all the first touch data fan-out line segments are located at a same layer, and prevents the critical dimension difference between two adjacent first touch data fan-out line segments from being large due to process fluctuation of different layers, thereby avoiding the problem that the resistance difference between adjacent first touch data fan-out line segments is too large.
In a specific embodiment, the second display data fan-out line segment or the second touch data fan-out line segment in the second conductive layer may overlap or be alternately arranged with the corresponding second display data fan-out line segment in the first conductive layer. It should be noted that the word “alternately” in this application means that there is no overlap in the orthogonal projections of the lines in the two conductive layers on the substrate. By arranging the display data lines and the touch data lines in two conductive layers alternately, the mutual coupling between the two layers of lines can be effectively reduced. The word “overlap” in this application means that there is a certain degree of overlap in the orthogonal projections of the lines in the two conductive layers on the substrate. By overlapping the display data lines and the touch data lines in the two conductive layers, the space occupied by the lines in the fan-out area can be effectively reduced, thereby effectively reducing the size of the bottom border of the product.
Only two first wiring groups 324 in the first wiring area 323 are schematically shown in
In the first wiring group shown in
It should be noted that, even in the embodiment in which the lines in the first wiring group are arranged in an overlapping manner between the first conductive layer and the second conductive layer, in order to facilitate the layered arrangement of the display data lines and the touch data lines in the first part of the fan-out area, the orthogonal projections of the lines in the two conductive layers on the substrate are not overlapped in the area of second part of the fan-out area closest to the first part of the fan-out area. As shown in
In the cross-sectional views shown in
In some embodiments, as shown in
Since the lines in the fan-out area is usually very thin, it is extremely demanding to make via holes on a very thin line, which improves the manufacturing difficulty and makes it difficult to ensure the manufacturing accuracy. According to the embodiment of the disclosure, the first widening portion and the second widening portion are arranged, so that the process difficulty in manufacturing the via hole is simplified, and the manufacturing accuracy is improved.
For the second display data fan-out line segments in the first conductive layer in the second part of the fan-out area, such as 321a and 321c in
In some embodiments, as shown in
According to the embodiment of the disclosure, the third widening portion and the fourth widening portion are arranged, so that the process difficulty in manufacturing the via hole is simplified, and the manufacturing accuracy is improved.
It should be noted that in the above embodiment, the first wiring group includes three display data lines and one touch data line, that is, the number ratio of display data lines to touch data lines in the first wiring group is 3:1, which is only exemplary. A person skilled in the art can reasonably set the number and ratio of display data lines and touch data lines in the first wiring group according to the number of display data lines and touch data lines required in actual products, and this application is not limited to this, as long as the lines in the two conductive layers can be “overlapped” or “alternately arranged” in the second part of the fan-out area.
In some embodiments, as shown in
In the embodiment shown in
In the embodiments shown in
Referring to
According to the embodiment of the disclosure, the fifth widening portion and the sixth widening portion are arranged, so that the process difficulty in manufacturing the via hole is simplified, and the manufacturing accuracy is improved.
In some embodiments, as shown in
In some embodiments, as shown in
According to the embodiment of the disclosure, the fifth widening portion and the sixth widening portion are arranged, so that the process difficulty in manufacturing the via hole is simplified, and the manufacturing accuracy is improved.
It should be noted that in the drawings of this application, one touch data line is connected with one first touch data fan-out line segment, which is only schematic. In practice, one touch data line may also be connected with a plurality of first touch data fan-out line segments, and those skilled in the art can make reasonable design according to the actual situation.
For the sake of clarity, in
In some embodiments, the first connecting part, the second connecting part, the third connecting part, the fourth connecting part and the fifth connecting part can be made in a same process as the common electrode or the pixel electrode of the array substrate. In this way, the manufacturing process of the common electrode or the pixel electrode can be reused, the manufacturing process is simplified, and the cost is reduced.
In some embodiments, the common electrode or pixel electrode of the array substrate can be made of transparent conductive materials, such as ITO and IZO, and in this case, the first connecting part, the second connecting part and the third connecting part can also be made of transparent conductive materials.
In the embodiments of the application, the non-display area further includes a signal input area. As shown in
Referring to
In the above embodiments of the present application, the first conductive layer may be a gate layer, and the second conductive layer may be a source-drain layer. In this way, the manufacturing processes of the gate layer and the source-drain layer can be reused to manufacture the display data lines and the touch data lines, which not only simplifies the manufacturing process, but also reduces the thickness of the array substrate compared with the scheme of arranging the display data lines and the touch data lines with another separate conductive layer.
It should be noted that the term “wiring” in this application is a general term for various data lines, fan-out lines and signal input lines. In some cases, the word “wiring” is used only for the convenience of description. In specific contexts, those skilled in the art can clearly know which data lines, fan-out lines and signal input lines it refers to. In addition, in this application, when referring to the “electrical connection” of two lines or line segments, it includes not only the direct integral connection of two lines or line segments in the same layer, but also the connection of conductive lines or line segments in different layers through via holes, and other connection methods not described in this application.
According to another aspect of the present disclosure, a touch display device is provided, which includes an array substrate described in any of the previous embodiments and a control chip, wherein pins of the control chip are connected with corresponding first bonding terminals and second bonding terminals in the signal input area. The number of control chips is not specifically limited in this application, and those skilled in the art can arrange them according to actual needs.
In some embodiments, the touch display device can be liquid crystal display devices, including but not limited to mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo borders, navigators, e-books and other products or components with display functions.
Since the touch display device can have basically the same technical effect as the array substrate described in the previous embodiments, for the sake of brevity, the technical effect of the touch display device is not repeated here.
The inventor applied the inventive concept of this application to actual products, and two products are briefly introduced below.
The number of display signal lines is 4800, the number of touch signal lines is 2560, and a ratio of the number of display signal lines to the number of touch signal lines is 15:8. In the first wiring area, the ratio of the number of display signal lines to the number of touch signal lines is 3:1, and the redundant touch signal lines are arranged in the second wiring area. The product is driven by two control chips, and the second wiring area can be arranged between the two control chips. The wiring carried out in the manner described in the embodiment of the application can effectively reduce the wiring space in the fan-out area. The bottom border can be reduced by about 0.25˜0.35 mm with the same wiring cycle of the fan-out area.
The number of display signal lines is 3600, the number of touch signal lines is 1560, and a ratio of the number of display signal lines to the number of touch signal lines is 30:13. In the first wiring area, the ratio of the number of display signal lines to the number of touch signal lines is 3:1, and the redundant touch signal lines are arranged in the second wiring area. The product is driven by two control chips, and the second wiring area can be arranged between the two control chips. The wiring carried out in the manner described in the embodiment of the application can effectively reduce the wiring space in the fan-out area. The bottom border can be reduced by about 0.25˜0.35 mm with the same wiring cycle of the fan-out area.
In the drawings, the thickness of areas and layers may be exaggerated for clarity. In the drawings, the same reference numerals denote the same or similar structures, and therefore their detailed description is omitted. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solution of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other instance, well-known structures, material or operations are not shown or described in detail to avoid obscuring that main technical concept of the present disclosure.
Spatial relative terms such as “row”, “column”, “up”, “down”, “left” and “right” can be used in the disclosure to describe the relationship between one element or feature and another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to cover different orientations of devices in use or operation other than those depicted in the figures. For example, if the device in the figure is turned over, elements described as “under other elements or features” or “below other elements or features” will be oriented as “above other elements or features” and elements described as “to the left of other elements” will be oriented as “to the right of other elements”. Thus, the exemplary term “under” can cover both orientations of “above” and “under”, and the exemplary term “to the left of” can cover both orientations of “to the left” and “to the right”. Devices can be oriented in other ways (rotated by 90 degrees or in other orientations) and the spatial relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as “between two layers”, it may be the only layer between the two layers, or there may be one or more intermediate layers.
In the description of this specification, descriptions referring to the terms “one embodiment”, “another embodiment” and the like mean that a specific feature, structure, material or characteristic described in connection with this embodiment is included in at least one embodiment of this disclosure. In this specification, the schematic expressions of the above terms are not necessarily aimed at the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine different embodiments or examples and features of different embodiments or examples described in this specification without contradicting each other. In addition, it should be noted that in this specification, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
The above embodiments are only used for explanations rather than limitations to the present disclosure, the ordinary skilled person in the related technical field, in the case of not departing from the spirit and scope of the present disclosure, may also make various modifications and variations, therefore, all the equivalent solutions also belong to the scope of the present disclosure, the patent protection scope of the present disclosure should be defined by the claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/128764 | 10/31/2022 | WO |
