ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE HAVING THE SAME, AND METHOD THEREOF

Abstract

An array substrate includes a gate line, a data line, a pixel electrode, a first thin film transistor, and a second thin film transistor. The gate line includes a plurality of sub lines receiving a gate signal. The data line crosses the gate line. The pixel electrode is between adjacent sub lines. The first thin film transistor is electrically connected to a first sub line of the adjacent sub lines, the pixel electrode, and the data line. The second thin film transistor is electrically connected to a second sub line of the adjacent sub lines, the pixel electrode, and the data line. Therefore, an image display quality is improved.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

FIG. 1 is an exploded perspective view illustrating an exemplary display device in accordance with an exemplary embodiment of the present invention;

FIG. 2 is a plan view illustrating the exemplary light generating unit shown in FIG. 1;

FIG. 3 is a plan view illustrating the exemplary array substrate shown in FIG. 1;

to FIG. 4 is a cross-sectional view taken along line I-I′ shown in FIG. 3;

FIG. 5A is a plan view illustrating portion ‘A’ shown in FIG. 3;

FIG. 5B is a plan view illustrating portion ‘B’ shown in FIG. 3;

FIGS. 6A and 6B are plan views illustrating exemplary misaligned thin film transistors in accordance with other exemplary embodiments of the present invention;

FIGS. 7A and 7B are plan views illustrating exemplary thin film transistors in accordance with other exemplary embodiments of the present invention;

FIG. 8 is a plan view illustrating an exemplary array substrate of an exemplary display device in accordance with other exemplary embodiments of the present invention; and

FIG. 9 is a plan view illustrating an exemplary array substrate of an exemplary display device in accordance with other exemplary embodiments of the present invention.

Claims

1. An array substrate comprising: a gate line including a plurality of sub lines receiving a gate signal;a data line crossing the gate line;a pixel electrode between two adjacent sub lines;a first thin film transistor electrically connected to a first sub line of the two adjacent sub lines, the pixel electrode, and the data line; anda second thin film transistor electrically connected to a second sub line of the two adjacent sub lines, the pixel electrode, and the data line.

2. The array substrate of claim 1, further comprising a plurality of gate lines, wherein each of the gate lines comprises the first sub line, the second sub line, a third sub line, and a fourth sub line.

3. The array substrate of claim 2, wherein the fourth sub line of an n-th gate line of the plurality of gate lines is adjacent to the first sub line of an (n+1)-th gate line of the plurality of gate lines, wherein n is a natural number.

4. The array substrate of claim 3, further comprising a plurality of data lines crossing the sub lines to define a plurality of sub regions, wherein the pixel electrode covers three sub regions arranged in a longitudinal direction of the plurality of gate lines.

5. The array substrate of claim 4, further comprising a plurality of first thin film transistors and a plurality of second thin film transistors, wherein a first transistor of the first thin film transistors and a first transistor of the second thin film transistors are formed in a leftmost sub region of three sub regions between the first and second sub lines,a second transistor of the first thin film transistors and a second transistor of the second thin film transistors are formed in a central sub region of three sub regions between the second and third sub lines, anda third transistor of the first thin film transistors and a third transistor of the second thin film transistors are formed in a rightmost sub region of three sub regions between the third and fourth sub lines, andthe leftmost sub regions, the central sub regions, and the rightmost sub regions of the three sub regions between each pair of the sub lines are aligned in a direction of the data lines.

6. The array substrate of claim 5, further comprising a storage line between at least one pair of adjacent sub lines, wherein the storage line is formed from a substantially same layer as the sub lines and is formed substantially in parallel with the sub lines.

7. The array substrate of claim 6, further comprising a passivation layer disposed between the pixel electrode and the first and second thin film transistors.

8. The array substrate of claim 7, further comprising a connecting electrode under the passivation layer in each of the sub regions, wherein the connecting electrode is electrically connected to the pixel electrode through a contact hole in the passivation layer.

9. The array substrate of claim 8, wherein the storage line is adjacent to one of the sub lines.

10. The array substrate of claim 9, wherein the connecting electrode comprises: a first connecting electrode part in each of the sub regions corresponding to the storage line, the first connecting electrode part electrically connected to the first thin film transistor in at least one of the sub regions; anda second connecting electrode part facing the first connecting electrode, the second connecting electrode part electrically connected to the second thin film transistor in at least one of the sub regions.

11. The array substrate of claim 8, wherein the storage line is on a central portion between the adjacent sub lines.

12. The array substrate of claim 11, wherein the connecting electrode comprises: a first connecting electrode part in each of the sub regions corresponding to the storage line; andtwo second connecting electrode parts in at least one of the sub regions, the second connecting electrode parts electrically connected to the first and second thin film transistors.

13. The array substrate of claim 8, further comprising two storage lines between adjacent sub lines, wherein the storage lines are adjacent to the adjacent sub lines, respectively.

14. The array substrate of claim 13, further comprising two connecting electrodes corresponding to the two storage lines in each of the sub regions, wherein the connecting electrodes are electrically connected to the first and second thin film transistors, respectively.

15. The array substrate of claim 8, wherein the first and second thin film transistors are substantially symmetric with respect to a central line between adjacent sub lines.

16. An array substrate of claim 15, wherein the first thin film transistor comprises: a first active layer on a first sub line of the sub lines;a first source electrode extended from the data line and partially overlapping the first active layer; anda first drain electrode spaced apart from the first source electrode by a predetermined distance and partially overlapping the first active layer, the first drain electrode extended in a longitudinal direction of the data line and electrically connected to a first connecting electrode part of connecting electrode parts of the connecting electrode, andthe second thin film transistor comprises:a second active layer on a second sub line of the sub lines;a second source electrode extended from the data line and partially overlapping the second active layer; anda second drain electrode spaced apart from the second source electrode by a predetermined distance and partially overlapping the second active layer, the second drain electrode extended in a direction opposite to the longitudinal direction of the data line and electrically connected to a second connecting electrode part of the connecting electrode parts of the connecting electrode.

17. The array substrate of claim 16, wherein the first drain electrode crosses the first active layer, and the second drain electrode crosses the second active layer.

18. The array substrate of claim 1, wherein the first thin film transistor and the second thin film transistor receive a substantially same data signal from the data line and simultaneously charge the pixel electrode.

19. A display panel comprising: a first substrate including: a gate line including a plurality of sub lines receiving a gate signal;a data line crossing the gate line;a pixel electrode between two adjacent sub lines;a first thin film transistor electrically connected to a first sub line of the two adjacent sub lines and the pixel electrode; anda second thin film transistor electrically connected to a second sub line of the two adjacent sub lines and the pixel electrode;a second substrate facing the first substrate, the second substrate including a common electrode; anda liquid crystal layer including liquid crystals interposed between the first and second substrates.

20. A display device comprising: a display panel including: a first substrate including a gate line including a plurality of sub lines receiving a gate signal, a data line crossing the gate line, a pixel electrode between two adjacent sub lines, a first thin film transistor electrically connected to a first sub line of the two adjacent sub lines and the pixel electrode, and a second thin film transistor electrically connected to a second sub line of the two adjacent sub lines and the pixel electrode;a second substrate facing the first substrate, the second substrate including a common electrode; anda liquid crystal layer including liquid crystals interposed between the first and second substrates; anda backlight assembly under the display panel and supplying the display panel with light.

21. The display device of claim 20, wherein the backlight assembly comprises: a receiving container including a bottom plate and a sidewall defining a receiving space; anda light generating unit in the receiving space, the light generating unit including: a driving substrate generating a driving voltage; anda light emitting diode on the driving substrate generating the light based on the driving voltage.

22. The display device of claim 21, wherein the light emitting diode comprises a red light emitting diode generating red light, a green light emitting diode generating green light, and a blue light emitting diode generating blue light.

23. The display device of claim 22, wherein the red, green, and blue light emitting diodes generate the red, green, and blue lights in sequence.

24. The display device of claim 23, wherein a frequency of each of the red, green, and blue light emitting diodes is about 180 Hz.

25. A method of improving an image display quality of a display device, the method comprising: increasing a charging rate of a pixel electrode by simultaneously driving the pixel electrode with first and second thin film transistors each connected to the pixel electrode.

26. The method of claim 25, further comprising providing a gate line with first and second sub lines electrically connected to each other; crossing the first and second sub lines with a data line;providing the pixel electrode between the first and second sub lines;electrically connecting the first thin film transistor to the first sub line, the pixel electrode, and the data line;electrically connecting the second thin film transistor to the second sub line, the pixel electrode, and the data line;applying a gate signal to the first and second sub lines to simultaneously turn on the first and second thin film transistors; andapplying a data signal to the data line to simultaneously charge the pixel electrode with the first and second thin film transistors.