Embodiments of the present invention relate to an array substrate, a fabrication method thereof and a display device.
A thin film transistor liquid crystal display (TFT-LCD) has won wide concern over the years. At present, a high-resolution low-power TFT-LCD has become a focus of research and development.
The high-resolution low-power TFT-LCD needs to form a non-photosensitive resin structure of low dielectric constant.
Currently, since a planarization layer is manufactured, a large number of masks are required, and generally, the manufacturing of the structure shown in
Embodiments of the present invention provide an array substrate and a fabrication method thereof, and a display device, which can reduce the number of masks in the fabrication process, and can improve the production efficiency.
In one aspect, an embodiment of the present invention provides a fabrication method of an array substrate, comprising: preparing a base substrate, the base substrate comprising a pixel region and a gate on array region; forming a pattern including a gate electrode and a pattern of an active layer and forming a gate lead in the gate on array region on the base substrate, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; forming a pattern including a pixel electrode by a fifth patterning layer.
In another aspect, an embodiment of the present invention further provides an array substrate, comprising: a base substrate, including a pixel region and a gate on array region; a pattern including a gate electrode, a pattern of a gate insulating layer, a pattern of an active layer, a pattern including a source/drain electrode, a pattern of a planarization layer, and a pattern including a pixel electrode, which are formed on the base substrate sequentially.
In still another aspect, an embodiment of the present invention further provides a display device, comprising any array substrate described above.
In order to clearly illustrate the technical solution of the embodiments of the invention, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the invention and thus are not limitative of the invention.
In order to make objects, technical details and advantages of the embodiments of the invention apparent, the technical solutions of the embodiment will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the invention. It is obvious that the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.
In an embodiment of the present invention, a gate electrode and an active layer are formed simultaneously by one patterning process using a half tone mask and a lift off technology, which can reduce the number of masks, improve the production efficiency, and reduce the cost.
Exemplarily, it should be understood that, in the embodiment of the present invention, a patterning process refers to a process of forming a pattern including coating, exposing, developing and etching a photoresist or a photosensitive material, and stripping the photoresist or the photosensitive material. Of course, the process of forming a pattern in the embodiment of the present invention may also adopt other processes for forming the pattern such as printing, etc.
The photoresist or the photosensitive material is a kind of material sensitive to light; by taking the photoresist as an example, it can be divided into two types of negative photoresist and positive photoresist depending on a chemical reaction mechanism and a developing principle. That forms an insoluble substance after light irradiation is the negative photoresist; on the contrary, that is insoluble for some solvent but becomes a soluble substance after light irradiation is the positive photoresist. The embodiment of the present invention is illustrated by taking the positive photoresist as an example, that is, the photoresist per se is insoluble for a developing solution, and becomes a soluble substance after exposure so as to expose a structure on the substrate. Correspondingly, in the embodiment of the present invention, a photoresist completely removed region is formed on the substrate by a transparent region of a mask, a photoresist completely-retained region is formed on the substrate by an opaque region of the mask, and a photoresist half-retained region is formed on the substrate by a semi-transparent region of the mask.
Hereinafter, the embodiment of the present invention is illustrated in detail in conjunction with the drawings. Therein, in respective drawings, a left region of a dotted line is a pixel region of an array substrate, and a right region of the dotted line is a gate on array region, that is, a peripheral lead region for forming a circuit.
Exemplarily, a fabrication method of an array substrate according to an embodiment of the present invention, comprises:
Step 201: preparing a base substrate, the base substrate including a pixel region and a gate on array (GOA) region;
Step 202: forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead in the GOA region, by a first patterning process;
In this step, the pattern including the gate electrode and the pattern of the active layer are formed on the base substrate by the first pattering process using a half tone mask and a lift off process; in the half tone mask, a region corresponding to the pattern of the active layer is opaque, a region corresponding to the gate electrode in a pixel region and a region corresponding to a gate lead in the GOA region are both semi-transparent, and other regions are transparent.
Exemplarily, step 202 includes:
Firstly, forming a gate metal layer film, a first gate insulating layer film and an active layer film on the base substrate sequentially;
Then, coating photosensitive material on the active layer film;
Thirdly, exposing and developing the photosensitive material by using a half tone mask, to form a photosensitive material completely-retained region in a region corresponding to the pattern of the active layer, form a photosensitive material half-retained region in a region corresponding to the pattern including the gate electrode, and form a photosensitive material completely removed region in other regions.
Exemplarily, by taking the positive photoresist as an example, the positive photoresist is exposed and developed by using the half tone mask, and a region of the half tone mask corresponding to the pattern of the active layer is opaque, where the positive photoresist is completely-retained; a region of the half tone mask corresponding to the pattern including the gate electrode is semi-transparent, where the positive photoresist is partially retained; and other regions of the half tone mask corresponding to the base substrate are fully transparent, where the positive photoresist is completely removed.
Further, removing the active layer film, the first gate insulating layer film and the gate metal layer film in the photosensitive material completely removed region by a first etching;
Further, performing an ashing process to remove the photosensitive material in the photosensitive material half-retained region, and removing the active layer film and the gate insulating layer film in the photosensitive material half-retained region by a second etching, to obtain the pattern including the gate electrode;
Further, forming a second gate insulating layer film covering the entire base substrate by using a material for forming the first gate insulating layer film;
Finally, removing the second gate insulating layer film and the photosensitive material in the photosensitive material completely-retained region by using the lift off process, to obtain the pattern of the active layer.
Step 203: forming a pattern of a gate insulating layer on the base substrate on which the pattern including the gate electrode and the pattern of the active layer are formed, by a second patterning process;
Step 204: forming a pattern including a source/drain electrode on the base substrate on which the pattern of the gate insulating layer is formed, by a third patterning process;
Step 205: forming a pattern of a planarization layer on the base substrate on which the pattern of the source/drain electrode is formed, by a fourth patterning layer;
Step 206: forming a pattern including a pixel electrode, a pattern of a first passivation layer and a pattern of a common electrode sequentially on the base substrate on which the pattern of the planarization layer is formed, by a patterning process.
Exemplarily, a thickness of the first gate insulating layer film is same as that of the second gate insulating layer film, so that the formed pattern of the gate insulating layer has no step.
Exemplarily, the fabrication method of the array substrate according to the embodiment of the present invention further comprises: forming a pattern of an ohmic contact layer, after the forming a pattern of the active layer.
Exemplarily, the forming a pattern of an ohmic contact layer includes:
Forming a prepattern of the pattern of the ohmic contact layer that is identical with, i.e., conformal with the pattern of the active layer by the first patterning process, while forming the pattern of the active layer; and
Etching the prepattern of the pattern of the ohmic contact layer to form the pattern of the ohmic contact layer, while forming the pattern including the source/drain electrode.
Next, the steps of the fabrication method of the array substrate according to the embodiment of the present invention are described in detail in conjunction with
Here, it should be noted that
Exemplarily, step 202 includes;
Depositing a gate metal layer film 21 on a base substrate 1, wherein the gate metal layer film may be made from metal materials such as aluminum, copper, chromium or molybdenum, or an alloy thereof. Then, sequentially depositing a first gate insulating layer film 31, which exemplarily may be made from SiNX, and an active layer film 41, as shown in
Thereafter, coating a photosensitive material 6 such as a photoresist or a photosensitive resin on the ohmic contact layer film 51, exposing and developing the photoresist material by using a half tone mask, to form a photosensitive material completely-retained region in a region corresponding to the pattern of the active layer and the pattern of the ohmic contact layer, form a photosensitive material half-retained region in a region corresponding to the pattern including the gate electrode, and form a photosensitive material completely removed region in other regions;
Here, by taking the positive photoresist as an example, the photosensitive material is exposed and developed by using the half tone mask, and a region of the half tone mask corresponding to the pattern of the active layer and the pattern of the ohmic contact layer is opaque, where the positive photoresist is completely-retained; a region of the half tone mask corresponding to the pattern including the gate electrode is semi-transparent, where the positive photoresist is partially retained; and other regions of the half tone mask corresponding to the base substrate are transparent, where the positive photoresist is completely removed;
Thereafter, by using the half tone mask, in which a region corresponding to a pattern of an active layer 4 to be formed is opaque, a region corresponding to the to-be-formed gate electrode 2 of the pixel region and a region corresponding to the gate lead in the GOA region are both semi-transparent, and the other regions are transparent, and exposing and developing the photoresist or the photoresist resin by using the half tone mask, to obtain the structure shown in
Then, performing an etching, and removing the gate metal layer film 21, the first gate insulating layer film 31, the active layer film 41, and the ohmic contact layer film 51 in the photosensitive material (the photoresist or the photosensitive resin) completely removed region by an etching, to form the structure shown in
Next, performing an ashing process on the photosensitive material (the photoresist or the photosensitive resin), to remove the photosensitive material in the photosensitive material half-retained region, so as to obtain the structure shown in
Thereafter, further forming a second gate insulating layer film 32 covering the entire substrate by using a material same as that for forming the first gate insulating layer film, and removing the second gate insulating layer film and the photosensitive material in the photosensitive material completely-retained region by using the lift off process, to obtain the pattern of the active layer.
Exemplarily, here, the photoresist or the photosensitive resin is not stripped, i.e., the photoresist or the photosensitive resin on the active layer film 4 is reserved, and the second gate insulating layer film 32 covering the entire substrate is further deposited by plasma enhanced chemical vapor deposition (PECVD), to obtain the structure shown in
At that time, a prepattern of the pattern of the ohmic contact layer is formed, and is identical with, i.e., conformal with the pattern of the active layer. For the prepattern of the pattern of the ohmic contact layer, when the pattern of the source/drain electrode is formed subsequently, a pattern of an ohmic contact layer 5 is formed by etching off the ohmic contact layer film 51 in a channel region. Exemplarily, when etching a source/drain metal film subsequently, a metal layer in a source/drain region and the GOA region is firstly etched by wet etching, and then the ohmic contact layer film 51 in the channel region is etched by dry etching, to form the pattern of the source/drain electrode and the pattern of the ohmic contact layer.
Obviously, in this step, the gate electrode and the active layer are formed at the same time by one mask, and only by one patterning process using the half tone mask, which as compared with the prior art, spares one mask, saves costs, and improves production efficiency.
Exemplarily, step 203 includes:
On the base substrate on which the pattern including the gate electrode 2 and the pattern 4 of the active layer are formed, patterning the second gate insulating layer film 32 deposited, i.e., exposing and developing, and etching by using a mask, to form the pattern of the gate insulating layer, which includes a via hole. Therein, the via hole is formed at a position of the gate insulating layer 3 corresponding to the gate lead in the GOA region, as shown in
Exemplarily, step 204 includes:
Further depositing a source/drain metal film on the base substrate on which the pattern of the gate insulating layer 3 is formed;
Coating photosensitive material on the source/drain metal film;
Exposing and developing the photosensitive material by using a mask, to form the photosensitive material completely removed region corresponding to a gate lead in a GOA region and corresponding to a channel region;
Etching the source/drain metal film and the ohmic contact layer film in the photosensitive material completely removed region;
Removing the remaining photosensitive material, to form the pattern of the source/drain electrode and the pattern of the ohmic contact layer, to form the source/drain electrode 7 and a channel, wherein the pattern including the source/drain electrode formed in the GOA region is connected to the gate lead through a via hole in the pattern of the gate insulating layer 3, as shown in
Exemplarily, after the step 204, the method further comprises: forming a pattern of a second passivation layer 8 on the substrate on which the pattern of the source/drain electrode is formed, includes:
Further depositing a layer of non-metal material on the base substrate, such as silicon nitride with a thickness of 300-800 Å, to form the pattern of the second passivation layer 8, which covers the entire base substrate, i.e., being formed above the pattern of the gate insulating layer 3 and the pattern including the source/drain electrode.
Here, the pattern of the second passivation layer 8 is formed in order to prevent an organic resin solvent component contained in an overflow gas upon heating the planarization layer subsequently from penetrating the active layer, thereby increasing defects on a surface of the active layer, and affecting characteristics and stability of the TFT.
Exemplarily, step 205: forming a pattern of a planarization layer on the base substrate on which the pattern of the source/drain electrode is formed, includes:
Coating a resin material, e.g., an organic resin, on the base substrate on which the pattern including the source/drain electrode 7 is formed, forming a pattern of a planarization layer 9 by a patterning process, and the planarization layer 9 is provided with via holes in a region corresponding pixel region and GOA region, as shown in
Exemplarily, step 206: forming a pattern including a pixel electrode, a pattern of a first passivation layer and a pattern of a common electrode sequentially on the base substrate on which the pattern of the planarization layer is formed, includes:
Depositing a layer of transparent conductive material film, which may be made of a material such as ITO, on the base substrate on which the pattern of the planarization layer 9 is formed, and patterning the same to form a pattern of a pixel electrode 10, as shown in
Depositing a layer of non-metal film, which may be made of material such as SiNX, on the base substrate on which the pattern of the pixel electrode 10 is formed, and patterning the same to form a pattern of a first passivation layer 11, which is provided with a via hole, as shown in
Further depositing a layer of transparent conductive material film, with a thickness of 500˜800 Å, and patterning the same to form a pattern of a common electrode 12, as shown in
It can be seen from the above fabrication method of the array substrate that as compared with the prior art in which the fabrication of the gate electrode and the active layer each requires one mask, the fabrication of the gate electrode and the active layer in the embodiment of the present invention only requires one mask, which reduces the number of patterning processes, effectively saves the cost, and improves the production efficiency.
An embodiment of the present invention further provides an array substrate. The array substrate is fabricated by using the above method, and its structure is shown in
Exemplarily, in a pixel region, the pattern of the gate insulating layer 3 includes a pattern of a first gate insulating layer 31 formed by a first gate insulating layer film and a pattern of a second gate insulating layer 32 formed by a second gate insulating layer film; in a GOA region, the pattern of the gate insulating layer 3 is formed by the second gate insulating layer film 32, and the first gate insulating layer film and the second gate insulating layer film are same in thickness, and the pattern of the first gate insulating layer 31 is conformal with the pattern of the active layer 4.
Exemplarily, the array substrate further comprises: a pattern of an ohmic contact layer 5 formed above the pattern of the active layer 4 and below the pattern including the source/drain electrode 7.
Exemplarily, the array substrate further comprises: a pattern of a first passivation layer 8 formed above the pattern including the source/drain electrode 7 and below a planarization layer 9.
Exemplarily, the array substrate further comprises: a pattern of a second passivation layer 11 formed above the pattern including the pixel electrode 10, as shown in
An embodiment of the present invention further provides a display device, the display device comprising the array substrate described above.
In the array substrate and the fabrication method thereof and the display device provided by the embodiments of the present invention, the gate electrode and the active layer are formed on the substrate by one patterning process using a half tone mask. As compared with the prior art in which the fabrication of the gate electrode and the active layer requires two masks, while in the embodiment of the present invention, the fabrication of the gate electrode and the active layer only needs one mask, which reduces the number of patterning processes, efficiently saves the cost, and improves production efficiency.
The foregoing implementation modes are only illustrative of the present invention, rather than limitative of the present invention. One person ordinarily skilled in the art can make various changes or modifications to the present invention without departing from the spirit and scope of the invention. Thus, all equivalent technical solutions also belong to the scope of the present invention, which is defined by the claims.
The present application claims priority of Chinese Patent Application No. 201310485935.9 filed on Oct. 16, 2013, the disclosure of which is incorporated herein by reference in its entirety as part of the present application.
Number | Date | Country | Kind |
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201310485935.9 | Oct 2013 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2014/086081 | 9/5/2014 | WO | 00 |