Array substrate for liquid crystal display device and method of fabricating the same

Abstract

An array substrate for a liquid crystal display device, includes: a gate line and a data line on a substrate, the data line crossing the gate line to define a pixel region; an insulating layer between the gate line and the data line; a switching element adjacent to a crossing of the gate line and the data line; a pixel electrode connected to the switching element, the pixel electrode disposed in the pixel region; and a first buffer pattern at a first side of one of the gate line and the date line and overlapped with the other one of the gate line and the date line, the first buffer pattern being disposed at the same layer as the one of the gate line and the date line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a schematic cross-sectional view of an LCD device according to the related art;

FIG. 2 is a schematic plan view of an array substrate with respect to one pixel region according to the related art;

FIG. 3 is an expanded plan view of “III” of FIG. 2;

FIG. 4 is a schematic cross-sectional view taken along a line of “IV-IV” in FIG. 3;

FIG. 5 is a schematic plan view of a crossing portion of two metal lines of an array substrate including buffer patterns according to a first embodiment of the present invention;

FIG. 6 is a schematic plan view of a crossing portion of two metal lines of an array substrate including buffer patterns according to a second embodiment of the present invention;

FIG. 7 is a schematic plan view of an array substrate for an LCD device including first and second buffer patterns with respect to one pixel region according to a first embodiment of the present invention;

FIG. 8 is a schematic plan view of an array substrate for an LCD device including first and second buffer patterns with respect to one pixel region according to a second embodiment of the present invention;

FIGS. 9A, 9B, 9C and 9D are schematic cross-sectional views of an array substrate for an LCD device taken along a line of “IX-IX” in FIG. 7 in accordance with manufacturing steps according to an embodiments of the present invention; and

FIGS. 10A, 10B, 10C and 10D are schematic cross-sectional views of an array substrate for an LCD device taken along a line of “X-X” in FIG. 7 in accordance with manufacturing steps according to an embodiments of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to embodiments of the present invention, example of which is illustrated in the accompanying drawings. Wherever possible, similar reference numbers will be used throughout the drawings to refer to the same or like parts.

Hereinafter, exemplary embodiments according to the present invention will be explained as follows.

FIG. 5 is a schematic plan view of a crossing portion of two metal lines of an array substrate including buffer patterns according to a first embodiment of the present invention. FIG. 6 is a schematic plan view of a crossing portion of two metal lines of an array substrate including buffer patterns according to a second embodiment of the present invention.

In FIG. 5, a first metal line 102 is formed along a first direction and a second metal line 110 is formed along a second direction crossing the first direction. Although not shown, an insulating layer is disposed between the first metal line 102 and the second metal line 110. Further, first and second buffer patterns 106 and 108 are formed at the same layer as the first metal line 102. Here, the first buffer pattern 106 has a bar shape spaced apart from the first metal line 102 and along the first direction. The second buffer pattern 108 extends from the first metal line 102. For example, the second buffer pattern 108 has a square pattern as shown in FIG. 5. Specifically, the size of the second buffer pattern 108 is selected from a range so that the main portion of the second buffer pattern 108 could be covered by the second metal line 110.

Alternatively, in FIG. 6, first and second buffer patterns 152 and 154 extend from a first metal line 150 along the second direction so as to be overlapped with the second metal line 160. For example, the first buffer pattern 152 may have a triangular shape and the second buffer pattern 154 may have a square shape. In FIG. 6, the first and second buffer patterns 152 and 154 are symmetrically disposed with respect to a central portion of the second metal line 160. However, in order to reduce the step difference of the first metal line 150, the first and second metal lines 150 and 160 may be disposed at the other positions within the range so that the second metal line 160 could cover the first and second buffer patterns 152 and 154. That is, each of the first and second buffer patterns 150 and 160 can be selected from various shapes to reduce the step difference in the first metal line 150. In addition, although two buffer patterns are used in the illustrated embodiments, any number of buffer patterns can be used to reduce the step difference. For example, a single buffer pattern can be used at one side of the second metal line 160, or more than two buffer patterns can be used at one side or two sides of the second metal line 160.

Anyway, what the buffer patterns according to the present invention are disposed at both sides of an upper metal line that overlapped with a lower metal line may be proper in order to obtain effects according to the present invention.

Further, what the etchant pools at the crossing of the first and second metal lines 150 and 160 is effectively prevented by the first and second buffer patterns 152 and 154.

FIG. 7 is a schematic plan view of an array substrate for an LCD device including first and second buffer patterns with respect to one pixel region according to a first embodiment of the present invention. FIG. 8 is a schematic plan view of an array substrate for an LCD device including first and second buffer patterns with respect to one pixel region according to a second embodiment of the present invention.

In FIGS. 7 and 8, a gate line 202 is formed along a first direction on a substrate 200. A data line 220 is formed along a second direction crossing the first direction to define a pixel region “P.” Although not shown, a gate insulating layer is interposed between the gate and data lines 202 and 220. A thin film transistor “T,” which includes a gate electrode 204, a semiconductor layer 214, a source electrode 216 and a drain electrode 218, is adjacent to the crossing of the gate and data lines 202 and 220. A pixel electrode 226 is connected to the thin film transistor “T” in the pixel region “P.” Further, the first and second buffer patterns 206 and 208 (of FIG. 7) or 306 and 308 (of FIG. 8) are formed at the same layer as the gate line 202.

In FIG. 7, the first buffer pattern 206 has a bar shape spaced apart from the gate line 202 and along a direction parallel to the first direction. The second buffer pattern 208 extends from the gate line 202 along the second direction so that the main portion of the second buffer pattern 208 is overlapped with the data line 220.

Alternatively, in FIG. 8, the first and second buffer patterns 306 and 308 extend from the gate line 202. Here, each of the first and second buffer patterns 306 and 308 extends toward a direction opposite to each other. Specifically, the first buffer pattern 306 has a triangular shape and the second buffer pattern 308 has a square shape. However, the shapes of the first and second buffer patterns 306 and 308 may be changed into different types.

Hereinafter, a manufacturing process of an array substrate for an LCD device according to an embodiment of the present invention will be explained as follows.

FIGS. 9A, 9B, 9C and 9D are schematic cross-sectional views of an array substrate for an LCD device taken along a line of “IX-IX” in FIG. 7 in accordance with manufacturing steps according to an embodiments of the present invention. FIGS. 10A, 10B, 10C and 10D are schematic cross-sectional views of an array substrate for an LCD device taken along a line of “X-X” in FIG. 7 in accordance with manufacturing steps according to an embodiments of the present invention.

In FIGS. 9A and 10A, a substrate 200 includes a pixel region “P” and a switching region “S.” A conductive metallic material is deposited the substrate 200 and is patterned to form a gate line 202 and a gate electrode 204. Although not shown, the gate line 202 is formed along a first direction and the gate electrode 204 is disposed in the switching region “S.”

Further, a first buffer pattern 206 is formed to be spaced from the gate line 202, and a second buffer pattern 208 extends from the gate line 202. Although not shown, the first buffer pattern 206 has a bar shape parallel to the first direction, and the second buffer pattern 208 has a square shape in a plan view. Specifically, the first and second buffer patterns 206 and 208 are disposed in a crossing portion of the gate line 202 and a data line that will be formed later.

However, the first and second buffer patterns 206 and 208 may be changed into various shapes.

The conductive metallic material is selected from aluminum (Al), aluminum alloy such as aluminum neodymium (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo) and titanium (Ti) and the like.

Next, a gate insulating layer is formed by depositing an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx) on the gate line 202, the gate electrode 204, and the first and second buffer patterns 206 and 208.

In FIGS. 9B and 10B, a semiconductor layer 214 is formed by sequentially depositing an intrinsic amorphous silicon (a-Si: H) and a doped amorphous silicon (n+ a-Si: H) on the gate insulating layer. Specifically, the intrinsic amorphous silicon (a-Si: H) and the doped amorphous silicon (n+ a-Si: H) are patterned into an active layer 214a and an ohmic contact layer 214b, respectively. That is, the semiconductor layer 214 includes the active layer 214a and the ohmic contact layer 214b.

Next, a data line 220, a source electrode 216 and a drain electrode 218 are formed by depositing and patterning a conductive metallic material such as the mentioned conductive metallic material on the semiconductor layer 214. Specifically, the data line 220 is formed along a second direction crossing the first direction, the source electrode 216 extends from the data line 220, and the drain electrode 218 is spaced apart from the source electrode 216. A portion of the active layer 214a is exposed between the source and drain electrode 216 and 218. The gate electrode 204, the semiconductor layer 214, the source electrode 216 and the drain electrode 218 constitute a thin film transistor “T.”

It is noted that the data line 220 crosses the gate line 202 and covers the first and second buffer patterns 206 and 208. Therefore, the step difference in the gate line 202 can be reduced by the first and second buffer patterns 206 and 208. Accordingly, the disconnection defect from the data line 220 can be prevented.

In FIGS. 9C and 10C, a passivation layer 222 is formed by depositing (or coating) and patterning an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as benzocyclobutene (BCB) or acrylic resin on the thin film transistor “T.” Here, the passivation layer 222 includes a drain contact hole 224 that exposes a portion of the drain electrode 218 through the patterning process.

In FIGS. 9D and 10D, a pixel electrode 226 is formed by depositing and patterning a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO) on the passivation layer 222 in the pixel region “P.” Here, the pixel electrode 226 is connected to the drain electrode 218 via the drain contact hole 224.

The first and second buffer patterns 206 and 208 according to an embodiment of the present invention can prevent disconnection defect at the crossing of two metal lines such as gate and data lines 202 and 220, thereby improving productivity and reducing the manufacturing cost.

Although the above embodiments use a bottom-gate TFT structure as an example and apply the present invention to prevent the disconnection defect of the date line due to the step difference of the gate line, it should be noted that the present invention can also be applied to any crossing line structure. For example, the present invention can also be applied to a top-gate TFT structure to prevent the disconnection defect of the gate line due to the step difference of the date line, or any other crossing line structure to prevent the disconnection defect of the upper line due to the step difference of the lower line.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. An array substrate for a liquid crystal display device, comprising: a gate line and a data line on a substrate, the data line crossing the gate line to define a pixel region;an insulating layer between the gate line and the data line;a switching element adjacent to a crossing of the gate line and the data line;a pixel electrode connected to the switching element, the pixel electrode disposed in the pixel region; anda first buffer pattern at a first side of one of the gate line and the date line and overlapped with the other one of the gate line and the date line, the first buffer pattern being disposed at the same layer as the one of the gate line and the date line.

2. The array substrate according to claim 1, wherein a second buffer pattern at a second side of the one of the gate line and the date line opposite to the first side and overlapped with the other one of the gate line and the date line, the first and second buffer patterns being disposed at the same layer as the one of the gate line and the date line.

3. The array substrate according to claim 2, wherein the first buffer pattern has a bar shape parallel to and spaced apart from the one of the gate line and the date line, and the second buffer pattern extends from the one of the gate line and the date line.

4. The array substrate according to claim 3, wherein the second buffer pattern is closer than the first buffer pattern to the switching element.

5. The array substrate according to claim 3, wherein the second buffer pattern has one of a tetragonal shape and a triangular shape.

6. The array substrate according to claim 2, wherein the first and second buffer patterns and the one of the gate line and the date line are substantially coplanar.

7. The array substrate according to claim 2, wherein the first and second buffer patterns and the one of the gate line and the date line are made of a substantially same material.

8. The array substrate according to claim 2, wherein the first buffer pattern extends from the first side of the one of the gate line and the date line, and the second buffer pattern extends from the second side of the gate line.

9. The array substrate according to claim 8, wherein the first and second buffer patterns are symmetrically disposed with respect to a central portion of the other one of the gate line and the date line.

10. A method of fabricating an array substrate for a liquid crystal display device, comprising: forming one of a gate line and a date line, and a first buffer pattern on a substrate, the first buffer pattern being formed at a first side of the one of the gate line and the date line;forming an insulating layer on the one of the gate line and the date line, and the first buffer pattern;forming the other one of the gate line and the date line on the insulating layer, the other one of the gate line and the date line crossing the one of the gate line and the date line to define a pixel region, the other one of the gate line and the date line being overlapped with the first buffer pattern;forming a switching element connected to the gate line and the data line adjacent to a crossing of the gate line and the data line; andforming a pixel electrode connected to the switching element, the pixel electrode being disposed in the pixel region.

11. The method according to claim 10, further comprising forming a second buffer pattern at a second side of the one of the gate line and the date line opposite to the first side, the other one of the gate line and the date line being overlapped with the second buffer pattern, wherein the step of forming the insulating layer includes forming the insulating layer on the second buffer pattern.

12. The method according to claim 11, wherein the steps of forming the one of the gate line and the date line, the first buffer pattern and the second buffer pattern include forming the first buffer pattern to have a bar shape parallel to and spaced apart from the one of the gate line and the date line, and forming the second buffer pattern to extend from the one of the gate line and the date line.

13. The method according to claim 12, wherein the steps of forming the one of the gate line and the date line, the first buffer pattern and the second buffer pattern include forming the second buffer pattern to have one of a tetragonal shape and a triangular shape.

14. The method according to claim 11, wherein the steps of forming the one of the gate line and the date line, the first buffer pattern and the second buffer pattern include forming the first and second buffer patterns and the one of the gate line and the date line to be substantially coplanar.

15. The method according to claim 11, wherein the steps of forming the one of the gate line and the date line, the first buffer pattern and the second buffer pattern include forming the first and second buffer patterns and the one of the gate line and the date line of a substantially same material.

16. The method according to claim 11, wherein the steps of forming the one of the gate line and the date line, the first buffer pattern and the second buffer pattern include: forming the first buffer pattern to extend from the first side of the one of the gate line and the date line; andforming the second buffer pattern to extend from the second side of the one of the gate line and the date line.

17. The method according to claim 16, wherein the steps of forming the one of the gate line and the date line, the first buffer pattern and the second buffer pattern include forming the first and second buffer patterns to be symmetrical to a central portion of the other one of the gate line and the date line.

18. A crossing line structure of a display device, comprising: a first line on a substrate;an insulating layer on the first line;a second line on the insulating layer, the second line crossing the first line; anda first buffer pattern at a first side of the first line and overlapped with the second line;

19. The crossing line structure according claim 18, further comprising a second buffer pattern at a second side of the first line opposite to the first side and overlapped with the second line.

20. The crossing line structure according claim 19, wherein the first and second buffer patterns are disposed at the same layer as the first line.

21. The crossing line structure according claim 20, wherein the first and second buffer patterns and the first line are substantially coplanar.

22. The crossing line structure according claim 20, wherein the first and second buffer patterns and the first line are made of a substantially same material.

23. The crossing line structure according claim 19, wherein the first buffer pattern has a bar shape parallel to and spaced apart from the first line, and the second buffer pattern extends from the first line.

24. The crossing line structure according claim 23, wherein the second buffer pattern has one of a tetragonal shape and a triangular shape.

25. The crossing line structure according claim 19, wherein the first buffer pattern extends from the first side of the first line, and the second buffer pattern extends from the second side of the first line.

26. The crossing line structure according claim 25, wherein the first and second buffer patterns are symmetrically disposed with respect to a central portion of the second line.