BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is an exploded perspective view showing a liquid crystal display device according to the related art.
FIG. 2 is an equivalent circuit diagram representing a liquid crystal display device according to the related art.
FIG. 3 is a cross-sectional view taken along a line “III-III” of FIG. 1.
FIG. 4 is a schematic cross-sectional view showing a thin film transistor of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.
FIGS. 5A and 5B are cross-sectional views showing a method of forming a gate insulating layer of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a solution used for a gate insulating layer of an array substrate for a liquid crystal display device according to a second embodiment of the present invention.
FIGS. 7A to 7D are cross-sectional views showing a method of forming an array substrate for a liquid crystal display device according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, similar reference numbers will be used to refer to the same or similar parts.
An array substrate for a liquid crystal display device according to the present invention includes a gate insulating layer benefiting a property of a thin film transistor and a display quality of the liquid crystal display device.
FIG. 4 is a schematic cross-sectional view showing a thin film transistor of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.
In FIG. 4, a thin film transistor (TFT) “T” includes a gate electrode 102 on a substrate 100, a gate insulating layer 104 on the gate electrode 102, a semiconductor layer 106 on the gate insulating layer 104 over the gate electrode 102, and source and drain electrodes 108 and 110 on the semiconductor layer 106. The gate insulating layer 104 may include a particle and a matrix, preferably a nano-particle 104a of an inorganic material and an organic matrix 104b of an organic material. The organic matrix 104b surrounds the nano-particle 104a and the nano-particle 104a is dispersed in the organic matrix 104b. The gate insulating layer 104 may be obtained through steps of forming a composite precursor film of a core-shell structure and curing the composite precursor film by, for example, heat or light. In addition, an active layer may include an active layer 106a of intrinsic amorphous silicon and an ohmic contact layer 106b of impurity-doped amorphous silicon. The source and drain electrodes 108 and 110 are shown as spaced apart from each other.
Since the gate insulating layer 104 preferably has a dielectric constant greater than about 6, for example within a range of about 6 to about 10, a property of the TFT “T” is improved and a pixel voltage variation ΔVp of the LCD device is reduced. The pixel voltage variation ΔVp may be expressed as an equation (1).
ΔVp=Cgd·(Vgh−Vgl)/(Cst+Cgd+CLC) (1)
where Cgd is a capacitance between the gate electrode 102 and the drain electrode 110, Cst is a capacitance of the storage capacitor, CLC is a capacitance of the liquid crystal layer, Vgh is a high level voltage of a gate signal and Vgl is a low level voltage of the gate signal.
Since the storage capacitor includes the gate insulating layer 104 as a dielectric layer between the pixel electrode (not shown) and the common electrode (not shown), the capacitance Cst of the storage capacitor increases as the dielectric constant of the gate insulating layer 104 increases. In addition, as the capacitance Cst of the storage capacitor increases, the pixel voltage variation ΔVp decreases according to the equation (1). Even though the capacitance Csd also increases according to increase of the dielectric constant of the gate insulating layer 104, the pixel voltage variation ΔVp does not increase because the capacitance Csd is negligibly smaller than the capacitance Cst. As a result, the pixel voltage variation ΔVp is reduced and the display quality is improved due to the gate insulating layer 104 including the nano-particle 104a and the organic matrix 104b.
Further, when a gate signal is applied to the gate electrode 102 of the TFT “T” having an inverted staggered structure, a channel is promptly generated in the semiconductor layer 106 due to the gate insulating layer 104. Accordingly, a property of the TFT “T” is improved.
Moreover, since the gate insulating layer 104 may be coated on the gate electrode 104, a forming step of the gate insulating layer 104 is simplified and a thickness uniformity is improved. As a result, a property of the TFT “T” is further improved.
FIGS. 5A and 5B are cross-sectional views showing a method of forming a gate insulating layer of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.
In FIG. 5A, a coating, for example a composite precursor film 160, is formed on a substrate 100 by a coating method. The composite precursor film 160 may include particles 150 each having a core-shell structure of a core 150a and a shell 150b surrounding the core 150a. The core 150a may include an inorganic material and the shell 150b may include an organic material. The composite precursor film 160 may have a dielectric constant over about 12. The core 150a may be fabricated through a polymerization method of an additive such as a sol-gel method. In addition, the core 150a may include one of barium strontium titanate, barium zirconate titanate, lead zirconate titanate, strontium titanate, barium titanate, barium magnesium fluoride, bismuth titanate, strontium bismuth tantalate, strontium bismuth tantalate niobate and a metal oxide material such as zirconium oxide (ZrO2), aluminum oxide (Al2O3), magnesium oxide (MgO), calcium oxide (CaO), zirconium silicate (ZrSiO4), hafnium silicate (HfSiO4), yttrium oxide (Y2O3), hafnium oxide (HfO2), strontium oxide (SrO), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), barium oxide (BaO) and titanium oxide (TiO2). After particles having the core-shell structure are dispersed in a solvent, the solvent is coated on the substrate 100.
In FIG. 5B, the coating 160 (of FIG. 5A) may be cured, for example, by one of heat and light. If the solvent is evaporated and the shell 150b melts during the curing step, the composite precursor film 160 (of FIG. 5A) is planarized to become the gate insulating layer 104 preferably including a nano-particle 104a and an organic matrix 104b surrounding the nano-particle 104a. The nano-particle 104a and the organic matrix 104b may correspond to the core 150a and the shell 150b, respectively. As a result, the gate insulating layer 104 may have a dielectric constant within a range of about 6 to about 10.
In the array substrate according to the first embodiment of the present invention, the gate insulating layer having a relatively high dielectric constant may be formed using a composite precursor film including particles having a core-shell structure. In an array substrate according to another embodiment, a gate insulating layer may be formed by coating an organic polymer solution where nano-particles are dispersed.
FIG. 6 is a cross-sectional view showing an organic polymer solution used for a gate insulating layer of an array substrate for a liquid crystal display device according to a second embodiment of the present invention.
In FIG. 6, an organic polymer melts in a solvent to constitute an organic polymer solution 202 in a vessel 200. A particle, preferably a nano-particle 204 such as zirconium oxide (ZrO2) having a dielectric constant over about 8 may be dispersed in the organic polymer solution 202. The organic polymer may include a material obtainable through a sol-gel method. For example, the organic polymer may include one of single polymer and copolymer such as siloxane polymer, polyacrylate-polyimide and polyester. In addition, the nano-particle 204 may include one of barium strontium titanate, barium zirconate titanate, lead zirconate titanate, strontium titanate, barium titanate, barium magnesium fluoride, bismuth titanate, strontium bismuth tantalate, strontium bismuth tantalate niobate and a metal oxide material such as zirconium oxide (ZrO2), aluminum oxide (Al2O3), magnesium oxide (MgO), calcium oxide (CaO), zirconium silicate (ZrSiO4), hafnium silicate (HfSiO4), yttrium oxide (Y2O3), hafnium oxide (HfO2), strontium oxide (SrO), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), barium oxide (BaO) and titanium oxide (TiO2)
The nano-particle 204 may be dispersed in the organic polymer solution 202 using one of a physical force and a chemical force. The organic polymer solution 202 having the nano-particle 204 may be stirred using a shear force in a dispersion step using a physical force, while a chemical bond may be induced in a dispersion step using a chemical force. After the organic polymer solution 202 where the nano-particle 204 is dispersed is prepared, a gate insulating layer having a dielectric constant within a range of about 6 to about 10 is formed on a substrate having a gate electrode by coating the organic polymer solution 202 having the nano-particle 204. The gate insulating layer may include an organic matrix and a nano-particle corresponding to the organic polymer and the nano-particle of the organic polymer solution 202, respectively.
FIGS. 7A to 7D are cross-sectional views showing a method of forming an array substrate for a liquid crystal display device according to an embodiment of the present invention.
In FIG. 7A, a gate electrode 302 and a gate line “GL” connected to the gate electrode 302 are formed on a substrate 300 by depositing and patterning a metallic material such as aluminum (Al), aluminum (Al) alloy, chromium (Cr), copper (Cu), titanium (Ti), tungsten (W) and molybdenum (Mo). A gate insulating layer 304 is formed on the gate electrode 302 and the gate line “GL.” The gate insulating layer 304 includes a nano-particle 304a and an organic matrix 304b surrounding the nano-particle 304a.
As illustrated in the first embodiment, the gate insulating layer 304 may be formed using a composite precursor film. The composite precursor film may be formed on the gate electrode 302 and the gate line “GL” by coating and curing a solvent having particles each having a core-shell structure of a core and a shell. If the solvent is evaporated and the shell melts during the curing step, a gate insulating layer 304 including the nano-particle 304a and the organic matrix 304b may be formed on the gate electrode 302 and the gate line “GL.” The nano-particle 304a and the organic matrix 304b correspond to the core and shell, respectively.
In addition, as illustrated in the second embodiment, the gate insulating layer 304 may be formed using an organic polymer solution where a nano-particle such as zirconium oxide (ZrO2) is dispersed. The gate insulating layer 304 may be formed by coating the organic polymer solution including an organic polymer and a nano-particle on the gate electrode 302 and the gate line “GL.” The nano-particle 304a and the organic matrix 304b correspond to the nano-particle and the organic polymer of the organic polymer solution, respectively.
Since the gate insulating layer 304 may have a dielectric constant within a range of about 6 and about 10, a capacitance of the storage capacitor increases and a pixel voltage variation is reduced. As a result, a display quality of the LCD device is improved. Further, a property of the TFT such as a response time is improved. Moreover, since the gate insulating layer 304 is formed using a coating method instead of a deposition method, a fabrication process is simplified.
In FIG. 7B, a semiconductor layer 306 may be formed on the gate insulating layer 304 by sequentially depositing and patterning intrinsic amorphous silicon (a-Si:H) and impurity-doped amorphous silicon (n+a-Si:H). The semiconductor layer 306 includes an active layer 306a of the amorphous silicon (a-Si:H) and an ohmic contact layer 306b of the impurity-doped amorphous silicon (n+a-Si:H).
In FIG. 7C, source and drain electrodes 308 and 310 may be formed on the semiconductor layer 306 by coating and patterning at least one of a metallic material such as aluminum (Al), aluminum (Al) alloy, chromium (Cr), copper (Cu), titanium (Ti), tungsten (W) and molybdenum (Mo). A data line (not shown) may be simultaneously formed on the substrate 300 having the semiconductor layer 306. The source and drain electrodes 308 and 310 are spaced apart form each other, and the data line crosses the gate line “GL” to define a pixel region “P.” In addition, a metal pattern 312 having an island shape may be formed on the gate insulating layer 304 over the gate line “GL” simultaneously. Accordingly, a portion of the gate line “GL” and the metal pattern 312 function as first and second capacitor electrodes to form a storage capacitor “Cst” with the gate insulating layer 304. Subsequently, the ohmic contact layer 306b exposed between the source and drain electrodes 308 and 310 may be removed to expose the active layer 306a.
In FIG. 7D, a passivation layer 314 having a drain contact hole 316 and a storage contact hole 318 may be formed on the source electrode 308, the drain electrode 310, the data line and the metal pattern 312 by depositing and patterning an organic insulating material such as benzocyclobutene (BCB) and acrylic resin. The drain contact hole 316 and the storage contact hole 318 expose the drain electrode 310 and the metal pattern 312, respectively.
In FIG. 7E, a pixel electrode 320 may be formed on the passivation layer 314 in the pixel region “P” by depositing and patterning one of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). The pixel electrode 320 is connected to the drain electrode 310 through the drain contact hole 316 and the metal pattern 312 through the storage contact hole 318. The pixel electrode 320 may be contacted with the drain electrode 310 and metal pattern 312 directly or indirectly via an intervening layer. The array substrate for an LCD device including the gate insulating layer having a relatively high dielectric constant is completed through process shown in FIGS. 7A to 7E.
Consequently, in the present invention, since a gate insulating layer having a relatively high dielectric constant may be formed using a composite precursor film or an organic polymer solution through a coating method instead of a deposition method, a fabrication process is simplified and a production yield is improved. In addition, since the gate insulating layer may have a relatively high dielectric constant and a planar surface, a property of a thin film transistor is improved. Further, since a pixel voltage variation is reduced, a display quality of an LCD device is improved.
It will be apparent to those skilled in the art that various modifications and variations can be made in an array substrate for a liquid crystal display device and a method of fabricating the array substrate of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Patent Application
20070236623
