Patent Application
20160322388
The present application claims a priority of the Chinese Patent Application No. 201510209721.8 filed on Apr. 28, 2015, which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of semiconductor display technology, in particular to an array substrate, its manufacturing method and a display device.
Thin Film Transistor Liquid Crystal Display (TFT-LCD) has currently become a mainstream of flat-panel display devices due to its features such as small volume, low power consumption and being free of radiation, and a TFT array substrate is an important component of the TFT-LCD. A conventional a-Si TFT has relatively low electron mobility, so it is impossible to meet the requirements of a display product on high charge-discharge rate and high refresh rate. Oxide TFT, e.g., IGZO TFT, has the electron mobility dozens of times the a-Si TFT. When the TFT is manufactured by a metal oxide, it is able for the TFT to remarkably increase the charge-discharge rate for a pixel electrode, so as to increase a response speed of the TFT. Hence, the oxide TFT is a development trend for novel display devices.
Generally, a metal oxide TFT array substrate is manufactured by forming a metal gate electrode, a gate insulation layer, an oxide semiconductor layer, an etch stop layer, source/drain electrodes, a passivation layer and a pixel electrode sequentially on a glass substrate. During the manufacture, there are a large number of process steps as well as a large number of mask plates to be used, which leads to a deterioration in the product quality and a long manufacture time period.
An object of the present disclosure is to provide an array substrate, its manufacturing method and a display device, so as to reduce the process steps and shorten manufacture time period for the manufacture of the TFT.
In one aspect, the present disclosure provides in some embodiments an array substrate, including a gate electrode, a gate insulation layer formed on the gate electrode, an active layer formed on the gate insulation layer, source/drain electrodes arranged at a layer identical to the active layer, and a pixel electrode arranged at a layer identical to the active layer. The active layer includes a metal oxide semiconductor, and the source/drain electrodes and the pixel electrode each include an ion-implanted metal oxide semiconductor.
Alternatively, the array substrate further includes a gate line arranged at a layer identical to the gate electrode and a plurality of first data line sections arranged at a layer identical to the gate electrode and separated by the gate line.
Alternatively, the gate insulation layer includes via-holes opened to the first data line sections respectively, the array substrate further includes a second data line section arranged at a layer identical to the active layer, and the second data line section spans over the gate line and is connected at two ends to the adjacent first data line sections separated by the gate line through the via-holes.
Alternatively, the second data line section is of a width less than each of the first data line sections.
In another aspect, the present disclosure provides in some embodiments a display device including the above-mentioned array substrate.
In yet another aspect, the present disclosure provides in some embodiments a method for manufacturing an array substrate, including steps of: forming a gate electrode; forming a gate insulation layer on the gate electrode; forming a metal oxide semiconductor layer on the gate insulation layer; and subjecting a part of the metal oxide semiconductor layer to ion implantation, and patterning the metal oxide semiconductor layer, so as to form source/drain electrodes and a pixel electrode at a region where the metal oxide semiconductor layer is subjected to the ion implantation, and form an active layer at a region where the metal oxide semiconductor layer is not subjected to the ion implantation.
Alternatively, the method further includes forming a plurality of first data lines and a gate line at a layer identical to the gate electrode while forming the gate electrode, the plurality of first data line sections being separated by the gate line.
Alternatively, the method further includes forming via-holes in the gate insulation layer and opened to the first data line sections respectively. The step of patterning the metal oxide semiconductor layer further includes forming a second data line section which spans over the gate line and is connected at two ends to the adjacent first data line sections separated by the gate line through the via-holes.
Alternatively, the ion implantation is hydrogen ion implantation.
Alternatively, the second data line section is of a width less than each of the first data line sections.
According to the embodiments of the present disclosure, the source/drain electrodes, the active layer and the pixel electrode are arranged at an identical layer, so they may be formed by merely one mask plate and one etching process. As a result, it is able to reduce the process steps and shorten the manufacture time period, thereby to improve the yield. In addition, it is also able to reduce a coupling capacitance between the data line section and the gate line by reducing a width of a portion of the data line section where the data line section is connected to the gate line.
In order to illustrate the technical solutions of the present disclosure or the related art in a clearer manner, the drawings desired for the present disclosure or the related art will be described hereinafter briefly. Obviously, the following drawings merely relate to some embodiments of the present disclosure, and based on these drawings, a person skilled in the art may obtain the other drawings without any creative effort.
In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.
Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as “first” and “second” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance. Similarly, such words as “one” or “one of” are merely used to represent the existence of at least one member, rather than to limit the number thereof. Such words as “connect” or “connected to” may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection. Such words as “on”, “under”, “left” and “right” are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too.
The present disclosure provides in some embodiments an array substrate which, as shown in
According to the array substrate in the embodiments of the present disclosure, the source/drain electrodes, the active layer and the pixel electrode are arranged at an identical layer, so they may be formed by merely one mask plate and one etching process. As a result, it is able to reduce the process steps and shorten the manufacture time period, thereby to improve the yield. In addition, it is also able to reduce a coupling capacitance between a data line section and the gate line by reducing a width of a portion of the data line section where the data line section is connected to the gate line.
Alternatively, the array substrate may further include first data line sections 41, 42 arranged at a layer identical to the gate electrode 2.
Alternatively, the gate insulation layer 3 may further include via-holes opened to the first data line sections 41, 42, respectively.
Alternatively, the array substrate may further include a gate line 20 arranged at a layer identical to the gate electrode 2, and a second data line section 4 arranged at a layer identical to the active layer 60. The second data line section 4 spans over the gate line 20 and is connected, at its two ends, to the first data line sections 41, 42 separated by the gate line 20 through the via-holes.
Alternatively, the second data line section 4 may be of a width less than the first data line sections 41, 42. In this way, it is able to reduce a coupling capacitance between the data line section and the gate line by reducing the width of a portion of the data line section where the data line section is connected to the gate line.
The present disclosure further provides in some embodiments a display device which includes the above-mentioned array substrate. The display device may be any device having a display function, such as a television, a display, a flat-panel computer, a digital photo frame, a navigator, an electronic paper or a mobile telephone.
The present disclosure further provides in some embodiments a method for manufacturing an array substrate which, as shown in
According to the method in the embodiments of the present disclosure, the source/drain electrodes, the active layer and the pixel electrode are arranged at an identical layer, so they may be formed by merely one mask plate and one etching process. As a result, it is able to reduce the process steps and shorten the manufacture time period, thereby to improve the yield. In addition, it is also able to reduce a coupling capacitance between the data line section and the gate line by reducing a width of a portion of the data line section where the data line section is connected to the gate line.
Alternatively, the method may further include forming first data line sections while forming the gate electrode.
Alternatively, the method may further include forming via-holes in the gate insulation layer and opened to the first data line sections respectively.
Alternatively, the method may further include forming a gate line while forming the gate electrode, and the step of patterning the metal oxide semiconductor layer may further include forming a second data line section which spans over the gate line and is connected at two ends to the first data line sections separated by the gate line through the via-holes.
Alternatively, the ion implantation may be hydrogen ion implantation.
Alternatively, the second data line section may be of a width less than each of the first data line sections.
The method for manufacturing the array substrate will be described hereinafter in more details.
As shown in
Step 501: forming the gate electrode, the gate line and the first data line sections on the glass substrate. In this step, referring to
Step 502: forming the gate insulation layer on the gate electrode, the gate line and the first data line sections, and forming the via-holes in the gate insulation layer. In this step, the gate insulation layer 3 may be deposited on the gate electrode 2, the gate line 20 and the first data line sections 41, 42, and the via-holes 01, 02 may be formed in the gate insulation layer 3 and opened to the first data line sections 41, 42 by masking, exposing and etching, as shown in
Step 503: depositing the metal oxide semiconductor layer on the gate insulation layer. In this step, the metal oxide semiconductor layer 50 may be deposited on the gate insulation layer 3, as shown in
Step 504: photoetching the metal oxide semiconductor layer and subjecting a part of the metal oxide semiconductor layer to the ion implantation, so as to form the second data line sections, the source/drain electrodes and the pixel electrode at a region where the metal oxide semiconductor layer is subjected to the ion implantation, and form the active layer at a region where the metal oxide semiconductor layer is not subjected to the ion implantation. In this step, a photoresist with different thicknesses may be formed on the semiconductor layer 50 through a halftone mask plate, and then etched so as to form the regions corresponding to the second data line section, the active layer, the source/drain electrodes and the pixel electrode, as shown in
At this time, the photoresist 80 is still reserved at a region right above the gate electrode 2, and thus this region is not subjected to the ion implantation (as shown in
According to method in the embodiments of the present disclosure, the array substrate may be formed using merely three mask plates. As a result, it is able to reduce the process steps and shorten the manufacture time period, thereby to improve the yield. In addition, it is also able to reduce a coupling capacitance between the data line section and the gate line by reducing a width of a portion of the data line section where the data line section is connected to the gate line.
The above are merely the preferred embodiments of the present disclosure. It should be appreciated that, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201510209721.8 | Apr 2015 | CN | national |
