The present disclosure relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.
Along with the maturation and development of the liquid crystal display (LCD) panel industry, a liquid crystal display panel with high quality, e.g., high brightness, high contrast and high resolution, is highly demanded. However, in terms of a current manufacturing process, a low light transmittance has become a bottleneck for the high-resolution LCD panel.
Especially, an array substrate of the LCD panel with an advanced super dimension switching (ADS) mode includes a plurality of insulation layers, e.g., a gate insulation layer, an insulation layer arranged between a source/drain metal layer and a first transparent electrode layer, and another insulation layer arranged between the first transparent electrode layer and a second transparent electrode layer. In addition, in the case that thin film transistors (TFTs) of the array substrate are of a top-gate type, the array substrate further includes another insulation layer between a gate metal layer and the source/drain metal layer. Due to the plurality of insulation layers, the light transmittance of the array substrate as well as a display effect may be adversely affected.
An object of the present disclosure is to provide an array substrate, a manufacturing method thereof, and a display device, so as to improve the light transmittance of the array substrate.
In one aspect, the present disclosure provides in some embodiments an array substrate, including: a plurality of gate lines and a plurality of data lines defining a plurality of pixel regions; and a plurality of insulation layers including at least one hollowed-out insulation layer. A portion of the hollowed-out insulation layer at a corresponding pixel region is provided with a hollowed-out region.
In a possible embodiment of the present disclosure, the array substrate further includes a gate insulation layer, and the hollowed-out insulation layer includes the gate insulation layer.
In a possible embodiment of the present disclosure, the array substrate further includes a source/drain metal layer, a first transparent electrode layer and a second insulation layer arranged between the source/drain metal layer and the first transparent electrode layer, and the hollowed-out insulation layer includes the second insulation layer.
In a possible embodiment of the present disclosure, the array substrate is a top-gate array substrate including a source/drain metal layer, a gate metal layer and a first insulation layer arranged between the gate metal layer and the source/drain metal layer, and the hollowed-out insulation layer includes the first insulation layer.
In a possible embodiment of the present disclosure, the array substrate further includes an active layer, and the first insulation layer is provided with a hollowed-out region at a position where the source/drain metal layer is lapped onto the active layer.
In a possible embodiment of the present disclosure, the portion of the hollowed-out insulation layer at the corresponding pixel region is fully hollowed out.
In a possible embodiment of the present disclosure, the portion of the hollowed-out insulation layer at each pixel region is provided with the hollowed-out region.
In a possible embodiment of the present disclosure, the portions of the hollowed-out insulation layer at a part of pixel regions are provided with the hollowed-out regions respectively, and the portions of the hollowed-out insulation layer at the other part of pixel regions are not provided with any hollowed-out regions.
In a possible embodiment of the present disclosure, the hollowed-out region of the first insulation layer at the position where the source/drain metal layer is lapped onto the active layer and the hollowed-out region of the first insulation layer at the other position in the pixel region are formed through one single patterning process.
In a possible embodiment of the present disclosure, the hollowed-out region of the first insulation layer at the position where the source/drain metal layer is lapped onto the active layer and the hollowed-out region of the first insulation layer at the other position in the pixel region are formed in one piece.
In another aspect, the present disclosure provides in some embodiments a display device including the above-mentioned array substrate.
In yet another aspect, the present disclosure provides in some embodiments a method for manufacturing an array substrate, including a step of forming a gate metal layer, a source/drain metal layer and a plurality of insulation layers. The gate metal layer includes a plurality of gate lines, the source/drain metal layer includes a plurality of data lines, the plurality of gate lines and the plurality of data lines define a plurality of pixel regions, the plurality of insulation layers includes at least one hollowed-out insulation layer, and a portion of the hollowed-out insulation layer at a corresponding pixel region is provided with a hollowed-out region.
In a possible embodiment of the present disclosure, the step of forming the plurality of insulation layers includes forming a gate insulation layer, and the hollowed-out insulation layer includes the gate insulation layer.
In a possible embodiment of the present disclosure, the method further includes forming a first transparent electrode layer. The step of forming the plurality of insulation layers includes forming a second insulation layer between the source/drain metal layer and the first transparent electrode layer, and the hollowed-out insulation layer includes the second insulation layer.
In a possible embodiment of the present disclosure, in the case that the array substrate is a top-gate array substrate, the step of forming the plurality of insulation layers includes forming a first insulation layer between the gate metal layer and the source/drain metal layer, and the hollowed-out insulation layer includes the first insulation layer.
According to the embodiments of the present disclosure, the portion of the at least one insulation layer at the corresponding pixel region of the array substrate is provided with the hollowed-out region, so as to reduce adverse impact of the insulation layers at the pixel region on a light transmittance, thereby to improve a display effect.
In order to illustrate the technical solutions of the present disclosure or the related art in a clearer manner, the drawings desired for the present disclosure or the related art will be described hereinafter briefly. Obviously, the following drawings merely relate to some embodiments of the present disclosure, and based on these drawings, a person skilled in the art may obtain the other drawings without any creative effort.
The present disclosure will be described hereinafter in conjunction with the drawings and embodiments. The following embodiments are for illustrative purposes only, but shall not be used to limit the scope of the present disclosure.
In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.
The present disclosure provides in some embodiments an array substrate, which includes: a plurality of gate lines and a plurality of data lines defining a plurality of pixel regions; and a plurality of insulation layers including at least one hollowed-out insulation layer. A portion of the hollowed-out insulation layer at a corresponding pixel region is provided with a hollowed-out region.
According to the array substrate in the embodiments of the present disclosure, the portion of the at least one insulation layer at the corresponding pixel region of the array substrate is provided with the hollowed-out region, so as to reduce adverse impact of the insulation layers at the pixel region on a light transmittance, thereby to improve a display effect.
In the embodiments of the present disclosure, the portion of the hollowed-out insulation layer at each pixel region may be provided with the hollowed-out region. Of course, in some other cases, the portions of the hollowed-out insulation layer at a part of pixel regions may be provided with the hollowed-out regions respectively, and the portions of the hollowed-out insulation layer at the other part of pixel regions may not be provided with any hollowed-out regions.
The array substrate further includes a gate insulation layer. In a possible embodiment of the present disclosure, the hollowed-out insulation layer may include the gate insulation layer. In other words, a portion of the gate insulation layer at the corresponding pixel region is provided with the hollowed-out region, so as to reduce adverse impact of the insulation layers at the pixel region on the light transmittance, thereby to improve the display effect.
The array substrate further includes a source/drain metal layer, a first transparent electrode layer and a second insulation layer arranged between the source/drain metal layer and the first transparent electrode layer. The source/drain metal layer may include source electrodes, drain electrodes and the data lines. The first transparent electrode layer may be a pixel electrode layer or a common electrode layer. In a possible embodiment of the present disclosure, the hollowed-out insulation layer may include the second insulation layer. In other words, a portion of the second insulation layer at the corresponding pixel region is provided with the hollowed-out region, so as to reduce adverse impact of the second insulation layer at the pixel region on the light transmittance, thereby to improve the display effect.
In a possible embodiment of the present disclosure, each drain electrode is lapped onto the pixel electrode layer through the hollowed-out region of the second insulation layer at the corresponding pixel region, i.e., it is unnecessary to form a via-hole in the second insulation layer for connecting the drain electrode and the pixel electrode layer. As a result, it is unnecessary to provide any additional mask plate, thereby to reduce the manufacture cost.
Of course, in some other embodiments of the present disclosure, the hollowed-out insulation layer may include the gate insulation layer and the second insulation layer, so as to further reduce adverse impact of the insulation layers at the corresponding pixel region on the light transmittance, thereby to improve the display effect.
In the case that the array substrate is a top-gate array substrate, it may include the source/drain metal layer, the gate metal layer and a first insulation layer arranged between the gate metal layer and the source/drain metal layer. The source/drain metal layer may include source electrodes, drain electrodes and the data lines. The gate metal layer may include gate electrodes and the gate lines. In a possible embodiment of the present disclosure, the hollowed-out insulation layer includes the first insulation layer. In other words, a portion of the first insulation layer at the corresponding pixel region is provided with the hollowed-out region, so as to reduce adverse impact of the first insulation layer at the pixel region on the light transmittance, thereby to improve the display effect.
Of course, in some other embodiments of the present disclosure, the hollowed-out insulation layer may include any two or three of the gate insulation layer, the first insulation layer and the second insulation layer, so as to further reduce adverse impact of the insulation layers at the corresponding pixel region on the light transmittance, thereby to improve the display effect.
The array substrate further includes an active layer. In a possible embodiment of the present disclosure, the first insulation layer is provided with the hollowed-out region at a position where the source/drain metal layer is lapped onto the active layer, so as to facilitate the connection of the source/drain metal layer to the active layer. The hollowed-out region of the first insulation layer at the position where the source/drain metal layer is lapped onto the active layer and the hollowed-out region of the first insulation layer at the other position in the pixel region may be formed through one single patterning process. As a result, it is unnecessary to form a via-hole in the first insulation layer for connecting the source/drain metal layer to the active layer.
In a possible embodiment of the present disclosure, the hollowed-out region of the first insulation layer at the position where the source/drain metal layer is lapped onto the active layer and the hollowed-out region of the first insulation layer at the other position in the pixel region are formed in one piece.
In a possible embodiment of the present disclosure, the portion of the hollowed-out insulation layer at the corresponding pixel region is fully hollowed out, so as to reduce adverse impact of the insulation layers on the light transmittance to the maximum extent, thereby to improve the display effect.
The present disclosure further provides in some embodiments a display device including the above-mentioned array substrate.
The display device may be a display panel or a display element including the display panel and a driving circuit. In a possible embodiment of the present disclosure, the display device is a liquid crystal display (LCD) device.
The present disclosure further provides in some embodiments a method for manufacturing an array substrate, which includes a step of forming a gate metal layer, a source/drain metal layer and a plurality of insulation layers. The gate metal layer includes a plurality of gate lines, the source/drain metal layer includes a plurality of data lines, the plurality of gate lines and the plurality of data lines define a plurality of pixel regions, the plurality of insulation layers includes at least one hollowed-out insulation layer, and a portion of the hollowed-out insulation layer at a corresponding pixel region is provided with a hollowed-out region.
In a possible embodiment of the present disclosure, the step of forming the plurality of insulation layers includes forming a gate insulation layer, and the hollowed-out insulation layer includes the gate insulation layer.
In a possible embodiment of the present disclosure, the method further includes forming a first transparent electrode layer. The step of forming the plurality of insulation layers includes forming a second insulation layer between the source/drain metal layer and the first transparent electrode layer, and the hollowed-out insulation layer includes the second insulation layer.
In a possible embodiment of the present disclosure, in the case that the array substrate is a top-gate array substrate, the step of forming the plurality of insulation layers includes forming a first insulation layer between the gate metal layer and the source/drain metal layer, and the hollowed-out insulation layer includes the first insulation layer.
The structure of the array substrate will be described hereinafter in conjunction with the embodiments.
Referring to
Referring to
According to the embodiments of the present disclosure, the portion of the first insulation layer 105 at the corresponding pixel region of the array substrate is provided with the hollowed-out region, so as to reduce adverse impact of the first insulation layer 105 on the light transmittance, thereby to improve the display effect.
Referring to
As mentioned above, the first insulation layer 105 between the gate metal layer and the source/drain metal layer is provided with the hollowed-out region at the corresponding pixel region. Of course, in some other embodiments of the present disclosure, the second insulation layer 107 between the source/drain metal layer and the common electrode layer 108 may be provided with the hollowed-out region at the corresponding pixel region. Alternatively, both the first insulation layer 105 and the second insulation layer 107 may be provided with the hollowed-out regions at the corresponding pixel regions.
In the embodiments of the present disclosure, the common electrode layer 108 and the pixel electrode layer 110 may be interchangeable with each other.
The present disclosure further provides in some embodiments a display device including the above-mentioned array substrate. The features of the array substrate included in the display device may refer to those mentioned above, and thus will not be particularly defined herein.
The present disclosure further provides in some embodiments a method for manufacturing an array substrate which, as shown in
In a possible embodiment of the present disclosure, the step of forming the plurality of insulation layers includes forming a gate insulation layer, and the hollowed-out insulation layer includes the gate insulation layer.
In a possible embodiment of the present disclosure, the method may further include forming a first transparent electrode layer. The step of forming the plurality of insulation layers includes forming a second insulation layer between the source/drain metal layer and the first transparent electrode layer. The hollowed-out insulation layer includes the second insulation layer.
In a possible embodiment of the present disclosure, in the case that the array substrate is a top-gate array substrate, the step of forming the plurality of insulation layers includes forming a first insulation layer between the gate metal layer and the source/drain metal layer. The hollowed-out insulation layer includes the first insulation layer.
Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as “first” and “second” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance. Similarly, such words as “one” or “one of” are merely used to represent the existence of at least one member, rather than to limit the number thereof. Such words as “connect” or “connected to” may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection. Such words as “on”, “under”, “left” and “right” are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too.
The above are merely the preferred embodiments of the present disclosure, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.
Number | Date | Country | Kind |
---|---|---|---|
201710331516.8 | May 2017 | CN | national |
The present application is the U.S. national phase of PCT Application No. PCT/CN2017/110125 filed on Nov. 9, 2017, which claims a priority of the Chinese patent application No. 201710331516.8 filed on May 11, 2017, which is incorporated herein by reference in its entirety.
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/CN2017/110125 | 11/9/2017 | WO | 00 |