Patent Application
20150162361
Embodiments of the disclosure relate to the field of display technologies, more particularly, to an array substrate, a method for fabricating the same and a display device.
Liquid Crystal Displays (LCDs) as important flat-panel display device have evolved rapidly during the past decade. Having the advantages of being lightweight, thin and power saving, LCD are widely used in modern information devices such as televisions, computers, mobile phones, digital cameras and the like. Recently, oxide Thin Film Transistors (TFTs) attract much attention from the industry due to high mobility. Oxide can reduce the size of the TFT and increase the resolution for having a higher mobility. However, increase in the resolution has to be accompanied by decreasing in the width of the source/drain electrode line, which will result in wire breakage occurring in metal lines.
Embodiments of the disclosure provide an array substrate, a method for fabricating the same and a display device.
An aspect of the disclosure provides an array substrate, comprising an oxide active layer; the oxide active layer comprises a non-metallized semiconductor region and a metallized metal oxide conductor region.
As an example, the array substrate further comprises an etch stop layer and a source/drain electrode layer,
the non-metallized semiconductor region corresponds to a location of the etch stop layer;
the metallized metal oxide conductor region corresponds to a location of the source/drain electrode layer.
As an example, the array substrate further comprises a gate electrode, a gate insulation layer, a pixel electrode layer and a passivation layer.
As an example, the oxide active layer is made of at least one of InGaZnO, InGaO, ITZO, AlZnO.
In another aspect, the disclosure further provides a method for fabricating an array substrate, comprising:
forming a pattern of an oxide active layer, the pattern of the oxide active layer comprising a non-metallized semiconductor region and a metallized metal oxide conductor region.
As an example, Ruining the pattern of the oxide active layer comprises:
forming an oxide semiconductor material;
forming a pattern of an etch stop layer on the oxide semiconductor material;
metallizing a portion of the oxide semiconductor material uncovered by the etch stop layer, and forming the non-metallized semiconductor region in a portion covered by the etch stop layer;
forming a source/drain metal layer, and foci ling a pattern of a source/drain electrode and the metal oxide conductor region at the same time through a patterning process.
As an example, the oxide active layer comprises at least one of InGaZnO, InGaO, ITZO, AlZnO.
As an example, the metallization is performed for 30 minutes to 120 minutes in a reducing atmosphere at a temperature of 100° C. to 300° C.
As an example, the reducing atmosphere comprises hydrogen or hydrogen-containing plasma.
As an example, the metallized metal oxide conductor region corresponds to a location of the source/drain electrode layer, the non-metallized semiconductor region corresponds to a location of the etch stop layer.
In another aspect, the disclosure further provides a display device comprising the above array substrate.
In order to clearly illustrate the technical solution of the embodiments of the disclosure, the drawings of the embodiments will be briefly described in the following. It is obvious that the described drawings are only related to some embodiments of the disclosure and thus are not limitative of the disclosure.
In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiment will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. It is obvious that the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.
The embodiment of the disclosure provides an array substrate; the array substrate will be described by taking a bottom-gate configuration as an example.
As illustrated in
The oxide active layer comprises a semiconductor region 22 not being metallized and a metal oxide conductor region 24 being metalized.
As an example, the semiconductor region 22 corresponds to a location of the etch stop layer 23; the metal oxide conductor region 24 corresponds to a location of the source/drain electrode layer 31 and is disposed under the source/drain electrode layer 31.
The oxide active layer is made of for example at least one of InGaZnO, InGaO, ITZO, AlZnO. It can be contemplated that the material of the oxide active layer may also be, other than those above-described, other materials having the same or similar properties to the above materials.
According to the embodiment of the disclosure, the metal oxide conductor region is formed by metallizing the portion of the oxide active layer corresponding to the source/drain electrode layer. Since the metal oxide conductor region is of conductor properties, it can effectively decrease the resistance of the source/drain electrode layer and reduce the possibility of wire breakage occurring in the data line to the maximum extent.
The embodiment of the disclosure provides an array substrate; the array substrate differs from that of Embodiment 1 in that the array substrate has a top-gate configuration.
The array substrate comprises a substrate, disposed on the substrate are a pixel electrode layer, a source/drain electrode layer, an oxide active layer, an etch stop layer, a gate insulation layer and a gate electrode, wherein the pixel electrode layer is connected to the drain electrode.
Herein the oxide active layer comprises a semiconductor region not being metallized and a metal oxide conductor region being metalized.
As an example, the semiconductor region corresponds to a location of the etch stop layer; the metal oxide conductor region corresponds to a location of the source/drain electrode layer and is disposed above the source/drain electrode layer.
The oxide active layer is made of for example at least one of InGaZnO, InGaO, ITZO, AlZnO. It can be contemplated that the material of the oxide active layer may also be, other than those above-described, other materials having the same or similar properties to the above materials.
It is noted that an improvement in the array substrate of the embodiment is mainly the improvement to the oxide active layer. For other layer structures please refer to conventional top-gate configurations, which will not be elaborated here.
As illustrated in
Step 1: forming a pattern of a gate electrode on a substrate.
For example, with reference to
Step 2: sequentially forming a gate insulation layer, an oxide semiconductor material and a pattern of an etch stop layer.
For example, with reference to
The oxide semiconductor material may comprise for example at least one of InGaZnO, InGaO, ITZO, AlZnO. It can be contemplated that the material of the oxide semiconductor material may also be, other than those above-described, other materials having the same or similar properties to the above materials.
Step 3: metallizing a portion of the oxide semiconductor material not covered by the etch stop layer, a portion covered by the etch stop layer and not metallized forming a semiconductor region.
For example, with reference to
The metallized metal oxide conductor region has the properties of conductors; therefore, it can effectively decrease the resistance of the source/drain electrode layer and reduce the possibility of wire breakage occurring in the source/drain electrode layer to the maximum extent.
The portion of the oxide semiconductor material covered by the etch stop layer is the semiconductor region 22.
Step 4: forming a source/drain metal layer, and forming a pattern of a source/drain electrode layer and the metal oxide conductor region through a single patterning process.
Still referring to
For example, the step comprises: depositing a source/drain metal layer on the metallized metal oxide conductor region 24, after exposing these two film layers with a single exposing process, first etching the source/drain metal layer once to form the pattern of the source/drain electrode layer, then continuing etching the metal oxide conductor region by changing the etchant to form the pattern of the metal oxide conductor region. The source/drain electrode layer and the metal oxide conductor region may be the same or different from each other.
Step 5: forming a passivation layer and forming a via hole.
With reference to
Step 6: forming a pattern of a pixel electrode through a patterning process.
With reference to
According to the embodiment of the disclosure, the metal oxide conductor region is formed by metallizing the portion of the oxide active layer not covered by the etch stop layer. Since the metal oxide conductor region is of conductor properties, it can effectively decrease the resistance of the source/drain electrode layer and reduce the possibility of wire breakage occurring in the data line.
It is noted that the patterning processes used in the disclosure are processes such as exposing, developing, etching, and peeling generally used in conventional art.
Furthermore, an embodiment of the disclosure provides a display device comprising the above array substrate. The display device may be a liquid crystal panel, an E-paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo-frame, a mobile phone, a tablet PC and any product or component having a display function.
What are described above is related to the illustrative embodiments of the disclosure only and not limitative to the scope of the disclosure; the scopes of the disclosure are defined by the accompanying claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201310446288.0 | Sep 2013 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2013/088840 | 12/9/2013 | WO | 00 |
