Patent Application
20150235586
The present application is based on and claims the benefit of priority of Chinese Patent Application No. 201410052962.1 filed on Feb. 17, 2014, the entire contents of which are hereby incorporated by reference.
The present invention relates to the field of display technology, in particular to an array substrate, a method for manufacturing an array substrate, and a display device.
In an existing TFT-LCD (liquid crystal display) panel, a data line and a pixel electrode are usually made of a metallic material on different two layers. Taking a display panel with an advanced super dimension switch (ADS) technique as an example, its core feature is forming a multidimensional electric field within an identical plane by means of an electric field produced at an edge of a slit electrode and an electric field produced between a slit electrode layer and a plate electrode layer, so as to rotate all alignment liquid crystal molecules that between the slit electrodes and those directly above the electrodes within a crystal liquid cell, thereby to improve the working efficiency of the liquid crystals and increase the light transmittance. Taking the display panel with the ADS mode as an example, as shown in
During the manufacture, a pixel electrode layer and a data line layer are required to be aligned with the gate line layer, respectively, and the repeated alignment will easily shift the position of the pixel electrode layer relative to the data line layer, as shown in
An object of the present invention is to prevent the deterioration of the display quality due to a shift of a data line.
In one aspect, the present invention provides an array substrate, comprising a substrate, a data line, and a gate line and a pixel electrode formed sequentially on the substrate. The data line includes a fixed segment arranged on a same layer as, and spaced from, the gate line or the pixel electrode, and a connection segment electrically connected to the fixed segment.
Further, two ends of the fixed segment of the data line are aligned with two ends of the pixel electrode, respectively.
Further, a gate insulating layer and a source/drain electrode layer are provided above the gate line, and the connection segment of the data line is arranged on a same layer as the source/drain electrode layer.
Further, when the fixed segment of the data line is arranged on a same layer as the gate line, the fixed segment of the data line is arranged spacing from the gate line, without overlapping each other.
Further, when the fixed segment of the data line is arranged on a same layer as the gate line, the connection segment of the data line is connected to the fixed segment of the data line through a via-hole penetrating through the gate insulating layer.
Further, the fixed segment of the data line is made of an identical material to the gate line.
Further, when the fixed segment of the data line is arranged on a same layer as the pixel electrode, the fixed segment of the data line is arranged spacing from the pixel electrode, without overlapping each other.
Further, when the fixed segment of the data line is arranged on a same layer as the pixel electrode, the connection segment of the data line is electrically lapped over the fixed segment of the data line directly.
Further, the fixed segment of the data line is made of an identical material to the pixel electrode.
In another aspect, the present invention provides a method for manufacturing an array substrate, comprising forming patterns of a gate line, a data line and a pixel electrode on a substrate. The pattern of the data line includes a fixed segment arranged on a same layer as, and spaced from, the gate line or the pixel electrode, and a connection segment electrically connected to the fixed segment of the data line.
Further, the step of forming the pattern of the gate line on the substrate comprises: forming the patterns of the gate line and the fixed segment of the data line on the substrate simultaneously by a patterning process.
Further, subsequent to forming the pattern of the gate line on the substrate, the method further comprises:
forming a gate insulating layer above the pattern of the gate line; and
forming patterns of source/drain electrodes and the connection segment of the data line above the gate insulating layer simultaneously by a patterning process.
Further, subsequent to forming the gate insulating layer above the pattern of the gate line, the method further comprises:
forming a via-hole that penetrates through the gate insulating layer, so as to the fixed segment is connected with the to-be-formed connection segment of the data line.
Further, subsequent to forming the pattern of the gate line on the substrate, the method further comprises:
forming the gate insulating layer above the pattern of the gate line; and
forming the patterns of the source/drain electrodes and the connection segment of the data line above the gate insulating layer simultaneously by a patterning process.
The step of forming the pattern of the pixel electrode on the substrate comprises:
forming the patterns of the pixel electrode and the fixed segment of the data line above the patterns of the source/drain electrodes and the connection segment of the data line simultaneously by a patterning process, the connection segment of the data line being electrically lapped over the fixed segment of the data line directly.
In yet another aspect, the present invention provides a display device comprising the above-mentioned array substrate.
According to the array substrate, the method for manufacturing the array substrate and the display device of the present invention, the data line is divided into two parts, i.e., the fixed segment and the connection segment, and the fixed segment is arranged on a same layer as the gate line or the pixel electrode while the connection segment is electrically connected to the fixed segment. It is merely required to carry out the alignment once with the layer on which the gate line is located, so as to reduce the number of times of the alignment, thereby to reduce the shift amount within a controllable range. As a result, it is able to prevent the data line from being too close to the pixel electrode at the shift side, thereby to prevent a charging voltage for the pixel electrode from being affected by the capacitance effect and ensure the display quality of an image. In addition, no additional resistor is required, so it is able to reduce the power consumption.
Wherein, 1. gate line; 2. pixel electrode; 3. data line; 31. fixed segment of data line; 32. connection segment of data line; 4. common electrode; 5. via-hole.
The present invention will be described hereinafter in conjunction with the drawings and the embodiments. The following embodiments are for illustrative purposes only, but shall not be used to limit the scope of the present invention.
In this embodiment, an array substrate comprises a substrate, a data line 3, and a gate line 1 and a pixel electrode 2 formed sequentially on the substrate. The data line 3 includes a fixed segment 31 arranged on a same layer as, and spaced from, the gate line 31, and a connection segment 32 is electrically connected to the fixed segment 31, as shown in
Preferably, two ends of the fixed segment 31 are aligned with two ends of the pixel electrode 2, respectively. It is to be noted that, the connection segment 32 of the data line merely serves as a connection end for connecting the fixed segment 31 of the data line and a driving circuit, and it is not located between the pixel electrodes 2, so no capacitance effect will be caused even if it is shifted during the manufacture.
Referring to
When the fixed segment 31 of the data line is formed on a same layer as the gate line 1, a via-hole 5 is provided on a gate insulating layer above the gate line 1, at a position corresponding to a lapping segment of the fixed segment 31 of the data line, and the connection segment 32 of the data line is connected to the fixed segment 31 of the data line through the via-hole 5.
In order to reduce the process steps and the process complexity, the fixed segment 31 of the data line is made of an identical material to the gate line 1.
The fixed segment 31 and the connection segment 32 of the data line may, in accordance with the actual situations, be made of identical or different materials.
A method for manufacturing the array substrate will be described hereinafter. At first, the fixed segment of the data line and the gate line, which are made of an identical material, are formed on the substrate. To be specific, patterns of the gate line and the fixed segment of the data line are formed on the substrate simultaneously by a patterning process, and the fixed segment 31 of the data line is spaced from the gate line 1, without overlapping one another. Then, the gate insulating layer, a source/drain electrode layer, the pixel electrode 2 and the connection segment 32 of the data line are sequentially arranged on the substrate. To be specific, after the pattern of the gate line is formed on the substrate, the gate insulating layer is formed thereabove, and the patterns of the source/drain electrodes and the connection segment 32 of the data line are formed above the gate insulating layer simultaneously by a patterning process, so that the connection segment 32 of the data line is formed on a same layer as the source/drain electrode layer. Finally, after the gate insulating layer is formed above the pattern of the gate line, the via-hole that penetrates the gate insulating layer is formed, through which the fixed segment 31 of the data line and the to-be-formed connection segment 32 of the data line are connected with each other.
Since other layers on the substrate are aligned with each other with the layer where the gate line is located as a basis, therefore, in this embodiment, the fixed segment of the data line, which is aligned with the pixel electrode, is formed on a same layer as the gate line, so it is merely required to align the pixel electrode with the layer where the gate line and the fixed segment of the data line are located, and the alignment of the connection segment of the data line is not highly required. As a result, it is able to improve the shift amount within a controllable range and prevent the data line from being too close to the pixel electrode at the shift side, thereby to prevent the charging voltage for the pixel electrode from being affected due to the capacitance effect and ensure the display quality of the image. In addition, no additional resistor is required, so it is able to reduce the power consumption.
In this embodiment, the array substrate comprises a substrate, a data line, and a gate line and a pixel electrode formed sequentially on the substrate. The data line comprises a fixed segment and a connection segment. As shown in
When the fixed segment of the data line is arranged on a same layer as the pixel electrode, there is no other layer between the pixel electrode and the connection segment 32, so the connection segment 32 of the data line can be electrically lapped over the fixed segment 31 of the data line directly. Of course, they may be connected to each other via any other electrical element.
For example, two ends of the fixed segment 31 are aligned with two ends of the pixel electrode 2, respectively. It is to be noted that, the connection segment 32 of the data line merely serves as a connection end for connecting the fixed segment 31 of the data line and a driving circuit, and it is not located between the pixel electrodes 2, so no capacitance effect will be caused even if it is shifted during the manufacture. As shown in
In order to reduce the process steps and the process complexity, when the fixed segment 31 of the data line is formed on a same layer as the pixel electrode 2, the fixed segment 31 of the data line may be made of an identical material to the pixel electrode 2.
The fixed segment 31 and the connection segment 32 of the data line may, in accordance with the actual situations, be made of an identical or different materials.
A method for manufacturing the array substrate according to the embodiment will be described hereinafter. At first, a pattern of the gate line is formed on the substrate; secondly, a gate insulating layer is formed above the pattern of the gate line, and patterns of source/drain electrodes and the connection segment 32 of the data line are formed above the gate insulating layer simultaneously by a patterning process. Then, a pattern of the pixel electrode is formed on the substrate with the gate line 1. To be specific, patterns of the pixel electrode and the fixed segment 31 of the data line are formed above the patterns of the source/drain electrodes and the connection segment 32 of the data line simultaneously by a patterning process, and the fixed segment of the data line is arranged on a same layer as the pixel electrode, and having the fixed segment 31 of the data line and the pixel electrode being spaced from each other, and without overlapping one another. The connection segment 32 of the data line is electrically lapped over the fixed segment 31 of the data line directly.
Since other layers on the substrate are aligned with each other with the layer where the gate line is located as a basis, therefore, in this embodiment, the fixed segment of the data line that is aligned with the pixel electrode is formed on a same layer as the pixel electrode, so it is merely required to align the layer where the fixed segment of the data line and the pixel electrode are located with the layer where the gate line is located, and the alignment of the connection segment of the data line is not highly required. As a result, it is able to improve the shift amount within a controllable range and prevent the data line from being too close to the pixel electrode at the shift side, thereby to prevent the charging voltage for the pixel electrode from being affected due to the capacitance effect and ensure the display quality of the image. In addition, no additional resistor is required, so it is able to reduce the power consumption.
It is to be noted that, the fixed segments of the data lines may be arranged on the array substrate by combining the ways mentioned in the first and second embodiments, i.e., a plurality of the data lines may be arranged in different ways selected from either of the first and second embodiments. However, the process therefore may be more complex.
In addition, it is to be noted that, the pixel electrode in the above embodiments may be arranged above or below the connection segment of the data line (similar to all the data lines in the prior art), and the position relationship between the pixel electrode and the connection segment of the data line is not particularly defined in the present invention.
When the pixel electrode is arranged below the connection segment of the data line, the patterns of the pixel electrode and the fixed segment of the data line may be formed prior to the patterns of the source/drain electrodes and the connection segment of the data line. When the pixel electrode is arranged above the connection segment of the data line, the patterns of the source/drain electrodes and the connection segment of the data line may be formed prior to the patterns of the pixel electrode and the fixed segment of the data line.
The present invention further provides a display device comprising the above-mentioned array substrate.
According to the array substrate, the method for manufacturing the array substrate and the display device of the disclosure, the data line is divided into two parts, i.e., the fixed segment and the connection segment. The ends of the fixed segment of the data line are aligned with the ends of the pixel electrode, respectively, and the connection segment of the data line merely serves as the connection end for connecting the fixed segment of the data line and the driving circuit but not located between the pixel electrodes. Meanwhile, the fixed segment of the data line is arranged on a same layer as the gate line or the pixel electrode. It is merely required to carry out the alignment once with the layer on which the gate line is located, so as to reduce the number of times of the alignment, thereby to reduce the shift amount within a controllable range. As a result, it is able to prevent the data line from being too close to the pixel electrode at the shift side, thereby to prevent a charging voltage for the pixel electrode from being affected by the capacitance effect, ensure the display quality of an image. In addition, no additional resistor is required, so it is able to reduce the power consumption.
The above are merely the preferred embodiments of the present invention. It should be noted that, a person skilled in the art may make modifications and improvements without departing from the principle of the present invention, and these modifications and improvements shall be also considered as the scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410052962.1 | Feb 2014 | CN | national |
