Patent Application
20240021629
Embodiments of the present disclosure relate to an array substrate, a method of manufacturing the same, a method of improving performance of the same, a display panel, and a display device.
In the manufacturing process of the display panel or array substrate, the bottom shielding metal (BSM) layer is commonly used in the shielding layer, fingerprint identification, or, in the flexible display panel, it is also used to eliminate the effect of moving charges on the side of the flexible substrate. However, due to BSM not being connected with the circuit, the electric field intensity of the additional electric field formed by BSM is uncontrollable. When the additional electric field acts on the active layer, it may cause the abnormal phenomenon of warping in the saturation region of the output characteristic curve, make the output current abnormal, and even affect the threshold voltage of the thin film transistor.
The research on array substrate needs to be deepened.
At least one embodiment of the present disclosure provides an array substrate, comprising: a base substrate; a shielding layer provided on a surface of the base substrate; a thin film transistor (TFT) provided on the base substrate and covering the shielding layer; and a compensation layer provided on a side of the thin film transistor away from the base substrate and configured to form a second electric field of an active layer of the thin film transistor.
For example, an orthographic projection of the compensation layer on the base substrate and an orthographic projection of the active layer on the base substrate have an overlapping region.
For example, the thin film transistor has a top-gate structure, and an orthographic projection of an active layer and an orthographic projection of the compensation layer of the thin film transistor on the base substrate have an overlap region, and an orthographic projection of a gate electrode of the thin film transistor on the base substrate does not completely overlap with the overlap region.
For example, the array substrate further comprises a storage capacitor structure, and the storage capacitor structure comprises a first electrode and a second electrode. If the thin film transistor is a bottom-gate structure TFT, the first electrode is arranged on a side of the buffer layer in the bottom-gate structure TFT away from the base substrate; if the thin film transistor is a top-gate structure TFT, the first electrode is arranged on a side of a first gate insulating layer in the top-gate structure TFT away from the base substrate, and the first electrode and a gate electrode of the thin film transistor are formed by a single patterning process; the second electrode is provided on a side of a second gate insulating layer of the thin film transistor away from the base substrate, and the second electrode and the compensation layer are formed by a single patterning process.
For example, the compensation layer is formed by material including a metal or a metal alloy.
For example, the compensation layer has a thickness ranging from about 100 nm to about 500 nm.
Embodiments of the present disclosure also provide a method of manufacturing an array substrate, comprising: providing a base substrate; forming a shielding layer on a surface of the base substrate; forming a thin film transistor (TFT) on the base substrate, the TFT covering the shielding layer; and forming a compensation layer on a side of the thin film transistor away from the base substrate, so as to form a second electric field in the active layer of the TFT.
For example, forming of the thin film transistor comprises: forming a buffer layer on the base substrate, the buffer layer covering the shielding layer; forming the active layer on a side of the buffer layer away from the base substrate; forming the first gate insulating layer on a side of the active layer and the buffer layer away from the base substrate, the first gate insulating layer covering the active layer; forming a gate electrode on a side of the first gate insulating layer away from the base substrate; and forming the second gate insulating layer on a side of the gate electrode and the first gate insulating layer away from the base substrate, the second gate insulating layer covering the gate electrode. An orthographic projection of the active layer and an orthographic projection of the compensation layer on the base substrate have an overlapping region, and an orthographic projection of the gate electrode on the base substrate does not completely overlap with the overlapping region.
For example, forming a storage capacitor structure comprising: forming a first electrode; if the thin film transistor is a bottom-gate structure TFT, the first electrode is formed on a side of the buffer layer of the bottom gate structure TFT away from the base substrate; if the thin film transistor is a top-gate structure TFT, the first electrode is formed on a side of the first gate insulating layer of the top-gate structure TFT away from the base substrate, the first electrode and the gate electrode being formed by a single patterning process; and forming a second electrode on a side of a second gate insulating layer of the thin film transistor away from the base substrate, the second electrode and the compensation layer being formed by a single patterning process.
For example, processes of forming the compensation layer, the shielding layer, and the gate electrode are selected from chemical vapor deposition and physical vapor deposition, respectively.
Embodiments of the present disclosure also provide a display panel comprising the array substrate.
Embodiments of the present disclosure also provide a display panel comprising the array substrate manufactured by the method.
Embodiments of the present disclosure also provide a display device comprising the display panel.
Embodiments of the present disclosure also provide a method of improving performance of the array substrate, comprising: detecting intensity of a first electric field generated by the shielding layer in the active layer of the thin film transistor; and applying a voltage to the compensation layer to allow the compensation layer to form a second electric field in the active layer.
For example, the voltage applied to the compensation layer is about-15V to about 15V.
The technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.
Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms, such as ‘first,’ ‘second,’ or the like, which are used in the description and the claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but for distinguishing various components. The terms, such as ‘comprise/comprising,’ ‘include/including,’ or the like are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but not preclude other elements or objects. The terms, such as “connect/connecting/connected,” “couple/coupling/coupled” or the like, are not limited to a physical connection or mechanical connection, but may include an electrical connection/coupling, directly or indirectly. The terms, ‘on,’ ‘under,’ ‘left,’ ‘right,’ or the like are only used to indicate relative position relationship, and when the absolute position of the object which is described is changed, the relative position relationship may be changed accordingly.
The inventors noticed that in order to reduce the effect of the first electric field generated by the shielding layer on the active layer, an approach of changing the length of the shielding layer or additionally connecting a constant potential to the shielding layer is usually adopted to reduce the effect of the first electric field on the active layer and alleviate the problem of warping of the characteristic curve. However, the above-mentioned solution also may bring some negative effects, for example, affecting the threshold voltage of the device and causing the threshold voltage drift. Moreover, if a constant potential is additionally connected to the shielding layer, the shielding layer needs to be connected in the circuit, but the shielding layer is generally arranged at the lowermost layer of the array substrate (directly arranged on the surface of the base substrate), and holes need to be punched in some insulating layers so that the shielding layer is electrically connected through the viaholes, which increases the process complexity and have poor effect.
The inventors found through research that if a compensation layer is arranged on a side of the thin film transistor away from the shielding layer, a given voltage is applied to the compensation layer to form a second electric field in the active layer, and the electric field distribution of the active layer in the thin film transistor is changed through superposition of the first electric field and the second electric field, adverse effects of the first electric field on the active layer can be relieved or eliminated, and effects of the first electric field on characteristics of the thin film transistor can be compensated. In this way, the abnormal phenomenon of warping in the saturation region of the output characteristic curve can be improved or eliminated, the current can be normally output, while the adverse effect of compensating the change of the threshold voltage of the thin film transistor caused by the first electric field can be improved, as well as the problems of threshold voltage drift and the like can be solved, and the thin film transistor can be restored to a working state without the first electric field affecting the active layer, or even to a better level.
Embodiments of the present disclosure provide an array substrate. According to an embodiment of the present disclosure, referring to
It should be noted that the electric field generated by the shielding layer can act on the active layer, and the electric field at the active layer is the first electric field; the electric field generated by the compensation layer can act on the active layer, and the electric field at the active layer is a second electric field, i.e. the compensation layer forms a second electric field in the active layer in the thin film transistor. No restriction is required to the other conductive structure generating the electric field with the compensation layer, and it can be any conductive structure of the array substrate with an overlapping area between its orthographic projections on the base substrate and the orthographic projection of the compensation layer on the base substrate, such as conductive structures, such as data lines, electrodes and the like. It is also possible to arrange a conductive structure at a suitable position in the array substrate so that the orthographic projection of the conductive structure on the base substrate and the orthographic projection of the compensation layer on the base substrate have overlapping areas.
In the following, the effect of the first electric field on the threshold voltage will be described in detail: the existence of the first electric field will cause a slight change in the threshold voltage of the thin film transistor and a drift phenomenon occurs. For example, for a p-type thin film transistor, when the test voltage Vds=−0.1V, the generated first electric field has little effect on the threshold voltage of the thin film transistor, but, when the test voltage Vds=−10.1V, the generated first electric field will cause the threshold voltage of the thin film transistor to drift 0.2V to 0.4V toward the negative direction. For a N-type thin film transistor, its drift direction is opposite to the drift direction of the p-type thin film transistor, and its voltage drift is similar to the voltage drift of the p-type thin film transistor. However, according to embodiments of the present disclosure, the existence of the second electric field can compensate the adverse effect of the change of the threshold voltage of the thin film transistor caused by the first electric field, solve the problems of threshold voltage drift and the like, and restore the thin film transistor to a working state in which the first electric field does not affect the active layer, or even to a better level.
For example, in embodiments of the present disclosure, the types of substrate include, but are not limited to, glass substrate or polymer substrate. If the array substrate is applied to a flexible display panel, the surface 11 of the base substrate may also be provided with a flexible substrate made of an organic thin film, and may also include a barrier layer formed by silicon oxide, silicon nitride, or a stack of them to prevent water oxygen invasion and affect of charges.
For example, in an embodiment of the present disclosure, the material forming the shielding layer includes, but is not limited to, a metal or a metal alloy, such as molybdenum (Mo), aluminum (Al), molybdenum-tungsten (Mo—W) alloy, and the like. In this way, the use performance is high, and the shading effect on the active layer is good. When it is applied to a flexible display panel, the affect of moving charges on the bottom side of the flexible substrate (the flexible substrate is arranged on the side of the base substrate near the compensation layer, and the bottom side refers to the side of the flexible substrate near the base substrate) can also be effectively eliminated.
For example, in embodiments of the present disclosure, the shielding layer may be a single-layer structure or a multilayer structure. In this way, the shading effect is good and the application range is wide.
For example, in embodiments of the present disclosure, the thickness of the shielding layer is about 50 to about 100 nanometers. In this way, the use requirements of the shielding layer and the requirements on the overall thickness of the array substrate can be met.
According to the embodiment of the present disclosure, the structure of the thin film transistor can be any thin film transistor in the art. The following description will be set forth with thin film transistors in bottom-gate structure and top-gate structure as examples.
In some embodiments of the present disclosure, referring to
According to the embodiments of the present disclosure, the positional relationship between the compensation layer and the active layer can enable the electric field generated by the compensation layer to act on the active layer. In some embodiments of the present disclosure, in order to facilitate the compensation layer 40 to generate a second electric field in the active layer 31, referring to
In other embodiments of the present disclosure, referring to
According to embodiments of the present disclosure, for example, materials forming the gate electrode include, but are not limited to, metals or metal alloys, such as molybdenum, aluminum, molybdenum-tungsten (Mo—W) alloy, and the like. In this way, the use performance is high.
According to the embodiment of the present disclosure, for example, the structure of the gate electrode may be a single-layer structure or a multilayer stacked structure. In this way, the application range is wide and the selectivity is wide.
According to embodiments of the present disclosure, for example, the thickness of the gate electrode may be about 100 nm to about 500 nm, for example, the thickness of the gate electrode may be about 150 nm to about 400 nm. In this way, the use performance is high, and the requirement on the overall thickness of the array substrate can also be met.
According to embodiments of the present disclosure, for example, materials forming the active layer include, but are not limited to, amorphous silicon, poly-silicon, oxide semiconductor, and the like. In this way, the use performance is high, so that the thin film transistor has better and more stable electrical characteristics.
According to embodiments of the present disclosure, for example, the thickness of the active layer is about 10 nm to about 300 nm, for example, the thickness of the active layer is about 50 nm to about 100 nm. In this way, the use requirement for the active layer can be met, and the thinning of the array substrate is facilitated.
According to an embodiment of the present disclosure, for example, the material forming the buffer layer is selected from at least one of silicon oxide or silicon nitride. In this way, the use effect is good and the cost is low.
According to an embodiment of the present disclosure, for example, the thickness of the buffer layer is about 50 to 500 nanometers. In this way, the structure of each layer on the array substrate can be effectively allowed not to affect each other, and the thinning of the array substrate is facilitated.
According to an embodiment of the present disclosure, for example, the material forming the first insulating layer and the second insulating layer may be respectively selected from at least one of silicon oxide or silicon nitride. In this way, the material resource is extensive, the cost is low, and the processing is easy.
According to an embodiment of the present disclosure, for example, the thickness of the first insulating layer and the second insulating layer may be about 10 to about 200 nanometers, respectively. In some embodiments of the present disclosure, for example, for a thin film transistor with a top-gate structure, in order to facilitate hot electron injection into the active layer, the thickness of the first insulating layer may be designed to be thinner, for example, about 10 to about 40 nanometers; in other embodiments of the present disclosure, referring to
According to the embodiment of the present disclosure, the material forming the compensation layer makes it possible to apply a voltage thereto to generate an electric field. For example, materials forming the compensation layer include, but are not limited to, metals or metal alloys, such as molybdenum, aluminum, Mo—W alloy, and the like. In this way, the use performance is high, the compatibility with thin film transistors is good, and the resources are wide.
According to the embodiment of the present disclosure, for example, the compensation layer may be a single-layer structure or a multilayer stacked structure. In this way, the application range is wide and the selectivity is wide.
According to embodiments of the present disclosure, for example, the thickness of the compensation layer is about 100 nm to about 500 nm, for example, the thickness is about 150 nm to about 400 nm. In this way, the use performance is high, and the design requirement on the overall thickness of the array substrate can be met; and the thinner compensation layer reduces the bulge on the subsequent film layer and reduces the affect of unevenness of the film layer on the subsequent process.
According to the embodiments of the present disclosure, for the magnitude of the voltage applied to the compensation layer, those skilled in the art can design the magnitude of the voltage applied to the compensation layer according to the type of thin film transistor (such as N-type thin film transistor, or P-type thin film transistor), fabrication process and structure (such as the length and width of the channel, the thickness of the insulating layers and the dielectric coefficient of the insulating layer disposed between the compensation layer and the active layer, and the dielectric coefficient of the insulating layer between the shielding layer and the active layer) in the array substrate, or, for example, the intensity of the third electric field after the superposition of the first electric field and the second electric field may be stronger than or weaker than the first electric field, or the intensity of the first electric field may not be changed (i.e., the second electric field is zero), however, embodiments of the present disclosure are not limited thereto. In an embodiment of the present disclosure, the voltage of the compensation layer is about-15V to about 15V. In this way, the compensation layer can generate a second electric field with the required intensity in the active layer, and meet the requirements to the second electric field under various conditions, as well as change the electric field distribution of the active layer in the thin film transistor, so that the effect of the first electric field on the active layer can be alleviated or eliminated, and the effect of the first electric field on the characteristics of the thin film transistor can be compensated. In this way, the abnormal phenomenon of warping in the saturation region of the output characteristic curve can be improved or eliminated, and the current can be normally output, while the adverse effect of the change of the threshold voltage of the thin film transistor caused by the first electric field can also be improved and compensated, and the problems of threshold voltage drift and the like are resolved, so that the thin film transistor can be restored to a working state without the first electric field affecting the active layer, or even to a better level.
According to the embodiment of the present disclosure, as mentioned above, the magnitude of the voltage applied to the compensation layer is related to the thicknesses and dielectric coefficients of the insulating layers provided between the compensation layer and the active layer and between the shielding layer and the active layer. For example, for the thin film transistors of the above two types of structures, the magnitude of the voltage applied to the compensation layer is related to the thicknesses and dielectric coefficients of the first insulating layer, the second insulating layer and the buffer layer. The following description will be set forthwith the thin film transistor in the top-gate structure as an example.
As shown in
According to an embodiment of the present disclosure, as described above, the array substrate may further include a storage capacitor structure including a first electrode 51 and a second electrode 52. If that thin film transistor (TFT) is a thin film transistor with a bottom gate structure, referring to
In another aspect of the present disclosure, embodiments of the present disclosure also provide a method of manufacturing an array substrate. According to an embodiment of the present disclosure, referring to
According to embodiments of the present disclosure, for example, a process of forming the shielding layer includes, but is not limited to, chemical vapor deposition, such as vacuum evaporation; or physical vapor deposition, such as magnetron sputtering. In this way, the operation is simple and the industrial production is easy.
According to embodiments of the present disclosure, for example, the formed thin film transistor may be of a bottom-gate structure type or a top-gate structure type.
In some embodiments of the present disclosure, for example, the thin film transistor is of a bottom-gate structure type. Referring to
According to some embodiments of the present disclosure, for example, the thin film transistor is a top-gate structure. Referring to
According to embodiments of the present disclosure, for example, the processes of forming the buffer layer, the first gate insulating layer, the second gate insulating layer, and the gate electrode are respectively selected from chemical vapor deposition (such as plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance plasma chemical vapor deposition), and physical vapor deposition (such as magnetron sputtering), but the embodiments of the present disclosure are not limited thereto.
According to an embodiment of the present disclosure, for example, the method of forming the active layer is illustrated by using poly-silicon as the material for forming the active layer. Amorphous silicon can be formed by a plasma enhanced chemical vapor deposition process or a low pressure chemical vapor deposition process at a deposition temperature below 600 Celsius degrees, and then amorphous silicon is converted into polycrystalline silicon by deposition induced metal, heat treatment crystallization, excimer laser irradiation crystallization or doping impurity activation and other processes to form the active layer. After that, the poly-silicon can be further optimized by heat treatment and dehydrogenation, and then the source and drain regions of the active layer can be ion implanted. For example, for the top-gate structure, the source and drain regions of the active layer can be ion implanted using the gate electrode as a mask to form the source and drain regions. However, embodiments of the present disclosure are not limited thereto.
According to embodiments of the present disclosure, for example, the process of ion implantation includes, but is not limited to, ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation or solid diffusion implantation, etc. In some embodiments of the present disclosure, for example, the process of ion implantation is ion cloud implantation. For example, a mixed gas containing boron (e.g., B2H6/H2) or phosphorus (e.g., PH3/H2) can be used for implantation according to design requirements. The ion implantation energy can be about 10 to about 200 keV, for example, the energy is about 40 to about 100 keV, the implantation dose can be about 1×1011˜ to about 1×1020 atoms/cm3, and the dose is about 1×1014˜ to about 1×1018 atoms/cm3. In this way, the formed source and drain electrodes have better performance.
According to the embodiment of the present disclosure, when the thin film transistor is the bottom gate structure described above, for example, referring to
According to an embodiment of the present disclosure, when the thin film transistor is the top-gate structure described above, the structure refers to
According to embodiments of the present disclosure, for example, the processes of forming the compensation layer may be selected from chemical vapor deposition (such as plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance plasma chemical vapor deposition), and physical vapor deposition (such as magnetron sputtering). In this way, the operation is simple and the industrial production is easy.
The manufacturing method is simple and easy to operate, and is easy for industrial production; moreover, by applying a given voltage to the compensation layer, the compensation layer forms a second electric field in the active layer, and the second electric field changes the electric field distribution of the active layer in the thin film transistor after the second electric field is superposed with the first electric field, so that the effect of the first electric field on the active layer is relieved or eliminated, the effect of the first electric field on the device characteristics is compensated, and the abnormal phenomenon of warping in the saturation region of the output characteristic curve is improved or eliminated, which enables the current to be output normally, while the adverse effect of the change of the threshold voltage of the thin film transistor caused by the first electric field can be improved and compensated, and the problems of threshold voltage drift and the like can be resolved, so that the thin film transistor can be restored to a working state without the effect of the first electric field on the active layer, or even to a better level.
According to an embodiment of the present disclosure, the above method further includes the step of forming a storage capacitor structure, and the step of forming the storage capacitor structure includes forming a first electrode 51. If the thin film transistor is a TFT of a bottom-gate structure, the first electrode 51 is formed on a side of the buffer layer 32 in the TFT of the bottom-gate structure away from the base substrate 10 (see
According to the embodiment of the present disclosure, the above manufacturing method of the present application can be used to prepare the array substrate described above. The requirements on the forming materials and thicknesses of the buffer layer, the shielding layer, the first gate insulating layer, the second gate insulating layer, the gate electrode, the active layer, and the compensation layer are the same as those described above, and will not be repeated here.
Embodiments of the present disclosure also provide a display panel. According to an embodiment of the present disclosure, the display panel includes the above-mentioned array substrate or the array substrate prepared by the above-mentioned method. In this way, the display panel has stable electrical characteristics, high service performance, high reliability and long service life. Those skilled in the art can understand that the display panel has all the features and advantages of the above-mentioned array substrate and will not be repeated here.
Those skilled in the art can understand that in addition to the array substrate described above, the display panel also includes structures or components necessary for a conventional display panel, such as structures necessary for a conventional display panel such as a liquid crystal layer, a Color film substrate, sealant, and the like.
Embodiments of the present disclosure also provide a display device. According to an embodiment of the present disclosure, the display device includes the aforementioned display panel. In this way, the display device has stable electrical characteristics, high service performance, high reliability and long service life. Those skilled in the art can understand that the display device has all the features and advantages of the array substrate or display panel described above, and will not be repeated here.
According to an embodiment of the present disclosure, the display device includes, but is not limited to, any electronic device or wearable device having a display function, such as a mobile phone, a television, a tablet computer, a game machine, etc.
Those skilled in the art can understand that in addition to the aforementioned display panel, the display device can also include structures or components necessary for conventional display devices. For example, for a mobile phone, in addition to the aforementioned display panel, the mobile phone also includes structures necessary for a conventional mobile phone, such as a camera module, a voice control module, a fingerprint module, a Central Processor Unit (CPU), etc.
Embodiments of the present disclosure also provide a method for improving the performance of the array substrate described above. According to an embodiment of the present disclosure, referring to
The inventors found that by forming a second electric field in the active layer, the electric field distribution of the active layer in the thin film transistor is changed, so that the effect of the first electric field on the active layer is relieved or eliminated, and the effect of the first electric field on the characteristics of the thin film transistor is compensated. The abnormal phenomenon of warping in the saturation region of the output characteristic curve is improved or eliminated, and the current can be normally output, while the adverse effect of the change of the threshold voltage of the thin film transistor caused by the first electric field can be improved, the problems of threshold voltage drift and the like are resolved, and the thin film transistor can be restored to a working state without the effect of the first electric field on the active layer, or even to a better level.
According to the embodiments of the present disclosure, there is no restriction to the magnitude of the voltage applied to the compensation layer as long as the second electric field generated by the compensation layer can reduce the adverse effect of the first electric field on the active layer. Those skilled in the art can design the magnitude of the voltage applied to the compensation layer according to the specific types of thin film transistors in the array substrate (e.g., N-type TFT, or P-type TFT), specific preparation processes and structures (e.g., the length and width of the channel, the thicknesses and the dielectric coefficients of the insulating layers arranged between the compensation layer and the active layer and between the shielding layer and the active layer); or, in other words, the magnitude of the third electric field obtained by the superposition of the first electric field and the second electric field is not limited. That is to say, the intensity of the third electric field may be stronger than or weaker than the first electric field, or the intensity of the first electric field may not be changed (i.e., the second electric field is zero), and those skilled in the art may flexibly design according to the above actual processes or the specific structure of the TFT. In the embodiment of the present disclosure, the voltage applied to the compensation layer is −15V to 15V. In this way, the compensation layer can generate a second electric field with the required intensity in the active layer, meet the requirements for the second electric field under various conditions, and change the electric field distribution of the active layer in the thin film transistor, so that the effect of the first electric field on the active layer can be alleviated or eliminated, the effect of the first electric field on the characteristics of the thin film transistor can be compensated, and the abnormal phenomenon of warping in the saturation region of the output characteristic curve can be improved, so as to enable the current to be output normally, while the adverse effect of the change of the threshold voltage of the thin film transistor caused by the first electric field can be improved, the problems of threshold voltage drift and the like can be resolved, and the thin film transistor can be restored to a working state without the first electric field affecting the active layer, or even to a better level.
According to the embodiments of the present disclosure, as mentioned above, the magnitude of the voltage applied to the compensation layer is related to the thicknesses and dielectric coefficients of the insulating layer provided between the compensation layer and the active layer and the insulating layer between the shielding layer and the active layer. For the thin film transistors of the above two types of structures, the magnitude of the voltage applied to the compensation layer is related to the thicknesses and dielectric coefficients of the first insulating layer, the second insulating layer and the buffer layer. The following description will be set forth with the thin film transistor of the top-gate structure as an example:
As shown in
The following points should be noted:
The above description is only the exemplary embodiments of the present disclosure for explaining the principle of the present disclosure, and the scope of the present disclosure is not limited thereto. A person of ordinary skill in the art can make various changes and modifications without departing from the principle of the present disclosure, and such changes and modifications shall fall into the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201810394256.3 | Apr 2018 | CN | national |
This application is a continuation application of the U.S. application Ser. No. 16/462,385, which is a U.S. National Phase Entry of International Application No. PCT/CN2018/112065 filed Oct. 26, 2018, which claims the priority of Chinese patent application No. 201810394256.3 entitled “array substrate and method of manufacturing the same, application and method of improving performance of the same” filed to CNIPA on Apr. 27, 2018, the entire text of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16462385 | May 2019 | US |
| Child | 18373767 | US |
