Patent Application
20240363642
This application claims priority to Chinese Patent Application No. 202310466042.3, filed Apr. 27, 2023, titled “Array substrate, preparation method thereof and display device”, which is herein incorporated by reference in its entirety.
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a preparation method of the array substrate and a display device.
In recent years, a thin film transistor liquid crystal display (TFT-LCD) has become a mainstream display product due to advantages of low radiation, low power consumption, low space occupancy, light weight, and aesthetics.
At present, on a traditional array substrate, a data line is located between adjacent pixels to provide data signals to pixels. However, there is often a large lateral parasite capacitance Cpd between a data line and a pixel electrode. The lateral parasite capacitance Cp is prone to generate signal crosstalk, which is extremely unfavorable for improving refresh rate and resolution of the display device.
A first technical solution provided in the present disclosure is an array substrate. The array substrate includes a base substrate, a first metal layer, a first insulation layer, a second metal layer, a second insulation layer and a semiconductor layer. The first metal layer is arranged on a side of the base substrate. The first insulation layer is arranged on a side of the first metal layer away from the base substrate. The second metal layer is arranged on a side of the first insulation layer away from the base substrate. The second insulation layer is arranged on a side of the second metal layer away from the base substrate. The semiconductor layer is arranged on a side of the second insulating layer away from the base substrate. The first metal layer includes a data line. The second metal layer includes a gate, a scanning line, and a common electrode. The gate is electrically connected to the scanning line. A projection of the common electrode on the base substrate covers a projection of the data line on the base substrate. The semiconductor layer includes an active layer and a pixel electrode. The active layer includes a channel region, a source, and a drain to overlap with the gate to form a driving transistor. The source is electrically connected to the data line through a conductive via hole, and the pixel electrode is electrically connected to the drain.
A second technical solution provided in the present disclosure is a preparation method of an array substrate. The preparation method includes the following operations. Providing a base substrate; preparing a first metal layer on a side of the base substrate and patterning the first metal layer to form a data line. Preparing a first insulation layer on a side of the first metal layer away from the base substrate. Preparing a second metal layer on a side of the first insulation layer away from the base substrate, and patterning the second metal layer to form a gate, a scanning line, and a common electrode; the gate is electrically connected to the scanning line, and a projection of the common electrode on the base substrate covers a projection of the data line on the base substrate. Preparing a second insulation layer on a side of the second metal layer away from the base substrate. Preparing a semiconductor layer on a side of the second insulation layer away from the base substrate, and forming a pixel electrode and an active layer on the semiconductor layer; and allowing the active layer to include a channel region, a source, and a drain, so as to overlap with the gate to form a driving transistor; the source is electrically connected to the data line through a conductive via hole, and the pixel electrode is electrically connected to the drain.
A third technical solution provided in the present disclosure is a display device. The display device includes a display panel and a backlight module. The display panel is configured to display an image. The display panel includes the array substrate as described above, or prepared by the preparation method as described above. The backlight module is arranged opposite to the display panel, and is configured to provide backlight to the display panel.
In order to provide a clearer explanation of the technical solution in embodiments of the present disclosure, a brief introduction will be given to the accompanying drawings required in the description of the embodiments. It is evident that the accompanying drawings in the following description are only some embodiments of the present disclosure. For ordinary technical personnel in the art, other accompanying drawings may be obtained based on these drawings without any creative efforts.
The following is a detailed explanation of technical solutions in embodiments of the present disclosure, combined with the accompanying drawings of the specification.
In the following description, specific details such as specific system structure, interfaces, technologies, etc., are proposed for the purpose of illustration rather than limitation, in order to fully understand the present disclosure.
The following will provide a clear and complete description of the technical solution in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technical personnel in the art without creative efforts fall within the protection scope of the present disclosure.
The terms “first,” “second,” and “third” in the present disclosure are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implying the quantity of technical features indicated. Therefore, features limited to “first”, “second”, and “third” may explicitly or implicitly include at least one of these features. In the description of the present disclosure, “multiple” means at least two, such as two, three, etc., unless otherwise specified. All directional indications (such as up, down, left, right, front, rear . . . ) in the embodiments of the present disclosure are only configured to explain the relative position relationship, motion situation, etc., between components in a specific posture (as shown in the attached drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms “including” and “having”, as well as any variations of them, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of operations or units is not limited to the listed operations or units, but optionally includes operations or units that are not listed, or optionally includes other operations or units that are inherent to these processes, methods, products, or devices.
The reference to “embodiment” in the present disclosure means that specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present disclosure. The phrase appearing in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. Ordinary technical personnel in the art explicitly and implicitly understand that the embodiments described in the present disclosure may be combined with other embodiments.
The following provides a detailed explanation of the present disclosure in conjunction with the accompanying drawings and embodiments.
As illustrated in
In some embodiments, the base substrate 10 is configured to carry and protect various components and signal wirings on the array substrate 101. The base substrate 10 may be a rigid substrate or a flexible substrate. The base substrate 10 may be specifically made of a material with insulation and high temperature resistance, such as glass, resin or polyimide.
In some embodiments, the first metal layer 20 is arranged on a side of the base substrate 10. The first metal layer 20 includes a plurality of data lines 21. The plurality of data lines 21 are spaced and parallel and are configured to transmit data drive signals.
The second metal layer 40 includes a gate 42, multiple scanning lines 41, and a common electrode 43. The multiple scanning lines 41 are spaced and parallel. A projection of the scanning lines 41 on the base substrate 10 is perpendicular to a projection of the data line 21 on the base substrate 10, forming multiple subpixel regions arranged in an array. Each subpixel region corresponds to a driving transistor. The gate 42 of the second metal layer 40 is the gate 42 of the driving transistor. The gate 42 is electrically connected to the corresponding scanning lines 41, so as to enable the scanning lines 41 to transmit scanning driving signals to the driving transistor. A projection of the common electrode 43 on the base substrate 10 covers the projection of the data line 21 on the base substrate 10.
The semiconductor layer 60 includes an active layer 61 and a pixel electrode 62. The active layer 61 includes a channel region 611, a source 612, and a drain 613. The active layer 61 is overlapped with the gate 42 to form the aforementioned driving transistor. The source 612 is electrically connected to the data line 21 through a conductive via hole 51 running through the first insulation layer 30 and the second insulation layer 50, and the drain 613 is electrically connected to the pixel electrode 62, so as to form a pixel driving circuit. In some embodiments, the source 612 covers the conductive via hole 51, so as to be electrically connected to the data line 21, thus saving a process of arranging a conductive layer inside the conductive via hole 51.
In the present embodiment, the first metal layer 20 includes the data line 21, the semiconductor layer 60 includes the pixel electrode 62, and the second metal layer 40 where the common electrode 43 is arranged between the first metal layer 20 and the semiconductor layer. Therefore, a distance between the data line 21 and the pixel electrode 62 is increased, effectively reducing the parasitic capacitance Cpd between the data line 21 and the pixel electrode 62, without the need for an additional film layer or an additional process. Further, the common electrode 43 is arranged between the data line 21 and the pixel electrode 62, and the projection of the common electrode 43 on the base substrate 10 covers the projection of the data line 21 on the base substrate 10, resulting in that the common electrode 43 covers and is above the data line 21, which may basically shield all parasitic capacitance between the data line 21 and the pixel electrode 62, thereby improving the shielding effect between the data line 21 and the pixel electrode 62. This effectively reduces the signal crosstalk caused by the parasitic capacitance to the pixel electrode 62, and facilitates to improve the refresh rate and the resolution of the display device. In addition, the semiconductor layer 60 includes the pixel electrode 62 and the active layer 61, and the active layer 61 includes the channel region 611, the source 612, and the drain 613. The active layer 61 overlaps with the gate 42 to form a driving transistor, the channel region 611, the source 612, and the drain 613 of the driving transistor are arranged in a same layer as the pixel electrode 62. It not only reduces the number of via holes and film layers, but also simplifying a manufacturing process of array substrate 101 through a same preparation process, improving production efficiency and reducing production costs.
As shown in
In the present embodiment, the channel region 611, the source 612, and drain 613 are an integrated structure, and the materials of the source 612 and the drain 613 are the same as that of channel region 611 through conductive treatment, such that a pattern of the channel region 611, the source 612, and the drain 613 may be patterned in a same process. The source 612 and the drain 613 only need to be one-step formed with the channel region 611. There is no need to reserve additional space for machine alignment accuracy for the preparation of source 612 and drain 613, and there is no deviation between design values of the source 612 and the drain 613 and their actual values. Therefore, a length of the channel region 611 may be effectively reduced, thereby reducing a size of the driving transistor and improving a pixel opening rate. The traditional array substrate 101, the source 612 and the drain 613 require additional metal patterns to be formed, and are prepared through different processes with channel region 611. Therefore, when preparing the source 612 and the drain 613, it is necessary to consider the machine alignment accuracy and the deviation between the design values and their actual values. As a result, for the channel length, there is a need to reserve a certain space to solve the alignment problem, such that the length of channel region 611 is not capable of being reduced. At the same time, in order to ensure that a TFT has a large on state current, a TFT size is usually arranged to be large, which will occupy some of the opening area, limiting the improvement of the opening ratio. Even if the metal oxide semiconductor with high electron mobility (such as IGZO) is adopted, the channel length of the TFT will still be greater than 6 μm, which is not able to significantly reduce the size of the TFT, and the improvement of the pixel opening ratio is relatively limited. The embodiments of the present disclosure may solve the technical problem through the above settings, effectively reducing the length of the channel region 611 and reducing the size of the driving transistor while ensuring a large open state current of the driving transistor, thereby significantly improving the pixel opening rate.
In some embodiments, a length range of the channel region 611 may be from 1.5 to 5.0 μm, which means that the length of the channel region 611 may even below 2.5 μm, significantly reducing the size of the driving transistor and effectively improving the pixel opening rate. In some embodiments, the length of channel region 611 may be 1.5 μm, 1.7 μm, 2.0 μm, 2.3 μm, 2.5 μm, 2.7 μm, 2.9 μm, 3.0μ, 3.2 μm, 3.5 μm, 3.7 μm, 3.9 μm, 4.0 μm, 4.2 μm, 4.4 μm, 4.6 μm, 4.8 μm, 4.9 μm or 5.0 μm, which may be set according to actual needs without specific restrictions.
In some embodiments, the pixel electrode 62 and the active layer 61 are arranged in the same layer. The material of the pixel electrode 62 is also a conductive metal oxide semiconductor. Therefore, the pixel electrode 62 and the active layer 61 may be formed through a same photomask patterning, which may reduce an additional process of preparing the pixel electrode 62. The pixel electrode 62 and the drain 613 may also be electrically connected through patterned wiring in a same process, without the need for cross layer connections through holes, which improves reliability of electrical connections. Meanwhile, due to the patterning of the pixel electrode 62 and the active layer 61 through the same photomask process, there is no need to consider the issue of the alignment accuracy or deviation between the design values and the actual values of the electrical connection between the pixel electrode 62 and the drain 613, which may further improve the pixel opening rate.
In some embodiments, the array substrate 101 also includes a passivation protection layer 70. The passivation protection layer 70 is arranged on a side of the semiconductor layer 60 away from the base substrate 10. The passivation protection layer 70 covers the semiconductor layer 60, so as to protect the active layer 61 and the pixel electrode 62 of the semiconductor layer 60, preventing a performance of the source layer 61 and the pixel electrode 62 from being affected by external water and oxygen. And in particular, the passivation protection layer 70 prevents the channel region 611 from being affected by water and oxygen, which may lead to conduction of the channel region 611, thus affecting switching effect of the driving transistor.
As shown in
As illustrated in
In some embodiments, the display panel 100 includes an array substrate 101, a counter substrate 102, and a dielectric layer 103. The display panel 100 is arranged opposite to the counter substrate 102, forming a closed storage space. The dielectric layer 103 is arranged in the storage space. The dielectric layer 103 may be a liquid crystal layer or an electrophoretic layer, and a driving electric field may be formed between the array substrate 101 and the counter substrate 102 to drive the liquid crystal layer to rotate or charged particles in the electrophoretic layer to move, thereby displaying an image.
In some embodiments, a specific structure and function of the array substrate 101 is the same or similar to a specific structure and function of the array substrate 101 mentioned in the previous embodiments, and may achieve the same technical effect. Details of the introduction are illustrated above, and will not be repeated here. The specific preparation method of the array substrate 101 may be obtained through the following operations. Please refer to the specific instructions below for the specific preparation method, which will not be introduced here.
The display device according to some embodiments may effectively reduce the parasitic capacitance between the pixel electrode 62 and the data line 21, reduce the signal crosstalk, and facilitate to improve the refresh rate and resolution of the display device. Meanwhile, it may increase the open state current of the driving transistor, reduce the size of the driving transistor, and significantly improve the pixel opening rate.
As illustrated in
S1: providing a base substrate 10.
S2: preparing a first metal layer 20 on a side of the base substrate 10 and patterning the first metal layer 20, to form a data line 21.
S3: preparing a first insulation layer 30 on a side of the first metal layer 20 away from the base substrate 10.
S4: preparing a second metal layer 40 on a side of the first insulation layer 30 away from the base substrate 10, and patterning the second metal layer 40 to form a gate 42, a scanning line 41, and a common electrode 43. The gate 42 is electrically connected to the scanning line 41, and a projection of the common electrode 43 on the base substrate 10 covers a projection of the data line 21 on the base substrate 10.
S5: preparing a second insulation layer 50 on a side of the second metal layer 40 away from the base substrate 10.
S6: preparing a semiconductor layer 60 on a side of the second insulation layer 50 away from the base substrate 10, and forming a pixel electrode 62 and an active layer 61 on the semiconductor layer 60. The active layer 61 includes a channel region 611, a source 612, and a drain 613, which are overlapped with the gate electrode 42 to form a driving transistor. The source 612 is electrically connected to the data line 21 through a conductive via hole 51, and the pixel electrode 62 is electrically connected to the drain 613.
In some embodiments, the patterning method involved in the above operations may be achieved through photomask exposure, development, etching, and photoresist stripping, or by photomask evaporation, which may be selected as needed.
The structure and function of the data line 21 and the scanning line 41 are the same or similar to that of the data line 21 mentioned in the previous embodiments, and may achieve the same technical effect. For details, please refer to the specific introduction above, which will not be repeated here. The materials of the data line 21, the scanning line 41, the gate 42, and the common electrode 43 may be Mo/Cu, Ti/Cu, Mo/Al/Mo, Al/Mo, or Mo/Ti/Cu, and their thickness and shape may be arranged according to actual needs.
The first insulation layer 30 and the second insulation layer 50 are configured to isolate adjacent metal layers, such that short circuits between adjacent metal layers may be avoided. Materials of the first insulation layer 30 and the second insulation layer 50 may be silicon nitride or silicon oxide, and their thickness may be arranged according to actual needs.
In some embodiments, by forming the data line 21 on the first metal layer 20, the scanning line 41, the gate 42, and the common electrode 43 on the second metal layer 40, and forming the pixel electrode 62 and the active layer 61 on the semiconductor layer 60, a distance between the data line 21 and the pixel electrode 62 is increased. Therefore, the parasitic capacitance Cpd between the data line 21 and the pixel electrode 62 is effectively reduced, without the need for an additional film layer or an additional process. Further, by arranging the common electrode 43 between the data line 21 and the pixel electrode 62, and covering the common electrode 43 above the data line 21, all parasitic capacitances between the data line 21 and the pixel electrode 62 may be basically shielded, which improves the shielding effect between the data line 21 and the pixel electrode 62, thus effectively reducing the signal crosstalk caused by the parasitic capacitance to the pixel electrode 62, and facilitates to improving the refresh rate and resolution of the display device. In addition, a pixel electrode 62 and an active layer 61 are formed in the semiconductor layer 60, and the active layer 61 includes the channel region 611, the source 612, and the drain 613, so as to overlap with the gate electrode 42 to form the driving transistor. The channel region 611, the source 612, and the drain 613 of the driving transistor are arranged in the same layer as the pixel electrode 62, which not only reduces the number of via holes and film layers, but also simplifies the process of array substrate 101 through the same process of preparation, improving production efficiency and reducing production costs.
In some embodiments, the patterning processing of the pixel electrode 62, the channel region 611, the source 612, and the drain 613 may be achieved in the same process through photomask, which not only reduces the processes and the use of photomask, but also eliminates the need to reserve space for the separate preparation of the pixel electrode 62, the source 612, and the drain 613 to consider the accuracy of machine alignment. There will also be no deviation between the design values of the positions of the source 612 and the drain 613 and their actual values, which may effectively reduce the length of the channel region 611, thereby reducing the size of the driving transistor and improving the pixel opening rate.
As illustrated in
S61: depositing an oxide semiconductor layer 601 on a side of the second insulation layer 50 away from the base substrate 10.
S62: dividing the oxide semiconductor layer 601 into a pixel electrode region 620 and an active layer region 610, and further dividing the active layer region 610 into a channel region 6110, a source area 6120, and a drain area (not shown in the drawings). The channel region 6110, the source area 6120, and the drain area are connected as a whole region.
S63: patterning the oxide semiconductor layer 601 according to the divided area, and retaining a photoresist layer on the pattern, such that a thickness of the photoresist layer covering the channel region 6110 is greater than that covering other areas.
S64: removing the photoresist layer covering other areas to expose a partial oxide semiconductor layer 601 on the pixel electrode region 620, the source electrode area 6120, and the drain electrode area.
S65: conducting the exposed oxide semiconductor layer 601 to form the pixel electrode 62, the source 612, and the drain 613.
S66: removing the remaining photoresist layer.
In some embodiments, a two-tone method is adopted. The first operation is coating and patterning the oxide semiconductor layer 601 to form the patterned active layer 61 and the pixel electrode 62. The second operation is performing conduction treatment on the oxide semiconductor layer 601 outside the channel region 6110, so as to form the conductive pixel electrode 62, the source 612, and the drain 613.
In some embodiments, after coating and patterning the oxide semiconductor layer 601, the photoresist is retained and may be exposed through a semi-transparent photomask, such that a thickness of the photoresist above the channel region 611 is greater than that of the photoresist in other regions. The photoresist may be either positive or negative, and may be selected according to actual needs. The thickness of the photoresist above channel region 611 is greater than that of the photoresist in other regions. In the second operation, operation S64, when removing the photoresist, the thickness of the photoresist above channel region 611 is greater than that of the photoresist in other regions, such that a certain thickness of photoresist layer may still be retained above the channel region 611. Therefore, in subsequent operations, when performing conduction treatment on the oxide semiconductor layer 601 of other regions does not affect the channel region 611, and will not cause the conduction of the channel region 611. In some embodiments, the conduction treatment may be carried out by dry etching with ion bombardment or ion implantation to improve conductivity of the pixel electrode 62, the source 612, and the drain 613.
In some embodiments, the material of the oxide semiconductor layer 601 may be a metal oxide semiconductor material, such as amorphous indium gallium zinc oxide (IGZO), amorphous indium gallium tin oxide (IGTO), amorphous indium tin zinc oxide (ITZO), or amorphous indium gallium zinc tin oxide (IGZTO), etc., which may be arranged according to actual needs without specific limitations.
By adopting metal oxide semiconductor as the material of the oxide semiconductor layer 601, not only the open state current of the driving transistor may be significantly increased, but also the length of the channel region 611 and the size of the driving transistor may be reduced, thereby effectively improving the pixel opening rate. In some embodiments, by adopting the above method, the length of the channel region 611 may be reduced to 1.5-5.0 μm, or even below 2.5 μm, such as 5.0 μm, 4.9 μm, 4.8 μm, 4.6 μm, 4.4 μm, 4.2 μm, 4.0 μm, 3.9 μm, 3.7 μm, 3.5 μm, 3.2 μm, 3.0 μm, 2.9 μm, 2.7 μm, 2.5 μm, 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, or 1.5 μm, etc., which may effectively reduce the size of the driving transistor, thereby significantly improving the pixel opening rate.
In some embodiments, the data line 21 includes the first part 211 and the second part 212 (as shown in
Therefore, after operation S5, an operation of arranging the conductive via hole 51 is also included.
Forming the conductive via hole 51 on the second insulation layer 50, and making the conductive via hole 51 penetrate the second insulation layer 50 and the first insulation layer 30, and electrically connecting the conductive via hole 51 to the data line 21.
At operation S6, it is also necessary to extend the source 612 of the driving transistor to the conductive via hole 51, such that the source 612 is electrically connected to the data line 21 through the conductive via hole 51. In some embodiments, by extending the source 612 and covering the conductive via hole 51 to be electrically connected to the data line, the process of arranging a conductive layer inside the conductive via hole 51 may be saved.
Through the above operations, without affecting the shielding effect of the common electrode 43, the common electrode 43 does not cover the part of the data line 21 corresponding to the driving transistor to expose the data line 21, thus the electrical connection between the data line 21 and the source 612 is achieved through the conductive through hole 51.
Furthermore, the preparation method includes the following operations.
S7: preparing a passivation protective layer 70 on a side of the semiconductor layer 60 away from the base substrate 10.
By arranging a passivation protection layer 70 and covering the active layer 61 and pixel electrode 62 with the passivation protection layer 70, the active layer 61 and pixel electrode 62 of the semiconductor layer 60 are protected to prevent external water and oxygen from affecting the performance of the active layer 61 and pixel electrode 62, especially the performance of the channel region 611. This prevents the channel region 611 from being affected by water and oxygen, which may lead to conduction of the channel region 611 and affecting the switching effect of the driving transistor, thereby ensuring the stability of the performance of the driving transistor.
The above are only some embodiments of the present disclosure and do not limit the protection scope of the present disclosure. Any equivalent structure or equivalent process transformation made using the description and accompanying drawings of the present disclosure, or directly or indirectly applied in other related technical fields, are equally included in the protection scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310466042.3 | Apr 2023 | CN | national |
