Patent Application
20220122558
The present disclosure relates to the field of display technology, and in particular to an array substrate row drive circuit unit, a drive circuit and a liquid crystal display panel thereof.
The following statements only provide information related to the present disclosure, and do not necessarily constitute prior art.
Gate Driver on Array (GOA) technology is an array substrate row drive technology, which uses the original array manufacturing process of the liquid crystal display panel to fabricate the drive circuit of the horizontal scan line on the substrate around the display area, so that it can replace the external integrated circuit (IC) board to complete the driving of the horizontal scan line. GOA technology can reduce the bonding process of external ICs, and has the opportunity to increase production capacity and reduce product costs, and can make LCD panels more suitable for manufacturing narrow-frame or borderless display products.
In the related art, part of the external integrated circuit (Gate IC) for gate drive can output the output signal waveform with two falling edges to reduce the feed-through voltage, but it is not suitable for GOA circuits. The GOA circuit in the related art can only output an output signal with one falling edge. Before and after the gate of the Thin Film Transistor (TFT) is turned off, the constant voltage high potential (VGH) is directly reduced to the constant voltage low potential (VGL). In addition, the feed-through voltage during charging of the pixels of the liquid crystal display panel cannot be reduced, which is not conducive to improving the display uniformity of the liquid crystal panel.
The present disclosure provides an array substrate row drive circuit unit, an array substrate row drive circuit is formed by cascading multiple stages of array substrate row drive circuit units, the array substrate row drive circuit unit includes:
a pull-up control module for outputting a pull-up control signal when receiving a DC high voltage signal and a stage transmission signal;
a pull-up module electrically connected to the pull-up control module, and for outputting a row scan signal of the array substrate row drive circuit unit of a current stage when receiving the pull-up control signal and a high-frequency clock signal;
a pull-down module connected to the pull-up control module and the pull-up module, and for simultaneously pulling down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to a low level according to a DC low voltage signal when receiving the row scan signal; and
a voltage dividing module electrically connected to the pull-up module, and for increasing a falling edge during pull-down when the pull-down module simultaneously pulls down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to the low level.
The present disclosure further provides an array substrate row drive circuit, the array substrate row drive circuit includes multiple stages of array substrate row drive circuit units, and the multiple stages of the array substrate row drive circuit units are cascaded to form the array substrate row drive circuit, each of the array substrate row drive circuit units charges a corresponding stage of horizontal scan lines in a display area, and each of the array substrate row drive circuit units includes:
a pull-up control module for outputting a pull-up control signal when receiving a DC high voltage signal and a stage transmission signal;
a pull-up module electrically connected to the pull-up control module, and for outputting a row scan signal of the array substrate row drive circuit unit of a current stage when receiving the pull-up control signal and a clock signal;
a plurality of pull-down modules, each of the pull-down modules is connected to a low-frequency signal, the pull-up control module, the pull-up module, and a DC low voltage signal, the plurality of pull-down modules are for simultaneously pulling down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to a low level according to the DC low voltage signal when receiving the row scan signal; and
a voltage dividing module electrically connected to the pull-up module, and for increasing a falling edge during pull-down when the pull-down module simultaneously pulls down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to the low level.
The present disclosure further provides a liquid crystal display panel, the liquid crystal display panel includes an integrated circuit and an array substrate row drive unit, an output terminal of the integrated circuit is electrically connected with the array substrate row drive unit, the array substrate row drive circuit includes multiple stages of array substrate row drive circuit units, and the multiple stages of the array substrate row drive circuit units are cascaded to form the array substrate row drive circuit, the array substrate row drive circuit unit charges a corresponding stage of horizontal scan lines in a display area, and the array substrate row drive circuit unit includes:
a pull-up control module for outputting a pull-up control signal when receiving a DC high voltage signal and a stage transmission signal;
a pull-up module electrically connected to the pull-up control module, and for outputting a row scan signal of the array substrate row drive circuit unit of a current stage when receiving the pull-up control signal and a high-frequency clock signal;
a plurality of pull-down modules, each of the pull-down modules is connected to a low-frequency signal, the pull-up control module, the pull-up module, and a DC low voltage signal, the plurality of pull-down modules are for simultaneously pulling down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to a low level according to the DC low voltage signal when receiving the row scan signal; and
a voltage dividing module electrically connected to the pull-up module, and for increasing a falling edge during pull-down when the pull-down module simultaneously pulls down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to the low level.
In technical solutions of the present disclosure, when receiving the row scan signal, the pull-down module simultaneously pulls down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to a low level according to the DC low voltage signal. During the process of pulling down, the voltage dividing module is increased. Through the voltage dividing function of the voltage dividing module, when the pull-down module pulls down the pull-up control signal and the row scan signal of the array substrate row drive circuit unit of the current stage to a low level simultaneously, the number of falling edges is increased, such that the row scan signal descends stepwise, and the waveform output by the array substrate row drive circuit unit of the current stage has two falling edges, to reduce the difference between the high potential and the low potential, and reduce the feed-through voltage of the pixel, thereby improving the uniformity of the liquid crystal display panel.
In order to more clearly illustrate the embodiments of the present disclosure, drawings used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. It will be apparent to those skilled in the art that other figures can be obtained according to the structures shown in the drawings without creative work.
The realization of the objective, functional characteristics, and advantages of the present disclosure are further described with reference to the accompanying drawings.
The technical solutions of the embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. It is obvious that the embodiments to be described are only some rather than all of the embodiments of the present disclosure. All other embodiments obtained by persons skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of the present disclosure.
It should be noted that if there is a directional indication (such as up, down, left, right, front, rear . . . ) in the embodiments of the present disclosure, the directional indication is only used to explain the relative positional relationship, movement, etc. of the components in a certain posture (as shown in the drawings). If the specific posture changes, the directional indication will change accordingly.
Besides, the descriptions associated with, e.g., “first” and “second,” in the present disclosure are merely for descriptive purposes, and cannot be understood as indicating or suggesting relative importance or impliedly indicating the number of the indicated technical feature. Therefore, the feature associated with “first” or “second” can expressly or impliedly include at least one such feature. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the realization of those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist, nor is it within the scope of the present disclosure.
As shown in
a pull-up control module 10 for outputting a pull-up control signal Q(N) when receiving a direct current (DC) high voltage signal Vdd and a stage transmission signal;
a pull-up module 20 electrically connected to the pull-up control module 10, and for outputting a row scan signal G(N) of the array substrate row drive circuit unit of a current stage when receiving the pull-up control signal Q(N) and a high-frequency clock signal HCK;
a pull-down module 30 connected to the pull-up control module 10 and the pull-up module 20, and for simultaneously pulling down the pull-up control signal Q(N) and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to a low level according to a DC low voltage signal VSS when receiving the row scan signal G(N); and
a voltage dividing module 40 electrically connected to the pull-up module 20, and for increasing a falling edge during pull-down when the pull-down module 30 simultaneously pulls down the pull-up control signal Q(N) and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to the low level.
Since the array substrate row drive circuit is formed by cascading multiple stages of array substrate row drive circuit units, the array substrate row drive circuit unit of the current stage charges the corresponding stage of horizontal scan lines in the display area. As shown in
The pull-up module 20 is electrically connected to the pull-up control module 10, and receives the pull-up control signal Q(N) and the clock signal HCK output by the pull-up control module 10, and outputs the row scan signal G(N) of the array substrate row drive circuit unit of the current stage according to the pull-up control signal Q(N) and the clock signal HCK. The pull-up module 20 includes a sixth field effect transistor T6, a source of the sixth field effect transistor T6 is connected to the clock signal HCK, a gate of the sixth field effect transistor T6 is electrically connected to a pull-up control signal Q(N) output by the pull-up control module 10 of the current stage, and a drain of the sixth field effect transistor T6 outputs the row scan signal G(N) of the array substrate row drive circuit unit of the current stage.
As shown in
The pull-down module 30 is electrically connected to the pull-up control module 10 and the pull-up module 20. When receiving the row scan signal G(N) output by a second array substrate row drive circuit unit Q(N−2), the pull-down module 30 pulls down the pull-up control signal Q(N) output by the pull-up control module 10 and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to a low level simultaneously according to the DC low voltage signal VSS, such that the pull-up control signal Q(N) output by the pull-up control module 10 and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage are maintained in a closed state. The pull-down module 30 includes a second field effect transistor T2, a third field effect transistor T3, and a fourth field effect transistor T4. A source of the second field effect transistor T2, a source of the third field effect transistor T3, and a source of the fourth field effect transistor T4 are respectively connected to a DC low voltage signal VSS. A gate of the second field effect transistor T2, a gate of the third field effect transistor T3, and a gate of the fourth field effect transistor T4 are electrically connected to each other. A drain of the second field effect transistor T2 is electrically connected to one end of the pull-up module 20 that outputs the row scan signal G(N) of the array substrate row drive circuit unit of the current stage. A drain of the third field effect transistor T3 is electrically connected to the stage transmission signal output by the stage transmission module 60. A drain of the fourth field effect transistor T4 is electrically connected to one end of the pull-up control module 10 that outputs the pull-up control signal Q(N).
The voltage dividing module 40 is electrically connected to the pull-up module 20 and connected to the DC low voltage signal VSS, and increases the number of falling edges when the row scan signal is pulled down according to a falling edge generation signal KF when the pull-down module 30 pulls down the pull-up control signal Q(N) and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to a low level simultaneously, such that the row scan signal descends stepwise.
It should be noted that the second array substrate row drive circuit unit is an array substrate row drive circuit unit located at the previous stage of the current stage array substrate row drive circuit unit. The first array substrate row drive circuit unit is an array substrate row drive circuit unit located at the previous stage of the second array substrate row drive circuit unit.
In technical solutions of the present disclosure, when receiving the row scan signal G(N), the pull-down module 30 simultaneously pulls down the pull-up control signal Q(N) and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to a low level according to the DC low voltage signal VSS. During the process of pulling down, the voltage dividing module 40 is added. Through the voltage dividing function of the voltage dividing module 40, when the pull-down module 30 pulls down the pull-up control signal Q(N) and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to a low level simultaneously, the number of falling edges is increased, such that the row scan signal descends stepwise, and the waveform output by the array substrate row drive circuit unit of the current stage has two falling edges, to reduce the difference between the high potential and the low potential, and reduce the feed-through voltage of the pixel, thereby improving the uniformity of the liquid crystal display panel.
In an embodiment, an electronic component is the first field effect transistor T1, a gate of the first field effect transistor T1 is for receiving the falling edge generation signal KF, a drain of the first field effect transistor T1 is for receiving a DC low voltage signal VSS through the voltage divider, a source of the first field effect transistor T1 is electrically connected to the pull-up module 20 to increase the number of falling edges of the row scan signal G(N) output by the pull-up module 20.
When receiving the falling edge generation signal KF, the first field effect transistor T1 increases the number of falling edges of the row scan signal during the process of pulling down according to the falling edge generation signal KF when the pull-down module 30 pulls down the pull-up control signal Q(N) and the row scan signal G(N) of the array substrate row drive circuit unit of the current stage to a low level simultaneously. It should be noted that the first field effect transistor T1 can also be a thin film transistor, the voltage divider is a diode, a positive electrode of the voltage divider is connected to the drain of the first field effect transistor T1, and a negative electrode of the voltage divider is connected to the DC low voltage signal VSS. Since the diode has the technical feature that only allows current to flow in a single direction, if the current flows in the reverse direction, the diode will be turned off, when the input falling edge generation signal KF is high, the signal output from the first field effect transistor T1 is high, the voltage divider can turn on the signal output by the first field effect transistor T1 to input the DC low voltage signal VSS. When the input falling edge generation signal KF is low, the signal output by the first field effect transistor T1 is low, and the diode cannot be turned on.
In an embodiment, as shown in
In order to increase the service life of the components, the two pull-down modules 30 are driven in turn to slow down the damage of the components and increase the service life of the components. The number and connection methods of the components in the two pull-down modules 30 are the same. The difference is that the low-frequency signals connected to the two pull-down modules 30 are different. The two pull-down modules 30 are divided into a first pull-down module 31 and a second pull-down module 32. The first pull-down module 31 is connected to the first low-frequency signal LC1, and the first pull-down module 31 is simultaneously connected to the pull-up control module 10, the pull-up module 20, and the DC low voltage signal VSS. According to the first low frequency signal LC1 and the DC low voltage signal VSS, the pull-up control signal Q(N) and the row scan signal G(N) of the current stage are maintained in the off state. The second pull-down module 32 is connected to the second low-frequency signal LC2, and the second pull-down module 32 is simultaneously connected to the pull-up control module 10, the pull-up module 20, and the DC low voltage signal VSS. According to the second low-frequency signal LC2 and the DC low voltage signal VSS, the pull-up control signal Q(N) and the row scan signal G(N) of the current stage are maintained in the off state.
It should be noted that when the first low-frequency signal LC1 is connected to the first pull-down module 31, it needs to flow through the ninth field effect transistor T9 and the eighth field effect transistor body T8. A drain of the eighth field effect transistor body T8 is connected to the gate of the second field effect transistor T2, the gate of the third field effect transistor T3 and the gate of the fourth field effect transistor T4. A source and gate of the ninth field effect transistor T9 and the source of the eighth field effect transistor body T8 are simultaneously connected to the first low-frequency signal LC1. A drain of the ninth field effect transistor T9 is connected to the gate of the eighth field effect transistor body T8. The circuit connection mode of the second pull-down module 32 is the same as the circuit connection mode of the first pull-down module 31.
In an embodiment, as shown in
In an embodiment, the array substrate row drive circuit unit further includes a pull-down holding module 50 electrically connected to the pull-up module 20 and the pull-up control module 10.
As shown in
In an embodiment, the pull-down holding module includes a fourteenth field effect transistor T14 and a fifteenth field effect transistor T15. A gate of the fourteenth field effect transistor T14 and a gate of the fifteenth field effect transistor T15 are connected to each other, and are connected to the row scan signal G(N+4) output by the pull-up module of the third array substrate row drive circuit unit. A source of the fourteenth field effect transistor T14 and a source of the fifteenth field effect transistor T15 are simultaneously connected to the DC low voltage signal VSS. A drain of the fourteenth field effect transistor T14 is connected to the pull-up control signal Q(N) output by the pull-up control module 10 of the current stage. A drain of the fifteenth field effect transistor T15 is connected to the row scan signal G(N) output by the pull-up module 20 of the current stage.
It should be noted that the third array substrate row drive circuit unit is an array substrate row drive circuit unit located at the next stage of the array substrate row drive circuit unit of the current stage. In an embodiment, as shown in
The bootstrap module 70 includes a bootstrap capacitor, one end of the bootstrap capacitor is electrically connected to the end of the pull-up control module 10 that outputs the pull-up control signal Q(N), and another end of the bootstrap capacitor is electrically connected to one end of the row scan signal G(N) of the array substrate row drive circuit unit of the current stage output by the pull-up module 20. The bootstrap capacitor is mainly to maintain the voltage between the gate and the source of the sixth field effect transistor T6 to stabilize the output of the sixth field effect transistor T6.
In summary, the present disclosure provides an array substrate row drive circuit unit, an array substrate row drive circuit is formed by cascading multiple stages of array substrate row drive circuit units, the array substrate row drive circuit unit includes:
a pull-up control module for outputting a pull-up control signal when receiving a DC high voltage signal and a stage transmission signal;
a pull-up module electrically connected to the pull-up control module, and for outputting a row scan signal when receiving the pull-up control signal and a high-frequency clock signal;
a pull-down module connected to the pull-up control module and the pull-up module, and for pulling down the pull-up control signal and the row scan signal to a low level according to a DC low voltage signal when receiving the row scan signal; and
a voltage dividing module electrically connected to the pull-up module, and for increasing a falling edge during pull-down when the pull-down module pulls down the pull-up control signal and the row scan signal to the low level.
The present disclosure further provides an array substrate row drive circuit. The array substrate row drive circuit includes multiple stages of array substrate row drive circuit units as described above. The specific circuit of the array substrate row drive circuit unit refers to the above-mentioned embodiment. Since the array substrate row drive circuit adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here. The array substrate row drive circuit is formed by cascading multiple stages of array substrate row drive circuit units. Compared with only one falling edge in the prior art, in the present disclosure, the number of falling edges of the output scan signal is increased, and the difference between the high potential VGH and the low potential VGL of the output row scan signal is reduced, thereby reducing the feed-through voltage of the pixels, improving the uniformity of the liquid crystal display panel, which is beneficial to the display of the liquid crystal display panel with a narrow frame.
As shown in
The above are only some embodiments of the present disclosure, and do not limit the scope of the present disclosure thereto. Under the inventive concept of the present disclosure, equivalent structural transformations made according to the description and drawings of the present disclosure, or direct/indirect application in other related technical fields are included in the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201910573179.2 | Jun 2019 | CN | national |
This application is a continuation application of International Application No. PCT/CN2020/098072, filed on Jun. 24, 2020, which claims priority to Chinese Patent Application No. 201910573179.2, filed on June 27, 2019, and entitled “ARRAY SUBSTRATE ROW DRIVE CIRCUIT UNIT, DRIVE CIRCUIT AND LIQUID CRYSTAL DISPLAY PANEL THEREOF”, the entire disclosures of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2020/098072 | Jun 2020 | US |
| Child | 17561988 | US |
