Patent Application
20230325645
Numerous examples are disclosed of an artificial neural network comprising a three-dimensional integrated circuit.
Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected “neurons” which exchange messages between each other.
One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.
Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference. The non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.
Non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in
Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.
Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22,and a positive voltage on the source region 14. Electron current will flow from the drain region 16 towards the source region 14. The electrons will accelerate and become heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.
Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal). If the floating gate 20 is positively charged (i.e., erased of electrons), then the portion of the channel region 18 under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
Table No. 1 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and program operations:
Other split gate memory cell configurations, which are other types of flash memory cells, are known. For example,
Table No. 2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations:
Table No. 3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations:
Table No. 4 depicts typical voltage ranges that can be applied to the terminals of memory cell 510 and substrate 12 for performing read, erase, and program operations:
The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random access memory), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation.
In order to utilize the memory arrays comprising one of the types of non-volatile memory cells described above in an artificial neural network, two modifications are made. First, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.
Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, and vice-versa, independently and with minimal disturbance of other memory cells. This means the cell storage is effectively analog or at the very least can store one of many discrete values (such as 16 or 64 different values), which allows for very precise and individual tuning of all the memory cells in the memory array, and which makes the memory array ideal for storing and making fine tuning adjustments to the synapsis weights of the neural network.
S0 is the input layer, which for this example is a 32×32 pixel RGB image with 5 bit precision (i.e. three 32×32 pixel arrays, one for each color R, G and B, each pixel being 5 bit precision). The synapses CB1 going from input layer SO to layer C1 apply different sets of weights in some instances and shared weights in other instances and scan the input image with 3×3 pixel overlapping filters (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, values for 9 pixels in a 3×3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3×3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3×3 filter scans across the entire 32×32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated.
In layer C1, in the present example, there are 16 feature maps, with 30×30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two dimensional array, and thus in this example layer C1 constitutes 16 layers of two dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships, not necessarily physical relationships—i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1 feature maps could all be directed to different aspects of the same image feature, such as boundary identification. For example, the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges, the second map (generated using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on.
An activation function P1 (pooling) is applied before going from layer C1 to layer S1, which pools values from consecutive, non-overlapping 2×2 regions in each feature map. The purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays of 15×15 pixels each). The synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4×4 filters, with a filter shift of 1 pixel. At layer C2, there are 22 12x12 feature maps. An activation function P2 (pooling) is applied before going from layer C2 to layer S2, which pools values from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied at the synapses CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 via a respective synapse of CB3. At layer C3, there are 64 neurons. The synapses CB4 going from layer C3 to the output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. This output could, for example, be indicative of an identification or classification of the contents of the original image.
Each layer of synapses is implemented using an array, or a portion of an array, of non-volatile memory cells.
Non-volatile memory cell array 33 serves two purposes. First, it stores the weights that will be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the non-volatile memory cell array 33 negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.
The output of non-volatile memory cell array 33 is supplied to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums up the outputs of the non-volatile memory cell array 33 to create a single value for that convolution. The differential summer 38 is arranged to perform summation of positive weight and negative weight.
The summed-up output values of differential summer 38 are then supplied to an activation function block 39, which rectifies the output. The activation function block 39 may provide sigmoid, tanh, or ReLU functions. The rectified output values of activation function block 39 become an element of a feature map as the next layer (e.g. C1 in
The input to VMM array 32 in
The output generated by input VMM array 32a is provided as an input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as an input to the next VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical non-volatile memory array, or multiple VMM arrays could utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays could utilize overlapping portions of the same physical non-volatile memory array. The example shown in
In VMM array 900, control gate lines, such as control gate line 903, run in a vertical direction (hence reference array 902 in the row direction is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run in a horizontal direction. Here, the inputs to VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array 900 emerges on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all the currents from the memory cells connected to that particular source line.
As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., the memory cells 310 VMM array 900, may be configured to operate in a sub-threshold region.
The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion (sub threshold region):
Ids=Io*e(Vg−Vth)/nVt=w*Io*e(Vg)/nVt,
where w=e(−Vth)/nVt
where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage=k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor=1+(Cdep/Cox) with Cdep=capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox*(n−1)* Vt2 where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.
For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current into an input voltage:
Vg=n*Vt*log [Ids/wp*Io]
where, wp is w of a reference or peripheral memory cell.
For a memory array used as a vector matrix multiplier VMM array with the current input, the output current is:
Iout=wa*Io*e(Vg)/nVt, namely
Iout=(wa/wp)*Iin=W*Iin
W=e(Vthp−Vtha)/nVt
Here, wa=w of each memory cell in the memory array. Vthp is effective threshold voltage of the peripheral memory cell and Vtha is effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of substrate body bias voltage and the substrate body bias voltage, denoted Vsb, can be modulated to compensate for various conditions, on such temperature. The threshold voltage Vth can be expressed as:
Vth=Vth0+gamma (SQRT|Vsb−2*φF)−SQRT|2*φF |)
where Vth0 is threshold voltage with zero substrate bias, φF is a surface potential, and gamma is a body effect parameter.
A wordline or control gate can be used as the input for the memory cell for the input voltage.
Alternatively, the flash memory cells of VMM arrays described herein can be configured to operate in the linear region:
Ids=beta*(Vgs−Vth)*Vds ; beta=u*Cox*Wt/L
W=α(Vgs−Vth)
meaning weight W in the linear region is proportional to (Vgs−Vth)
A wordline or control gate or bitline or sourceline can be used as the input for the memory cell operated in the linear region. The bitline or sourceline can be used as the output for the memory cell.
For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage.
Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region:
Ids=½*beta*(Vgs−Vth)2; beta=u*Cox*Wt/L
Wα (Vgs−Vth)2,
meaning weight W is proportional to (Vgs−Vth)2
A wordline, control gate, or erase gate can be used as the input for the memory cell operated in the saturation region. The bitline or sourceline can be used as the output for the output neuron.
Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.
Other examples for VMM array 32 of
Memory array 1003 serves two purposes. First, it stores the weights that will be used by the VMM array 1000 on respective memory cells thereof. Second, memory array 1003 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0-BLN), which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, memory array 1003 negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.
Table No. 5 depicts operating voltages and currents for VMM array 1000. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.
Table No. 6 depicts operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.
Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200. Second, memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays 1201 and 1202 convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0-BLN, and will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the memory array negates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the output emerges on the bit lines (BL0-BLN) during a read operation. The current placed on each bitline performs a summing function of all the currents from the memory cells connected to that particular bitline.
VMM array 1200 implements uni-directional tuning for non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased and the sequence of partial programming operations starts over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.
Table No. 7 depicts operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.
Table No. 8 depicts operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.
The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units.
LSTM cell 1500 comprises sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector. LSTM cell 1500 also comprises tanh devices 1504 and 1505 to apply a hyperbolic tangent function to an input vector, multiplier devices 1506, 1507, and 1508 to multiply two vectors together, and addition device 1509 to add two vectors together. Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.
An alternative to LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in
Whereas LSTM cell 1600 contains multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 contains only one set of VMM arrays 1701 and activation function block 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 will require less space than LSTM 1600, as LSTM cell 1700 will require ¼ as much space for VMMs and activation function blocks compared to LSTM cell 1600.
It can be further appreciated that LSTM units will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The examples described below therefore reduce the circuitry required outside of the VMM arrays themselves.
An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell.
An alternative to GRU cell 2000 (and another example of an implementation of GRU cell 1900) is shown in
Whereas GRU cell 2000 contains multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 contains only one set of VMM arrays 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 will require less space than GRU cell 2000, as GRU cell 2100 will require ⅓ as much space for VMMs and activation function blocks compared to GRU cell 2000.
It can be further appreciated that GRU systems -will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The examples described below therefore reduce the circuitry required outside of the VMM arrays themselves.
The input to the VMM arrays can be an analog level, a binary level, a pulse, a time modulated pulse, or digital bits (in this case a DAC is needed to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, a timing pulse, pulses, or digital bits (in this case an output ADC is needed to convert output analog level into digital bits).
In general, for each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of 2 cells). In the differential cell case, two memory cells are needed to implement a weight W as a differential weight (W=W+−W−). In the two blend memory cells, two memory cells are needed to implement a weight W as an average of two cells.
Each non-volatile memory cells used in the analog neural memory system is to be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.
The input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit 3406 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for input levels. The input circuit 3406 may implement an activation function such as ReLU or sigmoid.
The output circuit 3407 may include circuits such as an ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters. The output circuit 3407 may implement an activation function such as rectified linear activation function (ReLU) or sigmoid. The output circuit 3407 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit 3407 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.
As the applications for artificial neural networks become more complex, there is an increasing need for larger VMM arrays. At the same time, there exists a need to efficiently use space within a packaged integrated circuit and to save power as much as possible while still maintaining accuracy so that each of the N different weights are still stored and read properly.
Numerous examples are described for providing an artificial neural network system comprising a three-dimensional integrated circuit comprising one or more VMM arrays.
In this example, die 3501 contains a respective VMM array 3507 (functionally similar to VMM 3401 in
Die 3502 also contains a respective VMM array 3507, a respective input multiplexor 3509, a respective row buffer 3522, a respective high voltage decoder 3508, and a respective neuron circuit 3510.
In this example, two dies (dies 3501 and 3502) contain respective VMM arrays 3507, but it is to be understood that additional dies that contain respective VMM arrays can be included.
Die 3503 contains high voltage generator 3511 (functionally similar to high voltage generation block 3410 in
Die 3504 contains input circuit 3514 (functionally similar to input circuit 3406), which includes address decoding circuit 3524, row register 3525 (holding activation input values for array rows), and digital-to-analog converter (DAC) 3515. DAC 3515 receives digital signals from the row register 3525 and converts them into analog signals.
Die 3505 contains analog-to-digital converter (ADC) 3516. ADC 3516 receives analog signals and converts them into digital signals.
Die 3506 contains digital circuits 3517, static random access memory (SRAM) 3518, registers 3519, physical I/O connections 3520, digital accelerator 3531, and a network-on-chip (NOC) 3715. Die 3506 provides control functions for other dies. Digital circuits 3517 can include digital logic, micro-controllers, SIMD (single instruction multiple data) processor, and processors. SRAM 3518 and registers 3519 can be used to store system information and configuration information used by digital circuits 3517 or other circuits, or blocks in 3D VMM system 3500. Physical I/O connections 3520 provide IO interfaces to devices outside of VMM system 3500 (such as an external processing unit) or to another package 3522. Digital accelerator 3531 is used for certain neural networks or certain layers within a neural network where additional processing may be required, such as when a small activation size is present, where the weights stored in the cells are dynamic and not fixed, where a MAC operation needs to be performed, without limitation. NOC 3715 provides network routing functionality within 3D VMM system 3500, for example, by generating control signals to cause signals to be routed from one block to another block.
Respective ones of the plurality of dies are connected to one or more other dies within the plurality of dies through vertical interfaces 3521, which vertical interfaces 3521 respectively connect two or more dies together. In one example, vertical interfaces 3521 are implemented as a through-silicon via (TSV).
During a read operation of 3D VMM system 3500, a digital input is received by input circuit 3514. The digital input enables row registers 3525, which store activation inputs and applies a selected activation input in response to the digital input to DAC 3515 which DAC 3515 converts the digital outputs from the row registers 3525 into respective analog signals. The analog signal produced by DAC 3515 is provided by input circuit 3514 over one or more vertical interfaces 3521 to input multiplexor 3509 and row buffer 3523 on one, or more of dies 3501, 3502, which then applies the signals to one or more rows in the respective VMM array 3507, resulting in an output being generated by VMM array 3507. The output from the respective VMM array 3507 is received by the respective neuron circuit 3510, which provides a buffer function to drive the parasitic capacitance of the one or more vertical interfaces 3521 to which it connects. Neuron circuit 3510 provides analog signals over one or more vertical interfaces 3521 to ADC 3516 on die 3505, which ADC 3516 converts the analog signals into digital signals. Alternatively, the analog signals can bypass ADC 3516 and remain in analog form. The output of ADC 3516 is provided to a device external to 3D VMM system 3500 (such as a processing unit or graphics processing unit) through physical I/O 3520 or applied as inputs to a respective VMM array 3507 (representing another layer in the artificial neural network). Alternatively, the analog signals from neuron circuit 3510 can bypass ADC 3516 and remain in analog form and be applied as inputs to a respective VMM array 3507.
3D VMM system 3600 comprises a plurality of dies, such as dies 3601, 3602, 3603, 3604, 3605, and 3606, which are stacked vertically within common package 3522 to form a packaged integrated circuit.
In this example, die 3601 contains a respective VMM array 3507, a respective input multiplexor 3509, respective registers 3524 (holding the activation input values for array rows), respective row buffers 3523, a respective high voltage multiplexor 3608, and a respective column multiplexor 3610.
Die 3602 also contains a respective VMM array 3507, a respective input multiplexor 3509, respective registers 3524, respective row buffers 3523, a respective high voltage multiplexor 3608, and column multiplexor 3610.
In this example, two dies (dies 3601 and 3602) contain respective VMM arrays 3507, but it is to be understood that additional dies that contain VMM arrays can be included.
Die 3603 contains high voltage generator 3511, analog circuitry 3512, temperature compensation circuit 3513, and high voltage multiplexor 3608.
Die 3604 contains input circuit 3614 which includes address decoding 3524 and DAC 3515.
Die 3605 contains neuron circuit 3510 and ADC 3516.
Die 3606 contains digital circuits 3517, SRAM 3518, registers 3519, and physical I/O connections 3520.
Respective ones of the plurality of dies are connected to one or more other dies within the plurality of dies through respective vertical interfaces 3521.
During a read operation of 3D VMM system 3600, an input is received and an address is received by input circuit 3614. Address decoder 3524 decodes the address and provides the input over one or more vertical interfaces 3521 to a respective row register 3525 corresponding to the decoded address. The output of the respective row register 3525 is coupled over one or more vertical interfaces 3521 to DAC 3515 which converts the digital output bits received from row register 3525 into an analog signal, and provides the analog signal over one or more vertical interfaces 3521 to a respective input multiplexor 3509 and row buffer 3523. Row buffer 3523 applies the analog signal, buffered, to row inputs of the respective VMM array 3507 for the selected rows (such as array control gates or wordlines). The output from the respective VMM array 3507 (such as from array bitlines) is received by the respective column multiplexor 3610, and the output of the respective column multiplexor 3610 provides signals over one or more vertical interfaces 3521 to ADC 3516, on die 3605, which converts the analog signals into digital signals. Alternatively, the signals can bypass ADC 3516 and remain in analog form. The output of ADC 3516 is provided over one or more vertical interfaces 3521 to digital circuits 3517 (which can perform an activation function, a pooling function, or other network function) on die 3606, and the output of digital circuits 3517 may be provided to a device external to 3D VMM system 3600 (such as a processing unit or graphics processing unit) through physical I/O 3520 on die 3606 or to input circuit 3614 on die 3604, over a respective vertical interface 3521, as inputs to another respective VMM array 3507 (representing another layer in the artificial neural network).
In the example shown, die 3701 and die 3707 each contain a respective VMM array 3507, a respective array input 3729 (which includes a respective input multiplexor 3509, a respective address decoder 3713, a respective row register 3525, and a respective row buffer 3523), a respective high voltage multiplexor 3608, and a respective neuron circuit 3510.
Die 3702 and die 3708 also each contain a respective VMM array 3507, a respective array input 3729 (which includes a respective input multiplexor 3509, a respective address decoder 3713, a respective row register 3525, and a respective row buffer 3523), a respective high voltage multiplexor 3608, and a respective neuron circuit 3510.
In this example, four dies (dies 3701, 3702, 3707, and 3708) contain respective VMM arrays 3507, but it is to be understood that additional dies that contain VMM arrays can be included.
Die 3703 and die 3709 each contain a respective high voltage decoder 3714, a respective high voltage generator 3511, a respective analog circuitry 3512, and a respective temperature compensation circuit 3513.
Die 3704 and die 3710 each contain a respective input circuit 3514 which includes a respective DAC 3515.
Die 3705 and die 3711 each contain a respective ADC 3516.
Die 3706 and die 3712 each contain respective digital circuits 3517, a respective SRAM 3518, respective registers 3519, respective physical I/O connections 3520, and respective NOC (network-on-chip) connections 3715.
Respective ones of the plurality of dies are connected to one or more other dies within the plurality of dies through one or more vertical interfaces 3521 or horizontal interfaces 3716, which respectively connect two or more dies together. In one example, vertical interfaces 3521 are respectively a through-silicon via (TSV). In one example, horizontal interfaces 3716 are respectively a redistribution layer (RDL) connection.
During a read operation of 3D VMM system 3700, a digital input is received by a respective input circuit 3514, which converts the digital input to an analog signal via its respective DAC 3515, and the output of the respective DAC 3515 is coupled to the row register 3525 of the respective array input 3729 via the respective vertical interface(s) 3521 and/or horizontal interface(s) 3716. The output of row register 3525 of the respective array input 3729 is provided to input multiplexor 3509 and row buffer 3523, which then applies the signals to one or more rows in VMM array 3507. The output from the respective VMM array 3507 is received by the respective neuron circuit 3510, which neuron circuit 3510 provides a buffer function to drive the parasitic capacitance of the one or more vertical interfaces 3521 or horizontal interfaces 3716 to which it connects. Neuron circuit 3510 provides buffered analog signals over one or more vertical interfaces 3521 or horizontal interfaces 3716 to a respective ADC 3516, which converts the analog signals into digital signals. The output of ADC 3516 is provided to respective digital circuits 3517 (which performs an activation function, pooling function, or network function) and the output of the respective digital circuits 3517 may be provided to a device external to 3D VMM system 3700 (such as a processing unit or graphics processing unit) through respective physical I/O 3520 or to a respective input circuit 3514 to be converted by the respective DAC 3515, and the output of the respective input circuit 3514 is coupled to another VMM array 3507 (representing another layer in the artificial neural network) or to another package 3522 through a respective physical I/O 3520.=
In the example shown, die 3801, 3802, 3807 and die 3808 each contain a respective VMM array 3507, a respective array input 3729, a respective high voltage multiplexor 3608, a respective column multiplexor 3610, and a respective array input circuit 3729. Respective array inputs 3729 comprise an input multiplexor 3509, and address decoder 3713, a row register 3524 and a row buffer 3523.
In this example, four dies (dies 3801, 3802, 3807, and 3808) contain VMM arrays, but it is to be understood that additional dies that contain VMM arrays can be included.
Die 3803 and die 3809 respectively contain a high voltage decoder 3714, a high voltage generator 3511, an analog circuitry 3512, and a temperature compensation circuit 3513.
Die 3804 and die 3810 respectively contain an input circuit 3514 which includes DAC 3515.
Die 3805 and die 3811 respectively contain ADC 3516, and neuron circuit 3510.
Die 3806 and die 3812 respectively contain digital circuits 3517, an SRAM 3518, registers 3519, physical I/O connections 3520, and NOC connections 3715.
The plurality of dies are respectively connected to one or more other dies within the plurality of dies through one or more vertical interfaces 3521 or horizontal interfaces 3716, which respectively connect two or more dies together. In one example, respective vertical interfaces 3521 are implemented as a through-silicon via (TSV). In one example, respective horizontal interface 3716 are implemented as a redistribution layer (RDL) connection.
During a read operation of 3D VMM system 3800, a digital input is received by input circuit 3514, which uses DAC 3515 to convert the digital input into analog form and provide the analog signal to the respective array input circuit 3729 via the respective vertical interface(s) 3521 and/or horizontal interface(s) 3716. Array input circuit 3729 receives the analog signals from the input circuit and addresses and then applies the analog signal to the selected rows, responsive to the addresses, in VMM array 3507. The output from VMM array 3507 is received by column multiplexor 3610, which provides analog signals over one or more vertical interfaces 3521 or horizontal interfaces 3716 to ADC 3516, which converts the analog signals into digital signals. Alternatively, the analog signals can bypass ADC 3516 and remain in analog form. The output of ADC 3516 is provided over one or more vertical interfaces 3521 or horizontal interfaces 3716 to digital circuit 3517 (which can perform an activation function, a pooling function, or other network function) and the output of digital circuit 3517 can be provided to a device external to 3D VMM system 3800 (such as a processing unit or graphics processing unit) through physical I/O 3520 or to input circuits 3514 of other VMM array 3507 (representing another layer in the artificial neural network) or to another package 3522 through physical I/O 3520.
In the example shown, die 3901, 3902, 3905 and die 3906 respectively contain a VMM array 3507, an array input 3729, a high voltage multiplexor 3608, and a column multiplexor 3610.
In this example, four dies (dies 3901, 3902, 3903, and 3904) contain VMM arrays, but it is to be understood that additional dies that contain VMM arrays can be included.
Die 3903 and die 3907 respectively contain a high voltage decoder 3714, a high voltage generator 3511, an analog circuitry 3512, a temperature compensation circuit 3513, an input circuit 3514 which includes DAC 3515, a neuron circuit 3510, and ADC 3516.
Die 3904 and die 3908 respectively contain digital circuits 3517, an SRAM 3518, registers 3519, physical I/O connections 3520, and NOC connections 3715.
The plurality of dies are respectively connected to one or more other dies within the plurality of dies through one or more vertical interfaces 3521 or horizontal interfaces 3716, which respectively connect two or more dies together.
During a read operation of 3D VMM system 3900, a digital input is received by input circuit 3514, which input circuit 3514 uses DAC 3515 to convert the digital input into analog form and provide the analog signal to the respective array input circuit 3729 via the respective vertical interface(s) 3521 and/or horizontal interface(s) 3716. Array input circuit 3729 receives analog signals from the input circuit and addresses, and, responsive to the received addresses, applies the analog signal to the selected rows in VMM array 3507. The output from VMM array 3507 is received by column multiplexor 3610, which provides analog signals over one or more vertical interfaces 3521 or horizontal interfaces 3716 to ADC 3516, which converts the analog signals into digital signals. Alternatively, the analog signals can bypass ADC 3516 and remain in analog form. The output of ADC 3516 is provided to digital circuits 3517 via the respective vertical interface(s) 3521 and/or horizontal interface(s) 3716, and then provided to a device external to 3D VMM system 3900 (such as a processing unit or graphics processing unit) through physical I/O 3520 or to input circuit 3514 to be applied as inputs to VMM array 3507 (representing another layer in the artificial neural network) or to another package 3522 through physical I/O 3520.
In the example shown, die 3981, 3982, 3984 and die 3985 respectively contain a VMM array 3507, a high voltage block 3991, an input block 3990, an output block 3992 and an analog block 3993. Input block 3990 may include input circuit 3514, DAC 3515, array input circuit 3729. High voltage block 3991 may include high voltage multiplexor 3608 and high voltage decoder 3714. Output block 3992 may include column multiplexor 3610, neuron circuit 3510, and ADC 3516. Analog block 3993 may include high voltage generator 3511, analog circuitry 3512, and temperature compensation circuity 3513.
Die 3983 and die 3986 each contains digital circuits 3517, SRAM 3518, registers 3519, physical I/O connections 3520, digital accelerator 3521 (used for multiple and accumulate (MAC) function digitally) and NOC connections 3715.
The plurality of dies are respectively connected to one or more other dies within the plurality of dies through one or more vertical interfaces 3521 or horizontal interfaces 3716, each of which respectively connects two or more dies together.
In the example shown, die 4001, 4002, 4005 and 4006 respectively contain a VMM array 3507, an array input 4029 (which includes input multiplexor 3509 and/or decoder 3713—not shown), a high voltage multiplexor 3608, and a column multiplexor 3610.
In this example, four dies (dies 4001, 4002, 4003, and 4004) contain VMM arrays, but it is to be understood that additional dies that contain VMM arrays can be included.
Die 4003 and die 4007 respectively contain a high voltage decoder 3714, a high voltage generator 3511, an analog circuitry 3512, a temperature compensation circuit 3513, and a neuron circuit 3510.
Die 4004 and die 4008 respectively contain a digital circuits 3517, an SRAM 3518, registers 3519, physical I/O connections 3520, and NOC connections 3715.
Unlike VMM system 3900, VMM system 4000 does not contain DAC 3515, and ADC 3516 because the inputs and outputs are kept in analog form and not converted between analog and digital form.
The plurality of dies are respectively connected to one or more other dies within the plurality of dies through one or more vertical interfaces 3521 or horizontal interfaces 3716, which respectively connect two or more dies together.
During a read operation of 3D VMM system 4000, an analog input (such as a voltage, a current, or a timed based entity such as a sequence of pulses) is received by a respective array input 4029 which then applies the signals to one or more rows in respective VMM array 3507. The output from the respective VMM array 3507 is received by column multiplexor 3610, which provides analog signals (such as a voltage, a current, or a timed based entity) over one or more vertical interfaces 3521 or horizontal interfaces 3716 to a respective neuron circuit 3510, which neuron circuit 3510 provides a buffered signal to a device external to 3D VMM system 4000 (such as a processing unit or graphics processing unit), or to another package 3522, through physical I/O 3520 or to array input 4029 of other VMM array 3507 (representing another layer in the artificial neural network).
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Differential neuron circuit 5200 comprises operational amplifier 5201; variable integrating resistors 5202 and 5203; controlled switches 5204, 5205, 5206, and 5207; and sample and hold (and/or integrating) capacitors 5208 and 5209, configured as shown. Differential neuron circuit 5200 receives differential current BLw+ from a W+ bit line and BLw− from a W-bit line and outputs voltages Vout+ and Vout−, respectively. The output voltage Vout+=(BLw+)*R and Vout−=(BLw−)*R, with variable integrating resistors 5202 and 5203 each having value equal to R. Capacitors 5208 and 5209 serves as respective sample and hold (S/H) capacitors to hold the output voltage once the resistors 5202 and 5203 are removed from the circuit by opening controlled switches 5206, 5207 and the input current is shut off by opening controlled switches 5204, 5205. A control circuit (not shown) controls the opening and closing of switches 5204, 5205, 5206 and 5207 to provide an integration time. Optionally, differential output voltages Vout+ and Vout− can be input to ADC 3516, which converts differential output voltages Vout+ and Vout− into a set of digital output bits, Doutx. Optionally the circuit can use the capacitors 5208 and 5209 as integrating capacitors to integrate the neuron currents to convert the current into a voltage, Vout=Time*Ineuron/Capacitance. The neuron scaling is provided by variable resistors 5292 and 5203 or variable integrating time and/or variable capacitance in case of using integrating capacitor approach.
Differential successive address register analog-to-digital converter 5400 converts an analog input or differential analog input into a digital output using a binary search through all possible quantization levels to identify the appropriate digital output.
Differential successive address register analog-to-digital converter 5400 comprises binary capacitive digital-to-analog converter (CDAC) 5401, binary CDAC 5402 (complementary to CDAC 5401), comparator 5403, and SAR logic and registers 5404.
Differential successive address register analog-to-digital converter 5400 receives a differential current input, Vinp and Vinn. SAR logic and registers 5404 cycle through all possible digital bit combinations, which in turn control switches in CDAC 5401 and 5402 to couple voltage sources to capacitors. When the output of comparator 5403 flips, then the digital bit combination in SAR logic and registers 5404 is output as Digital Output. Optionally, SAR logic and registers 5404 generates an additional 1-bit digital output, DMAJ, in Digital Outputs which is a “1” if a majority of the bits in the digital value are a “1”, and a “0” if a majority of the bits in the corresponding digital value are not “1.”
It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
This application claims priority to U.S. Provisional Patent Application No. 63/328,126, filed on Apr. 6, 2022, and titled, “Artificial Neural Network Comprising a Three-Dimensional Integrated Circuit,” which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 63328126 | Apr 2022 | US |
