Patent Application
20250072303
The technical field of the invention is that of non-volatile resistive memories. It also relates to the manufacture of such memories.
The invention is part of the development of so-called “crossbar” memory arrays, in which a plurality of memory points are each located at the intersection between a conductive row and a conductive column. Each memory point is then addressed, for example by applying a voltage between the conductive row and the conductive column to which it is connected.
The invention more particularly relates to memory points comprising a resistive memory, i.e. a memory in which information is stored in the form of an electric resistance value. A resistive memory can be of different types, according to the phenomena used to write, store and read the information.
Resistive memories are typically made in layers located above a substrate (for example a Silicon substrate) on which the array is made. These components are said to belong to the “manufacturing unit”, that is manufactured during final manufacturing steps or even “Back-End-Of-Line” (BEOL) components, as opposed to components belonging to the initial manufacturing unit” or “Front-End-Of-Line” (FEOL) components. BEOL components, for example, are integrated between the metal interconnection levels. FEOL components are manufactured on the surface of the substrate (diodes and CMOS transistors, for example).
For example, a PCRAM (Phase Change Random Access Memory) implements the strong contrast in electronic properties between an amorphous phase and a crystalline phase of a material.
A CBRAM (Conductive Bridge RAM) implements the formation/dissolution of a conductive filament in a solid electrolyte as a result of diffusion of ions from an active electrode.
A so-called “oxide reversible dielectric breakdown” or OxRAM (Oxide RAM) memory implements reversible breakdown of a dielectric material as a function of an electrical voltage applied to this material.
A so-called magnetic memory or MRAM implements relative magnetisation between a reference magnetic layer and a programmable magnetic layer.
The use of resistive memories is proving to be a promising solution for increasing density of memory arrays. They are also being used to develop new applications such as “neuromorphic” computing and a new class of memory called “Storage Class Memory”. However, resistive memories can have different drawbacks.
In an array of memory points, a plurality of resistive memories are connected to a same row or column. However, applying an addressing voltage to the terminals of one of these memories (for example to read it) creates a non-negligible leakage current in the other memories of the same row or column. This leakage current degrades the ability to read and/or write information in one of the memories.
In order to solve this problem, it is known to add selection devices, called “selectors”, for example each connected in series with each memory (“1S1R” type arrangement). Activation of a single selector from the plurality of selectors thus enables a single memory to be selected, while the other selectors, being blocked (off), to eliminate or reduce leakage currents from the other memories.
A type of selector co-integratable in the back-end, called a “co-integratable” selector or “back-end” selector in the following, offers ease of co-integration with the memory, in series with the same, wherein its dimensions can be adjusted to the dimensions of the resistive memory. Indeed, the conducting (on) state of a back-end selector is sufficiently conductive to reduce its dimensions to the same level as those of the memory with which it can be connected in series. In addition, a back-end selector can be formed of layers deposited onto or under a memory layer and etched as a block at the same time as the memory layer. There are several types of back-end selector.
An Ovonic Threshold Switching (OTS) selector implements a characteristic property of some chalcogenide materials: under the effect of an electric field, it shifts from a resistive state to a metastable conductive state; the metastable conductive state can be maintained as long as a holding current flows in the OTS selector; otherwise, the OTS selector returns to the resistive state (off state);
An unstable conductive bridge or TS (Threshold Switch) selector implements the formation of a metastable metal filament by diffusing, under the effect of an electric field, an active electrode in an electrolyte; when the field is no longer applied, the metastable metal filament dissolves;
A MIEC (Mixed Ion-Electronic Conduction) selector implements mobility of metal ions for creating an electric current under the effect of an electric field;
A metal-insulator transition selector implements a material with high electronic correlation requiring the application of an electric field exceeding a threshold field to create an electric current, the threshold field being a function of the Coulomb repulsion forcing the free electrons of said material to be located;
Finally, a Schottky barrier or tunnel barrier selector implements a high degree of non-linearity in its current-voltage characteristic to achieve the desired “selection” effect.
A memory point comprising a “back-end” selector has a reduced overall size and is easy to manufacture (it can be etched at the same time as the resistive memory part of the memory point). However, good functionality of the assembly relies on matching in the electrical properties of the selector and the memory.
There is therefore a need for a non-volatile resistive memory device, with a selector, which is of low overall size, is convenient to manufacture, and wherein the electrical properties of the memory and the selector can each be adjusted independently.
The invention relates to an assembly including at least two selectors electrically disposed in parallel with each other and each being electrically connected in series to a memory layer forming at least two distinct non-volatile resistive memories each associated, respectively, with one of the two selectors, the assembly including:
Each upper electrode is electrically connected to a conduction region of the first active layer, i.e. the memory layer of the assembly. By conduction region or conduction channel, it is meant a portion of active layer where the resistivity can vary as a function of an applied voltage or a current flowing therethrough. In particular, this is a portion where the creation/destruction of a conductive structure such as a conduction filament is favoured.
As the first and second upper electrodes are separated from each other, they are connected to conduction regions that are also separated from each other. Thus the first active layer comprises two separate, independently operable conduction regions.
Since the first active layer is a memory layer, the two separate conduction regions of the first layer thus form a first non-volatile resistive memory and a second non-volatile resistive memory, which are distinct and independently operable. Thus, each memory is connected in series with a vertical (or at least oblique) stack, acting as a selector. The assembly according to the invention therefore comprises two independently addressable selector/memory assemblies 1S1R, enabling two distinct pieces of information to be stored in a non-volatile manner. In other words, the assembly is of the nSnR type, where n is at least equal to two.
The dimensions of the first memory partly depend on the surface area of the first upper electrode extending on the first active layer. The greater said surface area, the greater the dimensions of the first memory, especially in parallel to the given horizontal plane. Similarly, the dimensions of the second memory partly depend on the (planar) surface of the second upper electrode extending on the first active layer. It is thus possible to adjust dimensions of the first and second memories independently, by adjusting the planar surface areas of the first and second upper electrodes extending on the first active layer.
The first upper electrode is also electrically connected, via its first side surface, to a conduction region of the second active layer. The conduction region of the second active layer therefore forms a first selector. The vertical dimensions of the first selector partly depend on the surface area of the first upper electrode in contact with the second active layer. For example, it is proportional to a thickness of the first upper electrode. The greater said thickness, the greater the dimensions of the first selector. It is thus possible to adjust dimensions of the first selector by adjusting thickness of the first electrode. The thickness of the first upper electrode, on the one hand, and its arrangement (in particular its extent) on the first active layer, on the other hand, can be adjusted independently of each other (stated differently, the thickness of this electrode can be adjusted independently of the side dimensions of the conduction zone corresponding to the first resistive memory). The dimensions of the first selector and the first memory can therefore be adjusted independently.
Electrical properties of the first memory and the first selector partly depend on their dimensions. Indeed, the current passing through the memory partly depends on the size of the memory. Furthermore, for PCRAM-type memories, for example, the programming current is proportional to the surface area of the electrode against which it extends. Similarly, the threshold current of the selector also partly depends on its dimensions. And, for an OTS type selector, the holding current can be reduced by reducing the dimensions of the selector, especially when these are less than a critical dimension in the order of 80 nm. The leakage currents of a MIEC-type selector also partly depend on the size of the electrode against which the selector extends. Thus, electrical properties of the first memory, and those of the first selector can be adjusted independently, in this particular architecture, due to the fact that the surface areas (or effective surface areas) of these elements can be adjusted independently of each other.
The same reasoning applies to a conduction region of the third active layer, forming a second selector. Electrical properties of the second selector and the second memory can each be adjusted independently by adjusting a thickness of the second upper electrode and its arrangement on the first active layer.
As explained in detail with reference to the figures, the oblique orientation with respect to said plane, for example vertical, of at least some of the second and third active layers, combined with the use of a same first, horizontal, memory, results in a highly satisfactory compactness for the assembly.
In addition, this particular geometric arrangement surprisingly makes it possible to obtain effective surface areas (typically superimposed surface areas between electrodes or electrical contacts) that can be smaller than a minimum surface accessible at first sight for an etching fineness F, i.e. smaller than F2.
For each of the selectors of the assembly, oriented obliquely with respect to the horizontal plane, the surface area of the selector facing the upper electrode under consideration embraces part of the perimeter of this upper electrode. This surface area is therefore equal to the length of the selector/electrode portion in contact multiplied by the thickness of the electrode.
For example, when the selector embraces three of the four sides of the upper electrode under consideration, its surface area S is equal to:
where L is the length of one long side of the electrode, for example equal to fineness F, l is the length of two short sides of the electrode, for example equal to F/2 and w is the thickness of the electrode, for example equal to F/4. The surface area S (effective surface area of the selector) is according to this example equal to:
Selectors, for example ovonic selectors, advantageously benefit from this reduction in surface area, making it possible, for example, to reduce their leakage current and also their threshold and holding currents when their dimensions are below a limit value, generally in the order of 80 nm.
Similarly, each memory can also have a reduced surface area, also less than F2. Indeed, the manufacture of a memory according to prior art, i.e. aligned in the plane, is limited by the etching fineness F. The smallest surface area of a memory according to prior art that can be manufactured is therefore greater than or equal to F2.
For each of the two memories of the memory stack, its surface area is equal to the surface area of an upper electrode extending on the first active layer. For example, for an upper electrode with a long side having length F and a short side having length F/2, the surface area S of the memory is also equal to:
In addition, in this geometry, the effective surface area of the memory can be made even smaller by a lateral offset between the upper electrode and lower electrode.
Memories, for example of the OxRAM type, advantageously benefit from this reduction in surface area. Indeed, they can show greater resistance in the high state as their surface area is reduced. Modifying the resistance at the high state of the memory (so as to increase it) especially makes it possible to increase the reading window of the selector/memory assembly.
Further to the characteristics just discussed in the previous paragraph, the assembly according to the invention may have one or more additional characteristics from among the following, considered individually or according to any technically possible combinations:
The invention further relates to a resistive memory array comprising a plurality of assemblies according to the invention, wherein for each assembly:
The invention also relates to a method for manufacturing an assembly comprising at least two selectors electrically disposed in parallel with each other and each electrically connected in series to a memory layer forming at least two distinct non-volatile resistive memories each associated, with one of the two selectors, respectively, the method comprising the following steps of:
Advantageously, the steps of forming the second and third stacks are performed by carrying out the following steps of:
Optional characteristics set forth above in terms of the device (for the assembly described above) may also apply to the method just set forth.
The invention and its different applications will be better understood upon reading the following description and upon examining the accompanying figures.
The figures are set forth byway of indicating and in no way limiting purposes of the invention. Unless otherwise specified, a same element appearing in different figures is identified by the same reference sign.
The invention especially relates to an assembly 1 comprising at least two non-volatile resistive memories and two selectors, each associated in series with one of these memories. Assembly 1 according to the invention makes it possible to adjust electrical properties of these memories and these selectors independently, while having a reduced overall size.
For this, assembly 1 combines a first planar stack 10, parallel to a given horizontal plane P, and at least two distinct stacks 20, 30, at least a part of which extends obliquely with respect to the plane P in question, for example vertically. In the following, the term ‘planar’ or ‘horizontal’ will be used to indicate an orientation parallel to said plane P (for example parallel to within better than 5 degrees). The plane P in question is, for example, parallel to a substrate on which assembly 1 is made. Oblique means an orientation at an angle of 90°±45° to plane P, in other words an angle of between 45° and 135° to plane P. Vertical is taken to mean an orientation at an angle of 90°±30° to plane P, preferably 90°±5°. Herein, in the examples described here with reference to the figures, at least a part of the second and third stacks 20, 30 extend vertically (perpendicularly to plane P). Alternatively, however, each of these two stacks could be oriented differently, extending for example in parallel to a plane making an angle of 60 degrees with said horizontal plane P (or, more generally, an angle of between 60 and 80 degrees, for example).
In the first, second, third and fourth embodiments described below (and represented, respectively, in
The first planar stack 10 comprises two upper electrodes 121, 122, separated from each other, with no direct electrical contact therebetween. Each upper electrode 121, 122 is electrically connected to one of the vertical stacks 20, 30. This arrangement corresponds to two independent 1S1R type memory/selector circuits.
From an electrical point of view, the second and third stacks 20, 30 are, as it were, disposed in parallel with each other, since, on the one hand, they are both connected in series to a same memory stack. It should nevertheless be noted that, on the other hand, these two selector stacks 20, 30 are connected to distinct electrical contacts (40 and 50), electrically insulated from each other.
As already indicated, at least a part of the selector stack 20 extends in parallel to a vertical plane. This part of the stack 20 extends opposite a first part 1211 of a side surface 1211, 1212 which laterally delimits the first upper electrode 121. This part of the stack 20 here extends in parallel to this first part 1211 of side surface (in parallel thereto, to better than 5 or 10 degrees, for example).
Similarly, at least a part of the selector stack 30 extends in parallel to a vertical plane. This part of the stack 30 extends opposite a second part 1222 of a side surface 1221, 1222 which laterally delimits the second upper electrode 122. This part of the stack 30 here extends in parallel to this second part 1222 of the side surface.
In assembly 1, the different layers (including the electrodes) which extend in parallel to plane P are each laterally delimited by one (or possibly more) side surface(s) which is (are) vertical or at least oblique with respect to plane P. This side surface or surfaces are also referred to hereinafter as the flank(s). In the following, for some layers, it is indicated that the layer under consideration is laterally delimited by a side surface comprising two parts (i.e.: by a first and second flank, here), in practice located opposite to each other. The side surface in question may nevertheless be continuous, and go all around the electrode without discontinuity, for example when the edge of this layer is circular (this side surface then being cylindrical); in this case, the two portions in question correspond to two portions of this continuous surface, situated opposite to each other. These two parts of the side surface of the layer may also correspond to two distinct faces of the perimeter of the layer in question, when this perimeter is, for example, rectangular, as shown here (rectangular seen from above the layer).
[
The first active layer 11 extends in parallel to the plane P. The plane P corresponds, for example, to the surface of a dielectric layer 61 on which the assembly 1 may rest (it should be noted, however, that, at the end of manufacture, the dielectric layer 61 may form part of an overall protective dielectric coating in which the assembly is coated).
The first and second upper electrodes 121, 122 extend on the first active layer 11. The first active layer 11 is delimited by an upper surface 112 and a lower surface 113, opposite to the upper surface 112. Each upper electrode 121, 122 extends, for example, on the upper surface 112 of the first active layer 11, against it. The lower surface 113 of the first active layer 11 at least partly rests for example on the dielectric layer 61, in parallel to the plane P.
The first upper electrode 121 is laterally delimited by the aforementioned side surface 1211, 1212. Said side surface comprises a first part (or portion) referred to hereinafter as the first flank 1211. The first upper electrode 121 may, as here, have an overall rectangular shape. It is then laterally delimited by four parts of the side surface (including the first flank 1211, and another part, opposite to it, called the fifth flank 1212 in the following), corresponding to the four sides of this rectangle.
Similarly, the second upper electrode 122 is laterally delimited by the aforementioned side surface, a part of which is referred to as the second flank 1222. The second upper electrode 122 may also have an overall rectangular shape. It is then laterally delimited by four parts of said side surface (including the second flank 1222, and another part, opposite to it, referred to hereinafter as the sixth flank 1221), corresponding to the four sides of this rectangle.
The first active layer 11 is also laterally delimited by a side surface, comprising at least two parts, opposite to each other, called third flank 1111 and fourth side 1122. The third and fourth flanks 1111, 1122 may be located as an extension of the first and second flanks 1211 and 1222 of the first and second upper electrodes 121, 122; in this case, the first flank 1211 (of the first upper electrode 121) and the third flank 1111 (of the first active layer 11) form the same, overall, flank of the first planar stack 11 as a whole (resulting from overall etching of the first stack); similarly, the second and fourth flanks 1222, 1122 then form another, overall, flank of the first stack as a whole. Here, the first active layer also has an overall rectangular shape.
The first planar stack 10 performs a memory function, and the first active layer 11 is a memory layer. It is used to store information, more precisely two pieces of data, in a non-volatile manner. Each piece of data is, for example, encoded in the form of a resistance value of a portion (conduction channel) of the active layer of said first stack 10. The first stack 10 may be of the PCRAM, CBRAM, OxRAM or MRAM type as described in the introduction of prior art. Each conduction channel of the first active layer 11 may have a so-called “low” state, i.e. a low resistance, for example below a resistance in the order of 10 kΩ, or even 10 kΩ, or a so-called “high” state, i.e. a high resistance, for example above 50 kΩ. Each conduction channel of the active layer 11 shifts from the high state to the low state when a voltage applied to this layer or a current flowing in the layer exceeds a programming voltage/current, also known as the “set” voltage/current. Each channel of the first active layer 11 shifts from the low state to the high state when a voltage or current applied to the layer exceeds an erase voltage/current, also called a reset voltage/current. The first active layer 11 comprises, for example, a hafnium oxide layer (in contact with a titanium layer acting tank for oxygen vacancies), in which case the first stack 10 performs the OxRAM function.
The first upper electrode 121 is conductive. It includes one or more layers, parallel to the plane P. One of these layers may be a metal layer. Another of these layers may be a layer for avoiding diffusion of species into the first active layer 11.
The nature of the upper electrode 121 is chosen, for example, as a function of the type of first active layer 11 and the material or materials of this layer. It can also be chosen according to the type of material implemented in the second active layer 21. It may, for example, comprise a sub-layer adapted to the memory layer 11, on the side of this layer, and on the side of the first active layer, and another sub-layer, adapted to the selector, on the side of the second active layer 21. Indeed, some selectors may require the implementation of one or more so-called active electrodes in order to function. Examples include TS (Threshold Switch) or MIEC (Mixed Ion-Electronic Conduction) type selectors. Indeed, conduction in these selectors implements diffusion or migration of metal ions for forming a conductive filament in the presence of an electric field. For example, a TS type selector implements diffusion of metal ions such as silver ions. These ions can be supplied by an “active” electrode, in contact with the selective layer and which comprises silver. According to the same principle, a MIEC type selector implements diffusion/migration of metal ions such as copper ions, in which case an active electrode in contact with the selective layer advantageously comprises copper.
Depending on the direction of voltage application or current flow in the second active layer 21, the first upper electrode 121 may be active with respect to the second active layer 21, i.e. include elements contributing to conduction of the selective layer. In this case, the first active upper electrode may comprise silver or copper. It includes, for example, several layers, at least one of which, and if possible the layer in contact with the second active layer 21, includes silver or copper.
The second active layer 21 may also include a plurality of layers, at least one layer of which, for example of which is in contact with the first upper electrode 121, includes elements which contribute to the conduction of the selective layer. This is, for example, a copper or silver layer. The copper or silver layer is, for example, disposed on the surface of the second active layer 21 in contact with the first upper electrode 121, as an extension of this electrode. The conductive layer 22 set forth below, which connects the second active layer 21 opposite to the electrode 121, may also comprise such a layer or sub-layer (acting, for example, as an active electrode), adapted to the active layer 21.
In this first embodiment, the first upper electrode 121 extends on a first portion 1210 only of the upper surface 112 of the first active layer 11, in particular at a first portion 114 of the first active layer 11 (part of the portion 114 being located in vertical alignment with a lower electrode 13).
The second upper electrode 122 is also conductive. It can also contribute to the operation of the third active layer 31 in the same way as the first upper electrode 121. In the same way as the first upper electrode 121, it includes one or more layers parallel to the plane P. In this first embodiment, the second upper electrode 122 extends on a second portion 1220 of the upper surface 112 of the first active layer 11, in particular at a second portion 115 of the first active layer 11 (part of the second portion 115 also being located in vertical alignment with the lower electrode 13).
The fifth and sixth flanks 1212 and 1222 face each other and are at least spaced apart by a first distance D1 (corresponding, for example, to the width of a trench separating these two electrodes, obtained by etching). The fifth and sixth flanks 1212 and 1222 are also separated by an insulating layer 62, electrically insulating the electrodes 121, 122 from each other. Indeed, the assembly 1 completed is buried in a dielectric material 62 enabling different elements to be insulated from each other, including the first and second electrodes 121, 122.
As already indicated, the second vertical stack 20 here acts as a selector, and the second active layer 21 is a selective layer. This means that it is configured to modify its conductivity as a function of a voltage applied to this layer, and/or as a function of an electric current flowing through it. A threshold voltage is defined above which the second active layer 21 is in an on state. This means that at least a part of the second active layer 21 is conductive. By conductive, it is meant that its resistance is less than 10 kΩ. Below the threshold voltage, the selective layer 21 is in a so-called “off” state. This means that the resistance of the second active layer 21 is, for example, greater than or equal to at least 100 kΩ. Some types of active layer 21 may, however, have a resistance that varies as a function of the voltage applied. The resistance can vary exponentially so that it is in the order of 10 kΩ or a few tens of kΩ just before switching from the off state to the on state. The on state is preferably metastable. This means that the second active layer 21 is initially in the off state and does not have an on state until a voltage applied to this layer becomes greater than the threshold voltage. The second active layer 21 can keep an on state provided that a current or voltage applied to said layer 21 is greater than a given holding current.
The second active layer 21 comprises for example a chalcogenide, for example an alloy based on selenium, germanium, antimony and nitrogen. In which case, the second stack 20 is an Ovonic Threshold Switching (OTS).
The second active layer 21 can also comprise a material such that the second stack 20 is a TS (Threshold Switch) selector, a MIEC (Mixed ion-electronic conduction) selector or even a metal-insulator transition selector. In these cases, an active upper electrode can be present on either side of the second active layer.
Similarly, the third stack 30 comprises at least a third active layer 31, which is a selective layer. The electrical characteristics of the second and third active layers 21, 31, including at least the threshold or holding voltages/currents, are similar or even identical.
The reduction in the overall size of assembly 1 especially results from the sharing of a same memory stud for two selectors, and from the oblique orientation of at least a part of the second active layer 21, located opposite the first flank 1211 of the first upper electrode 121, and of at least a part of the third active layer 31, located opposite the second flank 1222 of the second upper electrode 122.
The first upper electrode 121 electrically connects the first active layer 11 with the second active layer 21. Similarly, the second upper electrode 122 electrically connects the first active layer 11 to the third active layer 31. Thus, the first active layer 11 is common to the second and third vertical stacks 20, 30. In other words, it is the same first active layer 11 that is electrically connected to the second active layer 11 on the one hand and to the third active layer 31 on the other hand. The second and third active layers 21, 31 are separate from each other. They are electrically insulated from each other because they are only in contact via the first active layer 11.
By electrically insulated, it is meant that there is no direct electrical contact therebetween. In other words, there is no element, being conductive in all circumstances (for example metal), directly connecting them.
The second active layer 21 can be electrically connected between a first upper electrical contact 40 and the first upper electrode 121. Similarly, the third active layer 31 can be electrically connected between a second, upper electrical contact 50 and the second, upper electrode 122. The first and second contacts 40, 50 are electrically insulated from each other.
The memory and selector assembly 1 may be buried in a dielectric material, for example an insulating oxide filler 62 such as silicon oxide.
The first upper electrode 121 extends on the first portion 1210, referred to as the first surface, of the upper surface 112 of the first active layer 11. At least a part of the first portion 114 of the first active layer 11 is located in vertical alignment with the first surface 1210. The first upper electrode 121 influences electrical conduction at the first portion 114. For example, the application of a voltage between the first upper electrode 121 and the lower surface 113 of the first active layer 11 enables the first portion 114 (first conduction channel) to shift from its highly resistive state to its low resistive state, or vice versa. The first portion 114 can therefore perform a memory function locally.
In the same way, the second upper electrode 122 influences electrical conduction at the second portion 115 of active layer 11. The second portion 115 can therefore also perform a memory function locally.
Since the first and second upper electrodes 121, 122 are separated from each other, the first and second portions 114, 115 of the first active layer 11 are therefore also separated from each other (unless the dimensions of the conduction region are close to or greater than the distance separating the two upper electrodes, in which case the first and second portions 114, 115 of the first active layer 11 may be too close and it may be desirable to separate the active layer 11 into two distinct parts, as in the case of
Assembly 1 thus comprises two 1S/1R type memory/selector circuits (the selector being connected in series with the resistive memory element), operable independently of each other.
The arrangement of the first portion 114 depends on the arrangement of the first upper electrode 121 on the first active layer 11 and therefore on the position and dimensions of the first surface 1210. In the example of [
The first surface 1210 therefore also extends, from this edge, over the second distance D2.
Electrical properties of the first portion 114 partly depend on its dimensions. The particular structure of assembly 1 thus makes it possible to adjust electrical properties of the resistive memory associated with the first portion 114, as a function of the arrangement of first upper electrode 121 on first active layer 11, in particular as a function of the extent of this first electrode, and as a function of its positioning more or less in vertical alignment with the lower electrode 13.
Similarly, assembly 1 enables electrical properties of the resistive memory associated with the second portion 115 to be adjusted as a function of the arrangement of the second upper electrode 121 on the first active layer 11.
A portion of the second active layer 21, referred to as the third portion 211, is in contact with the first flank 1111 of the first upper electrode 121. The first upper electrode 121 can also influence electrical conduction at this third portion 211. For example, the application of a voltage between the first upper electrode 121 and an opposite surface of the second active layer 21 enables the third portion 211 to shift from its off state to on state. The third portion 211 therefore locally provide a selector function.
Electrical properties of the third portion 211 also partly depend on its dimensions. The dimensions of the third portion 211 especially depend on the surface (i.e. the area) of the first flank 1111. Adjustment of the surface area of the first flank 111, obtained for example by adjusting the thickness of the layer 121, therefore makes it possible to adjust electrical properties of the selector associated with the third portion 211. The surface area of the first flank 1111 can, for example, be adjusted as a function of the thickness D3 of the first upper electrode 121.
The assembly 1 therefore enables dimensions of the memory associated with the first portion 111 and the selector associated with the third portion 111 to be adjusted independently. Thus, electrical properties of said selector and said memory can be independently adjusted.
The same reasoning applies to the fourth portion 311 (portion of the third active layer 31). By adjusting the area (i.e. the surface extent) of the second flank 1222, it is possible to adjust electrical properties of the selector associated with the fourth portion 311.
The assembly 1, comprising two 1S1R circuits, enables electrical properties of each selector and each memory to be adjusted independently.
The first planar stack 10 comprises a lower electrode 13, in contact with the lower surface 113 of the first active layer 11. A part of the first upper electrode 121 extends opposite a part of the lower electrode 13. In other words, the part of the first upper electrode 121 is superimposed by vertical projection to the lower electrode 13. By vertical projection, it is meant along a vertical direction as previously defined.
Here, only part of the first upper electrode 121 is superimposed on the lower electrode 13. Thus, the fifth flank 1212 is located above the lower electrode 13, in vertical alignment with it, whereas the first flank 1211 is laterally offset with respect to the lower electrode 13 and is not located in vertical alignment with the lower electrode 13, above it. In vertical alignment is meant to be aligned along a vertical direction. The memory associated with the first portion 114 of the active layer 114 then forms between the facing surfaces 1230 (i.e.: in superimposition) of the first upper electrode 121 and the lower electrode 13. The lateral offset between the first upper electrode 121 and the lower electrode 13 makes it possible (as does the reduced width D2 of the upper electrode) to obtain, for the memory in question, an effective surface area (in this case a surface on which there is superimposition between the electrodes 121 and 13) smaller than F2, where F is an etching fineness of the manufacturing technology considered at the level considered in the BEOL. The fact that it is possible to obtain a surface area smaller than F2 is surprising at first sight. This is especially due to the particular geometrical structure of the assembly 1, and to the fact that alignment accuracies during etching or deposition (accuracy better than 15 nm, for example) can be better than fineness F (equal to around forty nm, for example).
The area S1230 of the surface 1230 facing the first electrode 121 can then be expressed as (see
Considering, for example, D2=⅔ F, D7=½ F and D13=2 F, the surface area 1230 is then equal to ⅓ F2, which is much less than F2 (D13 is the width of the lower electrode 13, in parallel to the plane P, and along a direction perpendicular to X—therefore along a direction perpendicular to that corresponding to the width D5).
Similarly, only a part of the second upper electrode 122 extends opposite a part of the lower electrode 13 (or by vertical projection on it), in vertical alignment with it. The sixth flank 1221 is located above the lower electrode 13, in vertical alignment with the same, while the second flank 1222 is laterally offset with respect to the lower electrode 13: it is not located in vertical alignment with the lower electrode 13 (it is not located above the same).
Some variability in electrical characteristics of the first planar stack 10 may be caused by manufacturing steps of said stack 10 or vertical stacks 20, 30 introducing defects in a part of the first active layer 11. The defects are generally located at the flanks of the first active layer 11 (i.e. especially at the third and fourth flanks 1111, 1122), exposed to etching or deposition steps. Electrical characteristics at these flanks are then modified locally. It is then planned to move the third and fourth flanks 1111, 1122 away from each other, so that they are separated by a third distance D4, greater than a width D5 of the lower electrode 13. Thus, each memory associated with the portions 114, 115 of the first active layer, is away from the flanks 1111, 1122 of the first active layer 11. They are thus little influenced by electrical characteristics at the third and fourth flanks 1111, 1122. Each memory thus has minimal variability in its electrical characteristics.
The first distance D1 between the first and second upper electrodes 121, 122 is, for example, between 40 nm and 90 nm.
The third distance D4 separating the third and fourth flanks 1111, 1122 is for example between 60 nm and 110 nm, or even between 80 nm and 100 nm. This reduces variability in the electrical characteristics of the memory stack, set by those of the conduction channels located away from the flanks (away from the edges).
The partly vertical orientation of the second and third stacks 20, 30, and the use of a common, planar first active layer 11, means that the third and fourth flanks 1111, 1122 can be spaced apart from each other, as indicated above, to reduce variability problems, without increasing overall size of the assembly 1, compared to 1R1S devices of prior art, at least from the point of view of overall size along direction X represented in
In the direction X, each vertical stack 20, 30 extends, from the first flank 1111 of the first upper electrode 12, over a fourth distance D6. In the first embodiment, this distance corresponds as it were to the total thickness of the second stack 20 and of an optional metal layer 42 covering it. Furthermore, the first flank 1111 is laterally offset, with respect to the lower electrode 13, by a fifth, non-zero distance D7. Similarly, the second flank 1222 is laterally offset, with respect to the lower electrode 13, by the same fifth distance D7. Therefore D4=D5+2−D7. The first upper electrode 121 is therefore only partially superimposed on the lower electrode 13.
In practice, the width D5 of the lower electrode 13 is at least equal to the etching fineness, F, which is 40 nm for example. The fineness especially imposes a minimum width on a lower via 70, passing through the dielectric layer 61 to connect the lower electrode 13. The width D5 of the lower electrode 13 and a width of the lower via 70 are equal to each other. The width D5 is therefore at least equal to the fineness F.
The first distance D1 separating the first and second upper electrodes 121, 122 advantageously depends on the width D5 of the lower electrode 13. In order to allow face-to-face contact between the upper electrodes 121, 122 and the lower electrode 13, the first distance D1 is preferably strictly less than the width D5. In practice, the conduction channels can still be established if there is no face-to-face contact between the upper electrodes 121, 122 and the lower electrode 13. However, this may increase variability in the conduction channels established in the first active layer 11.
Similarly, the first and second electrical contacts 40, 50 respectively have a width D8 and D9 at least equal to this fineness F (i.e.: limited by the fineness F), and separated by the first distance D1.
Dimensioning the assembly so that the sum D6+D2 is, as here, less than or equal to the width D8 (width along the direction X) of the first upper contact 40 thus enables the second stack 20 to be housed beneath this contact, as well as the part of the first planar stack 10 which laterally projects beyond the lower electrode 13. The overall size of assembly 1 takes account of an additional distance, due to the space separating the assembly from its close neighbours (known as the “metal pitch”). Said distance is equal to F (F/2 on each side of the assembly 1). Thus, along direction X, the overall size is 4 F, even though the first active layer 11 has a lateral extension greater than F (to limit the undesirable influence of the layer edges).
By way of example, and depending on the etching fineness F, the assembly 1 may have the following dimensions:
D11 is the width of the upper electrodes 121, 122, is parallel to the plane P, and along a direction perpendicular to X—thus along a direction perpendicular to that corresponding to the width D5. The side surface of the upper electrodes 121, 122 is laterally offset with respect to the lower electrode 13 by a distance D11 along the direction perpendicular to X.
The total surface area STOT occupied by the assembly 1 (i.e. its footprint, including a peripheral zone surrounding the assembly, and which stops halfway between this assembly and neighbouring assemblies) can be expressed as:
where MP is a space between each assembly, called a metal pitch, for example equal to F.
In practice, D14 is equal to D7. The total surface area STOT is then equal to 15 F2, for these example values. As assembly 1 comprises two 1S1R circuits, an equivalent occupied surface area S1S1R, for a single circuit 1S1R is therefore equal to 7.5×F2, here. This is greater than the surface area occupied by a 1S1R circuit in a conventional purely planar design, for which this surface area may be 4×F2 (comprising the peripheral zone mentioned above, which surrounds the memory point). On the other hand, the arrangement set forth here offers the advantage of being able to adjust, independently, the surface areas of each memory and each selector (and to have effective surface areas, for the active zones, which are less than F2).
Viewed in cross-section, the second active layer 21 comprises, for example, a vertical portion and two planar portions at each of its ends. Seen in cross-section view, it thus forms an ‘S’ which can be housed beneath the first contact 40, in line with it, without laterally protruding therefrom. In line with is meant to be in vertical alignment.
The two planar portions of the active layer 21 are optional. The active layer 21 could be entirely vertically oriented and disposed beneath the first contact 40.
In the same way, the third active layer 31, at least partly vertically oriented, allows the first active layer 11 and/or the second upper electrode 122 to extend to beneath the second contact 50 without increasing overall size of the assembly 1 (in the direction X).
The storage density offered by an array of memory points partly depends on the spacing imposed between two-by-two addressing rows and/or two-by-two addressing columns. The smaller the spacing, the greater the storage density of the final array. This spacing, which corresponds to the first distance D1 between the first and second electrical contacts 40, 50, intended to be connected to the addressing rows/columns, or which directly form these addressing rows/columns, is limited in practice by the etching fineness F.
The first planar stack 10 is also electrically connected to the lower via 70 mentioned above (or to another equivalent conductive element). The dielectric layer 61 on which the first planar stack 10 rests has this lower via 70 passing therethrough. The lower via 70 can thus be electrically connected to the lower surface 113 of the first active layer 11 through the lower electrode 13. The lower via 70 and the lower electrode 13 can moreover be made of the same material and as an extension of each other, so that they are indeed one and the same. Thus, the first active layer 11 is electrically connected in series between the first upper electrode 121 and the conductive via 70 on the one hand and the second upper electrode 122 and the conductive via 70 on the other hand. The lower electrode 13 may comprise one or several sub-layers, acting for example as a tank layer for oxygen vacancies (such a layer being made of titanium, for example), or as an insulating layer opposing the passage of oxygen (titanium nitride layer, for example), or playing yet another role in the operation of the first stack 10 as a memory stack.
The lower electrode 13 extends on a part, here only a part, of the lower face 114 of the first active layer 11.
The second stack 20 may, as here, comprise a conductive layer 22. The conductive layer 22 electrically connects the second active layer 21 to the first upper contact 40. Here, it is disposed between the second active layer 21 and the first upper contact 40. Here, the conductive layer 22 extends on the second active layer 21, against it. Advantageously, at least a part of the conductive layer 22 also extends in parallel to the first flank 1211 and opposite this first flank 1211. This conductive layer 22 may, for an OTS type selector, for example, be based on titanium nitride, tantalum nitride, tungsten, or tungsten nitride, or even carbon.
The conductive layer 22 and the second active layer 21 of the second stack advantageously extend, in the portion facing the first flank, at a distance D10 advantageously less than or equal to 20 nm, or even 10 nm. In other words, this is the height of the selector.
Similarly, the third vertical stack 30 may comprise a conductive layer 32 electrically connecting the third active layer 31 to the second upper contact 50.
The first electrical contact 40 may comprise a first upper via 41 which extends, for example, vertically from the second stack 20. In order to improve electrical contact between the first contact 40 and the second stack 20, the same may also comprise a first metal layer 42, electrically connecting the second stack 20, interposed therebetween. The first metal layer 42 extends, for example, partly over the second stack 20, covering a vertical part and a planar part of said second stack 20. In one development, the first metal layer 42 is the conductive layer 22 of the second stack 20. The first metal layer 42 could also form one of the addressing columns of the array, the via 41 being a connection via of this column, possibly offset with respect to the assembly 1.
Similarly, the second electrical contact 50 may comprise a second upper via 51 extending, for example, vertically from the third stack 30. It may also comprise a second metal layer 52 electrically connecting the third stack 30. The second metal layer 52 may also extend on the third stack 30, covering a vertical part and a planar part.
As already indicated, the second active layer 21 is electrically connected to the first upper electrode 121 of the planar stack 10. In the embodiment of [
Thus, the second active layer 21 has a portion disposed between the conductive layer 22 of the second stack 20 and the first upper electrode 121. When the second active layer 21 is, for example, of the OxRAM or CBRAM type, the application of a potential difference between the conductive layer 22 and the first upper electrode 121 during an initial forming operation (first creation of a conductive filament) results in the formation of a conduction channel, in the second active layer 21, at a zone located opposite the first flank 1211, of the first upper electrode 121. The position of the conduction channel is therefore controlled (and, herein, is also remote from the edges—i.e. the ends—of the first active layer), making it possible to reduce variability of the second vertical stack 20.
The second active layer 21 may comprise a planar portion, covering part of the first upper electrode 121. In this way, in order to keep location of the conduction channel at the first flank 1211 of the first upper electrode 121, assembly 1 may then comprise an insulating layer 141, 142. This is for example a layer of dielectric material, such as silicon nitride, especially to form a hard mask. At least a portion 141 of the insulating layer is disposed between said planar portion of the second active layer 21 and the first upper electrode 121, to insulate them electrically from each other. The insulating layer 14 may also extend continuously on the two upper electrodes 121, 122 of the first planar stack 10, as in the alternative embodiment represented in [
The insulating layer 14 is for example delimited by at least one side surface. When the insulating layer 14 is continuous and in one piece, it is then delimited by a single side surface 1411, 1422. The side surface of the insulating layer 14 comprises two parts, opposite to each other, called the ninth flank 1411 and tenth flank 1422 hereinafter, for example located as an extension of the first and second flanks 1211, 1222. When the insulating layer 14 is divided into two distinct portions 141, 142, it is then delimited by two side surfaces, each delimiting a portion 141, 142. The first portion 141 of the insulating layer may be located in vertical alignment with the first upper electrode 121, and may comprise, in addition to the ninth flank 1411, another part of its side surface, referred to here as the eleventh flank 1412. Similarly, the second part 142 may be delimited, in addition to the tenth flank 1422, by another flank called the twelfth flank 1421. The eleventh and twelfth flanks 1412, 1421 are for example located respectively as an extension of the seventh and eighth flanks 1212, 1221, of the first and second upper electrodes 121, 122.
[
Indeed, in this second embodiment, the assembly 1 further comprises an electrically insulating spacer 151 which extends against a part of the side surface 1211, 1222 of the first upper electrode 121, and against the side surface 1111, 1122 of the first active layer 11. This spacer 151 especially extends against the third flank 1111 of the first active layer 11 and against a part of the first flank 1211 of the first electrode 121. It makes it possible to reduce surface area of the second active layer 21 in contact with the first flank 1211, for adjusting electrical properties of the selector established in this layer. Indeed, reducing thickness D3 of the first upper electrode 121 may present a limit, especially in technological terms. Due to the presence of this spacer 151, only an upper strip 12111 of the side surface of the first electrode 121, especially of the first flank 1211, is in contact with the second active layer 21. Furthermore, the spacer 151 protects the flank 1111 of the first active layer, especially from possible contamination, for example during the steps of manufacturing the assembly, such as the operations of forming the second and third stacks 20, 30.
The first upper electrode 121 can have an additional conductive layer 121′ thereabove, as a vertical extension of the upper electrode 121 (and its first flank 1211). In this way, the first flank 1211 has a total thickness D3 equal to the initial thickness D31 of the first electrode 121 plus an additional thickness D32 of the additional conductive layer 121′. The upper strip 12111 of the first flank 1211 left exposed by the spacer 151 may thus be equal to the additional thickness D32, or even less.
A part of the spacer 151, or possibly another similar spacer, may extend partially between, on the one hand, the first stack and, on the other hand, the third active layer 31. It may especially extend on the second flank 1222 and the fourth side 1122, only partially covering the second flank 1222, in order to expose an upper strip of the second upper electrode, against which the third active layer 31 is in contact.
[
The first and second parts 116, 117 are advantageously separated by the first distance D1. The physical separation between the two parts 116, 117 makes it possible to electrically insulate the conduction channels that can be established between each upper electrode 121, 122 and the lower electrode 13. In this way, memories can be operated independently of each other, even when the distance D1 between the two parts 116, 117 is small, less than 60 nm, or even less than 40 nm. As a reminder, when the first active layer comprises an ovonic material, the conduction channels can have a lateral dispersion of up to 40 nm or even 60 nm. The first and second parts 116, 177 may be in contact with each other, but separated from each other by an insulating barrier, such as a dielectric layer.
The subdivision of the first active layer 11 into two parts (116 and 117) results here from an etching of the whole, of a block, of an initial stack comprising an initial active layer, in one piece, and, on top of this, an upper electrode layer, in one piece (said etching separating this electrode layer to obtain the first and second upper electrodes 121, 122).
[
The fourth memory stack 10′ comprises a fourth active layer 16, a third electrode 171 and a fourth electrode 172. The fourth active layer 16 is also a memory layer. In this example, the fourth active layer 16 is divided into a first part 161 and a second part 162.
The first and second upper electrodes 121, 122 are separated from the third and fourth electrodes 171, 172 by the insulating layer 14. The fourth active layer 16, here its first and second parts 161, 162, extend on, against and above the third and fourth electrodes 171, 172. The third and fourth electrodes 171, 172 are advantageously distinct and separated by an insulator 62, such as a dielectric material. They have no direct electrical contact with each other and are thus electrically insulated from each other.
The first planar stack 10 comprises a lower electrode 13, the first active layer 11 being connected to the lower electrode 13. The fourth planar stack 10′ may also comprise a fifth electrode 18, extending on and above the fourth active layer 16. The fourth active layer 16 is thus electrically connected between the third and fourth electrodes 171, 172 on the one hand, and the fifth electrode 18 on the other hand. The fifth electrode 18 can also be electrically connected to a via, called the upper via 70′, located above the fourth planar stack 10′. The upper via 70′ is disposed between the first and second electrical contacts 40, 50, from a lateral point of view.
The third electrode 171 is also delimited by a side surface comprising at least one vertically oriented flank 1711, referred to as the first additional flank. The first additional flank 1711 is parallel to the first flank 1211 of the first upper electrode 121. The first additional flank 1711 is preferably aligned with the first flank 1211 of the first upper electrode 121, located as an extension thereof. In practice, the overall stack formed by the first planar stack 10, the insulating layer 14 and the fourth planar stack 10′ which covers it, can be laterally delimited during a same overall etching operation, yielding a same overall flank which extends on the entire height of this overall stack (and this on each side, or on each side face of this overall stack).
The second active layer 21 of the second vertical stack 20 vertically extends on an entire part of the height of this overall stack (here, over the entire height of this overall stack, and even more). It extends not only opposite the first flank 1211, the first upper electrode 121, but also opposite the first additional flank 1711, the third electrode 171, in parallel to these flanks 1211, 1711. In this way, the second active layer 21 of the second vertical stack 20 can comprise two distinct conduction channels 211, 212 (one, 211, located in front of the first flank 1211, and the other, 211, located in front of the first additional flank 1711), addressable independently of each other, each enabling a distinct piece of information to be encoded. The single active layer 21 thus makes it possible to form two distinct “selectors”.
Like the second active layer 21, the third active layer 31 vertically extends on a part of the height of the overall stack in question (here, over the entire height of this overall stack, and even more). It extends not only opposite a second flank 1222 partly delimiting the second upper electrode 122, but also opposite a second additional flank 1722 of the fourth electrode 172, in parallel to these flanks 1222, 1722.
The fourth active layer 16 is divided into a first part 161 and a second part 162. Said first part 161 extends on the third electrode 171, for example as an extension of the same. Said second part 162 extends, in the same way, on the fourth electrode 172.
The fifth electrode 18 is insulated from each vertical stack 20, 30. It is, for example, insulated by means of additional insulating spacers 152 extending on either side of the fifth electrode 18. The fifth electrode 18 can thus have a smaller width than the lateral extension of the fourth active layer 16 (as for the lower electrode 13 and the first active layer 11). Advantageously, the fifth electrode 18 has a width such that it has at least one part facing each of the third and fourth electrodes 171, 173.
[
The electrical diagram of assembly 1 comprises two circuits connected to a common row 81a. A first circuit comprises the first portion 114 of the first active layer 11, connected in series with the second vertical stack 20. Both are connected between the lower electrode 13 and the first electrical contact 40. The lower electrode 13 is for example connected to the address row 81a and the first electrical contact is connected to a first addressing column 82a. A second circuit comprises the second portion 115 of the first active layer 11, connected in series with the third stack 30, both being connected between the lower electrode 13 and the second electrical contact 50. The second electrical connector is connected to a second addressing column 82b.
[Table 1] below shows a voltage bias diagram for the addressing rows and columns 81a-b, 82a-b for programming a low-resistive state (SET), or erase (writing a high-resistive state, or RESET) operations in each of the first and second memory stacks 20, 30. This is a ‘V/2’ type bias diagram. There are other bias schemes. According to the “V/2” bias scheme, the value of the voltage U applied is chosen so that:
The invention also relates to a method for manufacturing an assembly 1 of memories and selectors as described previously. A mode of implementation of said method is described with reference to [
[
The first intermediate stack 912a comprises, for example from the surface of an addressing row 81a, a lower via 70 and a first planar stack 10 comprising a lower electrode 13, a first active layer 11, a first upper electrode 121 and a second upper electrode 122, each extending on the first active layer 11. The first and second electrodes 121, 122 have an insulating layer 14 thereabove. The first active layer 11 is a memory layer. It is divided into two parts 116, 117 separate from each other. The first intermediate stack 912a thus makes it possible to eventually obtain an assembly 1 according to the embodiment of [
To obtain said first intermediate stack 912a, the manufacturing method initially comprises a step of forming the first planar stack 10. This step may comprise a sub-step of forming the lower electrode 13, extending for example as an extension of the lower via 70. The lower via 70 and the lower electrode 13 are not differentiated in [
Each addressing row 81a, 81b and each lower via 70 can be made by the implementation of a damascene method. This involves, for example, depositing a dielectric material, etching cavities for forming the addressing rows 81a, 81b or the lower vias 70 and filling said cavities with a liner, for example of titanium nitride, and a conductive material, for example tungsten, followed by chemical mechanical polishing (or CMP). The addressing rows 81a, 81b are buried in the dielectric layer 61. Each lower via 70 passes through the dielectric layer 61.
Each lower electrode 13 is made as an extension of each lower via. Said dielectric layer 61 and each lower electrode 13 are levelled, for example by means of planarisation.
The formation step further comprises a sub-step of forming a first layer 910a, extending in parallel to the plane P, as illustrated in [
The step of forming the first stack 10 also comprises a sub-step of forming a second layer 910b, for forming the first and second upper electrodes 121, 122. The second layer 910b extends in parallel to the plane P, and rests on the first layer 910a. The second layer 910b is formed from a conductive alloy, for example TiN.
The formation step also comprises a sub-step of delimiting the first and second layers 910a, 910b so as to form the first active layer 11. The first active layer 11 is thus delimited by third and fourth flanks 1111, 1122.
The delimitation sub-step is also carried out so as to obtain the first upper electrode 121 and the second upper electrode 122. The first upper electrode 121 is thus laterally delimited by at least one first flank 1211 and the second upper electrode 122 is delimited by at least one second flank 1222. In practice, the first active layer 11 and the upper electrodes 121, 122 are laterally delimited during a same etching step.
The first and second upper electrodes 121, 122 are also separated during the delimitation sub-step. The delimitation is for example carried out by a first etching, as illustrated by [
After the first etching, the trench can be filled with a dielectric material 62. After deposition, the dielectric material 62 is advantageously planarised so as to be flush with the upper surface of the upper electrodes.
The first layer 910a can also be divided into two parts during the first etching. Thus, at the end of the second etching, the first active layer 11 comprises two distinct parts 116, 117, as an extension of the first and second upper electrodes 121, 122.
The first intermediate stack 912a may also comprise an insulating layer 14, extending on the upper electrodes 121, 122. In which case the method may also comprise a sub-step of depositing an insulating layer onto the first and second layers 910a, 910b so that delimiting the same also delimits the insulating layer 14. The insulating layer can be deposited between the first and second etchings described previously. In this way, the insulating layer 14 continuously extends from the first upper electrode 121 to the second upper electrode 122.
[
The second intermediate stack 913a may also comprise an overall conductive layer 9132 extending on the overall active layer 9131, intended to form the conductive layers 22, 32 of the second and third stacks 20, 30. It may also comprise an additional conductive layer, intended to form at least a part of the first and second electrical contacts 40, 50. Here, the additional conductive layer may be intended, after etching, to form addressing columns of the array.
The formation of the second and third stacks 20, 30 firstly comprises a sub-step of depositing the overall active layer 9131 onto the first planar stack 10 and onto the dielectric layer 61. At least a first part of the overall active layer 9131 extends in parallel to the first and second flanks 1211, 1222 of the upper electrodes 121. It extends especially at least partly opposite the first flank 1211 of the first upper electrode 121 and the second flank 1222 of the second upper electrode 122. Deposition of the overall active layer 9131 is conformally performed, for example so as to have a substantially constant thickness at all points. By substantially constant, it is meant to within at least 20%, for example to within 10% or even 5%, or even better. This conformal deposition is achieved, for example, by ‘ALD’ (Atomic Layer Deposition).
The method may further comprise a sub-step of depositing the conductive layer 9132, for example by conformal deposition, so that it extends on the overall active layer 9131. The method may also comprise a sub-step of depositing the additional conductive layer, for example also by conformal deposition, so that it extends on the conductive layer 9132.
[
To obtain the second and third selective stacks 20, 30, the method comprises etching the overall active layer 9131 so as to separate it into a second active layer 21 and a third active layer 31. Etching is carried out so that at least a first part of the second active layer 21 extends in parallel to the first flank 1211 of the first upper electrode 121, opposite this first flank 1211, and so that at least a second part of the third active layer 31 extends in parallel to the second flank 1222 of the second upper memory electrode 122, opposite this second flank 1222.
Etching can be stopped before reaching the insulating layer 14. However, according to one development, the overall active layer 9131 and the first planar stack could be etched at one time, thus dividing each layer into two distinct parts. In any case, etching is stopped before reaching the lower electrode 13.
Alternatively, etching step 922 may simultaneously etch conductive layer 9132 in two parts so that they form conductive layers 22, 32 respectively, extending for example over second and third active layers 21, 31 respectively. For the assembly formed to be functional, it is necessary for the etching step to divide at least the layer 9132.
The electrical contacts 42, 52 are formed, for example, at the same time as the etching of the conductive layer 9132. It thus enables the electrical contacts 42, 52 to be electrically separated from each other.
The etching step can also be used to electrically separate neighbouring second intermediate stacks 913b, 913c, 913d by separating the layers 9131, 9132 deposited onto each first planar stack 10.
[
| Number | Date | Country | Kind |
|---|---|---|---|
| FR2114399 | Dec 2021 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/087638 | 12/22/2022 | WO |
