A typical power management system of an electric or hybrid vehicle is shown in
In some cases, the power management system also includes a cell balancing circuit 105, which compensates for different states of charges (SOC) of individual cells, as shown in
The balancing circuits can be divided into two general categories. The first one is the passive balancing systems, in which the cells are balanced by dissipating energy from excessively charged cells, through resistors.
The second category is the active balancing systems, which are far more efficient. In these systems, the energy of over-charged cells is transferred to those with less charge using dc-dc converters. Even though the benefits of the active cell balancing are known, their use is relatively sparse, due to the overly large extra cost and weight the cell balancing circuits add to the system.
Balancing systems of possible interest include those described in the following US patent published applications:
A prior-art balancing circuit 105 might utilize a buck-boost and a Cuk converter for cell balancing. These topologies can be implemented with a relatively small number of active components and regulated with fairly simple controllers. However, these circuits are fairly large in form factor, which reflects on the overall physical size of the system. Implementations based on the use of a bi-directional flyback and a two stage flyback converters have been proposed. Compared to other solutions, these systems lower efficiency at high power levels.
Others have proposed a configurable system for cell balancing using a large number of switches to transfer the energy between cells. The main drawback of such a system is that the balancing becomes too slow for the energy transfer between cells having similar output voltages.
Many prior-art approaches direct themselves only to a single one of the functions suggested by the functional blocks of
It would be desirable if a way could be found to accomplish the aims of the functional blocks of
What is described is a battery management architecture that eliminates previously described problems of the previous solutions and compensates for the extra cost of a cell-balancing circuit. These advantages are achieved by integrating the voltage step-up and balancing functions as well as charging functions inside a single converter topology. Instead of providing the entire output voltage and power, the converter in this configuration is merely assisting the battery by providing a portion of the power delivered to the load, rather than the entirety of the power delivered to the load. This portion of power is proportional to the difference between the output and the battery pack voltages.
The invention will be described with respect to a drawing in several figures.
Where possible, like reference numerals have been employed for like elements.
The introduced topology, here referred to as an “assisting converter” architecture, is shown in
As described below, the assisting configuration drastically reduces power processing requirements needed to achieve required conversion and, consequently, improves power processing efficiency. The introduced topology also allows fast cell balancing even when the cells have similar or equal voltages and allows energy transfer between any two cells in the battery pack. Furthermore, unlike other solutions, the topology provides functionality of the system even when a significant number of cells in the battery pack are out of function, potentially improving overall system reliability.
The principle of operation of a general assisting converter 106 shown in
P
out
=V
out
I
out=(Vbatt+Vcf)Iout=Pconverter+Pbatt
where Pconverter=VcfIout is the portion of the battery power delivered through the converter and Pbatt
For the conventional converter 103 (
where ηconverter is the efficiency of the assisting converter 106. This expression can be explained by looking at the system of
For example, if the assisting converter 106 is providing a 20% of the output voltage and has a very low power processing efficiency of 50%, a relatively high power processing efficiency of 90% at the system level still can be achieved. The system may be designed so that the capacitor 107 carries only 20% of the voltage intended to be delivered to the load, or only 10%, or only 5%.
This shows that, in order to achieve targeted overall system efficiency, the assisting converter 106 (
It will be helpful to characterize some of the benefits of the inventive topology of
Yet another benefit presents itself, namely that even if a particular cell fails “open” the system will be able to maintain a substantial portion of its function despite loss of that cell. Indeed the system will be able to continue its function even with loss of two or more cells in an “open” failure mode.
Finally the alert reader will appreciate that the topology of
It will be recalled from
An implementation of the assisting converter 106 based on a multi-phase isolated dual active bridge converter is shown in
Another interesting feature of the DAB is that it can operate with both continuous input and continues output currents, thus reducing requirements for input and output filters.
The system of
The linkage between the transformer 123 and its respective cell 121 is by means of an active bridge 122. The active bridge 122 has four semiconductor switches, typically FETs (field-effect transistors).
The linkage between the transformer 123 and the capacitor 107 is also by means of an active bridge 124. The active bridge 124 also has four semiconductor switches, typically FETs (field-effect transistors).
It is these semiconductor switches that are driven by control signals 128 from the controller 125. The control signals have phase relationships which bring about for example a draw of current from one or another of the cells, or a pumping of current into one or another of the cells, and which bring about a charging-up of capacitor 107 or a drawing-down of capacitor 107.
An implementation based on a multi-winding transformer is also possible. This is shown in
The digital controller 125 implementing phase-shift modulation regulates the operation of this converter 106. The phase shift control provides both the output voltage regulation (charging of capacitor 107 to tend toward a constant voltage available to load 104) and cell balancing (balancing the energy content of the various cells) through the regulation of the currents to and from the individual cells.
Typical waveforms of a DAB converter connected between two DC sources are shown in
where VA and VB are the amplitudes of the two sinusoidal sources, φk is the phase shift (delay) between the voltages, and ωL the impedance value of an inductor placed between them. In the case of
where Vcell is the voltage of the battery cell (e.g. 121 in
The non-overlapping times prevent simultaneous conduction of both switches of a single converter branch, that is, they prevent a short circuit.
Eight equivalent circuits of
Mode 1 corresponds to the time interval t0 to t1 of
Mode 2 occurs during the time interval t1<t≦t2. This mode starts when iPE(t), that is iL(t), changes polarity and has the same state of switches as Mode 1.
Mode 3 occurs during the transistors' non-overlapping time (between t3 and t4) when all of the switches are turned off. It can be seen that in this mode a resonant circuit consisting of the Lp and the capacitive network Cpar11 to Cpar14 is formed, meaning that oscillations might occur, depending on the speed of the body diodes of the MOSFETs. Ideally, for the case when the antiparallel body diodes are fast, a soft transition between Mode 3 and Mode 4 occurs. This happens when the Cpar13 is discharged to a value of approximately −VF and the charge of Cpar11 is approximately equal to Vcell+VF, where VF is the forward voltage drop of the body diodes, shown in the equivalent circuit of Mode 4.
In Mode 4, the anti-parallel diodes conduct and the maximum voltage across the transistors is clamped to a value of Vcell+2VF.
For the case when the body diodes of the MOSFETs are slow, compared to the period of the resonant circuit oscillations, and, hence, are not able to react, the circuit does not go through Mode 4. The amplitude of the overshoot is directly proportional to the energy stored in the leakage inductance at the time instant t3, i.e. WE=½iL(t3)2Lp, and inversely proportional to the equivalent of the Cpar11-Cpar14 capacitive network.
Mode 3 (or Mode 4) is followed by Mode 5. Mode 5 starts immediately after Q12 and Q13 are turned on and occurs during the time interval t0<t≦t5. This mode is equivalent to Mode 1. If prior to this mode the DAB was in Mode 4, both transistors turn on softly, with zero voltage transition. For a slow body diode case, i.e. when the previous state is Mode 3, a soft transition cannot be guaranteed and, consequently, increased switching losses occur.
A similar analysis can be carried out for Modes 6 to 8.
The discussion just given shows that the parasitic drain source capacitance increases the voltage stress across the switches and negatively affects the converter efficiency for the case when the antiparallel diode is slow compared to the frequency of oscillations. The discussion also indicates that the voltage stress value and the frequency of oscillations are inversely proportional to the equivalent capacitance of the Cpar11-Cpar14 network.
To minimize this effect a straightforward solution would be to use faster Schottky diodes connected in parallel with the body diodes of the transistors. These diodes would provide snubber action. They would allow the converter 106 to enter Mode 4, described in the previous discussion, and consequently would eliminate voltage overshoots while providing zero voltage switching (ZVS).
To minimize the cost, in this case, instead of using extra Schottky diodes, a small ceramic capacitor is placed in parallel with each of the transistors. These capacitors, labeled as Cs in
The waveform of
To eliminate this effect a decoupling capacitor Cdec 141 is placed across the primary side bridge, as shown in
In addition to eliminating the large ripple, Cdec 141 can also be potentially used for improving the reliability of the system in the case of a battery cell failure. In such a situation the capacitor can act as a replacement for the battery, capable of maintaining the cell voltage and transferring reactive power.
The main goal of the controller 125 of
The relative phase shifts between the DAB switches on the primary sides (for example bridge 122) are adjusted based on the cells' state of charge (SOC) (input 126). The calculation of the relative phase shifts between primary side modules is performed by the Primary side phase shift calculator (167), which sends four control signals, jr1[n] to jr4[n], to the Primary side phase shift modulator 128, for each of the bridges such as 122.
What was just described is passing the analog voltage to an ADC and then carrying out a digital difference calculation and carrying out later steps digitally. The alert reader will appreciate that there are many ways to provide a controller that will offer the benefits of the invention. The controller 125 may be implemented by appropriate firmware in a microcontroller of suitable bandwidth. Alternatively it may be implemented by an FPGA with suitable programming. Another approach could be the use of hardware combining mixed-signal circuits, for example analog-to-digital converters for measurement, and digital logic for calculations. An implementation based on the use of application specific integrated circuits (ASIC) is also possible.
A simplified balancing method may be employed instead of using continuously variable phase shifts for the balancing functions. In this implementation, one of n pre-defined discrete values of the relative phase shifts is assigned to each cell, depending on its state of the charge. This way computational overhead is minimized.
To verify the previously described concepts, a 4-cell, 200 W experimental setup was built and tested. At the input, four 6V, 12 AH Lead-Acid cells were used. The DAB stages operated at a switching frequency of 100 kHz and provided a 42 V regulated output. The component values for the power stage of
The controller of this setup was implemented with an FPGA system. For test purposes the system was largely over-designed allowing an opportunity to verify operation of the assisting converter at higher power levels. The tests were performed for cell balancing as well as for developing the voltage assist of the capacitor 107. Operation of this converter as a battery charger was also tested. The converter achieved a peak efficiency of 92%.
The discussion above focuses on a system which is connected with a battery composed of electrochemical cells. Such a system might, however, also offer some of its benefits to a solar panel array of photovoltaic modules.
The alert reader will likewise appreciate that while the system is described as connected with a battery of many cells, the system can likewise offer its benefits in the case of a single cell. In such a case it provides a more efficient DC-to-DC converter because less than all of the power is being passed through the converter.
It is interesting to consider the ability of this system to tolerate any of several possible failure modes. As mentioned above, if a single cell were to fail “open”, a suitably sized capacitor 141 may permit continued system function by stepping into the shoes of the failed cell.
In many prior-art systems, a capacitor is placed in parallel with the load, at the output of a step-up (boost) stage (for example within block 103 in
In sum, a new system level architecture for providing both battery balancing and step-up voltage functions has been described. The architecture is based on an “assisting converter” concept where a low-power converter is used merely to provide a voltage that is added to the battery pack voltage to yield the desired output. The assisting converter can also provide cell balancing. In comparison with conventional systems this architecture drastically reduces the power processing requirements of the step-up power stage and it relaxes the requirements regarding converter power processing efficiency. An implementation of this concept based on multi-input isolated dual active bridge topology (DAB) has been demonstrated. In comparison with a single step-up stage the multi-input DAB allows operation at a higher switching frequency, allows implementation with lower voltage rating low-cost components, and provides better power processing efficiency.
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/US2013/056917 | 8/27/2013 | WO | 00 | 3/5/2014 |
Number | Date | Country | |
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61693644 | Aug 2012 | US | |
61867956 | Aug 2013 | US |